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diff --git a/include/asm-xtensa/xtensa/xt2000.h b/include/asm-xtensa/xtensa/xt2000.h
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1#ifndef _INC_XT2000_H_
2#define _INC_XT2000_H_
3
4/*
5 * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
6 *
7 * include/asm-xtensa/xtensa/xt2000.h - Definitions specific to the
8 * Tensilica XT2000 Emulation Board
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 *
14 * Copyright (C) 2002 Tensilica Inc.
15 */
16
17
18#include <xtensa/config/core.h>
19#include <xtensa/config/system.h>
20
21
22/*
23 * Default assignment of XT2000 devices to external interrupts.
24 */
25
26/* Ethernet interrupt: */
27#ifdef XCHAL_EXTINT3_NUM
28#define SONIC83934_INTNUM XCHAL_EXTINT3_NUM
29#define SONIC83934_INTLEVEL XCHAL_EXTINT3_LEVEL
30#define SONIC83934_INTMASK XCHAL_EXTINT3_MASK
31#else
32#define SONIC83934_INTMASK 0
33#endif
34
35/* DUART channel 1 interrupt (P1 - console): */
36#ifdef XCHAL_EXTINT4_NUM
37#define DUART16552_1_INTNUM XCHAL_EXTINT4_NUM
38#define DUART16552_1_INTLEVEL XCHAL_EXTINT4_LEVEL
39#define DUART16552_1_INTMASK XCHAL_EXTINT4_MASK
40#else
41#define DUART16552_1_INTMASK 0
42#endif
43
44/* DUART channel 2 interrupt (P2 - 2nd serial port): */
45#ifdef XCHAL_EXTINT5_NUM
46#define DUART16552_2_INTNUM XCHAL_EXTINT5_NUM
47#define DUART16552_2_INTLEVEL XCHAL_EXTINT5_LEVEL
48#define DUART16552_2_INTMASK XCHAL_EXTINT5_MASK
49#else
50#define DUART16552_2_INTMASK 0
51#endif
52
53/* FPGA-combined PCI/etc interrupts: */
54#ifdef XCHAL_EXTINT6_NUM
55#define XT2000_FPGAPCI_INTNUM XCHAL_EXTINT6_NUM
56#define XT2000_FPGAPCI_INTLEVEL XCHAL_EXTINT6_LEVEL
57#define XT2000_FPGAPCI_INTMASK XCHAL_EXTINT6_MASK
58#else
59#define XT2000_FPGAPCI_INTMASK 0
60#endif
61
62
63
64/*
65 * Device addresses.
66 *
67 * Note: for endianness-independence, use 32-bit loads and stores for all
68 * register accesses to Ethernet, DUART and LED devices. Undefined bits
69 * may need to be masked out if needed when reading if the actual register
70 * size is smaller than 32 bits.
71 *
72 * Note: XT2000 bus byte lanes are defined in terms of msbyte and lsbyte
73 * relative to the processor. So 32-bit registers are accessed consistently
74 * from both big and little endian processors. However, this means byte
75 * sequences are not consistent between big and little endian processors.
76 * This is fine for RAM, and for ROM if ROM is created for a specific
77 * processor (and thus has correct byte sequences). However this may be
78 * unexpected for Flash, which might contain a file-system that one wants
79 * to use for multiple processor configurations (eg. the Flash might contain
80 * the Ethernet card's address, endianness-independent application data, etc).
81 * That is, byte sequences written in Flash by a core of a given endianness
82 * will be byte-swapped when seen by a core of the other endianness.
83 * Someone implementing an endianness-independent Flash file system will
84 * likely handle this byte-swapping issue in the Flash driver software.
85 */
86
87#define DUART16552_XTAL_FREQ 18432000 /* crystal frequency in Hz */
88#define XTBOARD_FLASH_MAXSIZE 0x4000000 /* 64 MB (max; depends on what is socketed!) */
89#define XTBOARD_EPROM_MAXSIZE 0x0400000 /* 4 MB (max; depends on what is socketed!) */
90#define XTBOARD_EEPROM_MAXSIZE 0x0080000 /* 512 kB (max; depends on what is socketed!) */
91#define XTBOARD_ASRAM_SIZE 0x0100000 /* 1 MB */
92#define XTBOARD_PCI_MEM_SIZE 0x8000000 /* 128 MB (allocated) */
93#define XTBOARD_PCI_IO_SIZE 0x1000000 /* 16 MB (allocated) */
94
95#ifdef XSHAL_IOBLOCK_BYPASS_PADDR
96/* PCI memory space: */
97# define XTBOARD_PCI_MEM_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0000000)
98/* Socketed Flash (eg. 2 x 16-bit devices): */
99# define XTBOARD_FLASH_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x8000000)
100/* PCI I/O space: */
101# define XTBOARD_PCI_IO_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xC000000)
102/* V3 PCI interface chip register/config space: */
103# define XTBOARD_V3PCI_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xD000000)
104/* Bus Interface registers: */
105# define XTBOARD_BUSINT_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xD010000)
106/* FPGA registers: */
107# define XT2000_FPGAREGS_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xD020000)
108/* SONIC SN83934 Ethernet controller/transceiver: */
109# define SONIC83934_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xD030000)
110/* 8-character bitmapped LED display: */
111# define XTBOARD_LED_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xD040000)
112/* National-Semi PC16552D DUART: */
113# define DUART16552_1_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xD050020) /* channel 1 (P1 - console) */
114# define DUART16552_2_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xD050000) /* channel 2 (P2) */
115/* Asynchronous Static RAM: */
116# define XTBOARD_ASRAM_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xD400000)
117/* 8-bit EEPROM: */
118# define XTBOARD_EEPROM_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xD600000)
119/* 2 x 16-bit EPROMs: */
120# define XTBOARD_EPROM_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0xD800000)
121#endif /* XSHAL_IOBLOCK_BYPASS_PADDR */
122
123/* These devices might be accessed cached: */
124#ifdef XSHAL_IOBLOCK_CACHED_PADDR
125# define XTBOARD_PCI_MEM_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0000000)
126# define XTBOARD_FLASH_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x8000000)
127# define XTBOARD_ASRAM_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0xD400000)
128# define XTBOARD_EEPROM_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0xD600000)
129# define XTBOARD_EPROM_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0xD800000)
130#endif /* XSHAL_IOBLOCK_CACHED_PADDR */
131
132
133/*** Same thing over again, this time with virtual addresses: ***/
134
135#ifdef XSHAL_IOBLOCK_BYPASS_VADDR
136/* PCI memory space: */
137# define XTBOARD_PCI_MEM_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0000000)
138/* Socketed Flash (eg. 2 x 16-bit devices): */
139# define XTBOARD_FLASH_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x8000000)
140/* PCI I/O space: */
141# define XTBOARD_PCI_IO_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xC000000)
142/* V3 PCI interface chip register/config space: */
143# define XTBOARD_V3PCI_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xD000000)
144/* Bus Interface registers: */
145# define XTBOARD_BUSINT_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xD010000)
146/* FPGA registers: */
147# define XT2000_FPGAREGS_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xD020000)
148/* SONIC SN83934 Ethernet controller/transceiver: */
149# define SONIC83934_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xD030000)
150/* 8-character bitmapped LED display: */
151# define XTBOARD_LED_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xD040000)
152/* National-Semi PC16552D DUART: */
153# define DUART16552_1_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xD050020) /* channel 1 (P1 - console) */
154# define DUART16552_2_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xD050000) /* channel 2 (P2) */
155/* Asynchronous Static RAM: */
156# define XTBOARD_ASRAM_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xD400000)
157/* 8-bit EEPROM: */
158# define XTBOARD_EEPROM_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xD600000)
159/* 2 x 16-bit EPROMs: */
160# define XTBOARD_EPROM_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0xD800000)
161#endif /* XSHAL_IOBLOCK_BYPASS_VADDR */
162
163/* These devices might be accessed cached: */
164#ifdef XSHAL_IOBLOCK_CACHED_VADDR
165# define XTBOARD_PCI_MEM_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0000000)
166# define XTBOARD_FLASH_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x8000000)
167# define XTBOARD_ASRAM_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0xD400000)
168# define XTBOARD_EEPROM_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0xD600000)
169# define XTBOARD_EPROM_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0xD800000)
170#endif /* XSHAL_IOBLOCK_CACHED_VADDR */
171
172
173/* System ROM: */
174#define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE
175#ifdef XSHAL_ROM_VADDR
176#define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR
177#endif
178#ifdef XSHAL_ROM_PADDR
179#define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR
180#endif
181
182/* System RAM: */
183#define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE
184#ifdef XSHAL_RAM_VADDR
185#define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR
186#endif
187#ifdef XSHAL_RAM_PADDR
188#define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR
189#endif
190#define XTBOARD_RAM_BYPASS_VADDR XSHAL_RAM_BYPASS_VADDR
191#define XTBOARD_RAM_BYPASS_PADDR XSHAL_RAM_BYPASS_PADDR
192
193
194
195/*
196 * Things that depend on device addresses.
197 */
198
199
200#define XTBOARD_CACHEATTR_WRITEBACK XSHAL_XT2000_CACHEATTR_WRITEBACK
201#define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_XT2000_CACHEATTR_WRITEALLOC
202#define XTBOARD_CACHEATTR_WRITETHRU XSHAL_XT2000_CACHEATTR_WRITETHRU
203#define XTBOARD_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS
204#define XTBOARD_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT
205
206#define XTBOARD_BUSINT_PIPE_REGIONS XSHAL_XT2000_PIPE_REGIONS
207#define XTBOARD_BUSINT_SDRAM_REGIONS XSHAL_XT2000_SDRAM_REGIONS
208
209
210
211/*
212 * BusLogic (FPGA) registers.
213 * All these registers are normally accessed using 32-bit loads/stores.
214 */
215
216/* Register offsets: */
217#define XT2000_DATECD_OFS 0x00 /* date code (read-only) */
218#define XT2000_STSREG_OFS 0x04 /* status (read-only) */
219#define XT2000_SYSLED_OFS 0x08 /* system LED */
220#define XT2000_WRPROT_OFS 0x0C /* write protect */
221#define XT2000_SWRST_OFS 0x10 /* software reset */
222#define XT2000_SYSRST_OFS 0x14 /* system (peripherals) reset */
223#define XT2000_IMASK_OFS 0x18 /* interrupt mask */
224#define XT2000_ISTAT_OFS 0x1C /* interrupt status */
225#define XT2000_V3CFG_OFS 0x20 /* V3 config (V320 PCI) */
226
227/* Physical register addresses: */
228#ifdef XT2000_FPGAREGS_PADDR
229#define XT2000_DATECD_PADDR (XT2000_FPGAREGS_PADDR+XT2000_DATECD_OFS)
230#define XT2000_STSREG_PADDR (XT2000_FPGAREGS_PADDR+XT2000_STSREG_OFS)
231#define XT2000_SYSLED_PADDR (XT2000_FPGAREGS_PADDR+XT2000_SYSLED_OFS)
232#define XT2000_WRPROT_PADDR (XT2000_FPGAREGS_PADDR+XT2000_WRPROT_OFS)
233#define XT2000_SWRST_PADDR (XT2000_FPGAREGS_PADDR+XT2000_SWRST_OFS)
234#define XT2000_SYSRST_PADDR (XT2000_FPGAREGS_PADDR+XT2000_SYSRST_OFS)
235#define XT2000_IMASK_PADDR (XT2000_FPGAREGS_PADDR+XT2000_IMASK_OFS)
236#define XT2000_ISTAT_PADDR (XT2000_FPGAREGS_PADDR+XT2000_ISTAT_OFS)
237#define XT2000_V3CFG_PADDR (XT2000_FPGAREGS_PADDR+XT2000_V3CFG_OFS)
238#endif
239
240/* Virtual register addresses: */
241#ifdef XT2000_FPGAREGS_VADDR
242#define XT2000_DATECD_VADDR (XT2000_FPGAREGS_VADDR+XT2000_DATECD_OFS)
243#define XT2000_STSREG_VADDR (XT2000_FPGAREGS_VADDR+XT2000_STSREG_OFS)
244#define XT2000_SYSLED_VADDR (XT2000_FPGAREGS_VADDR+XT2000_SYSLED_OFS)
245#define XT2000_WRPROT_VADDR (XT2000_FPGAREGS_VADDR+XT2000_WRPROT_OFS)
246#define XT2000_SWRST_VADDR (XT2000_FPGAREGS_VADDR+XT2000_SWRST_OFS)
247#define XT2000_SYSRST_VADDR (XT2000_FPGAREGS_VADDR+XT2000_SYSRST_OFS)
248#define XT2000_IMASK_VADDR (XT2000_FPGAREGS_VADDR+XT2000_IMASK_OFS)
249#define XT2000_ISTAT_VADDR (XT2000_FPGAREGS_VADDR+XT2000_ISTAT_OFS)
250#define XT2000_V3CFG_VADDR (XT2000_FPGAREGS_VADDR+XT2000_V3CFG_OFS)
251/* Register access (for C code): */
252#define XT2000_DATECD_REG (*(volatile unsigned*) XT2000_DATECD_VADDR)
253#define XT2000_STSREG_REG (*(volatile unsigned*) XT2000_STSREG_VADDR)
254#define XT2000_SYSLED_REG (*(volatile unsigned*) XT2000_SYSLED_VADDR)
255#define XT2000_WRPROT_REG (*(volatile unsigned*) XT2000_WRPROT_VADDR)
256#define XT2000_SWRST_REG (*(volatile unsigned*) XT2000_SWRST_VADDR)
257#define XT2000_SYSRST_REG (*(volatile unsigned*) XT2000_SYSRST_VADDR)
258#define XT2000_IMASK_REG (*(volatile unsigned*) XT2000_IMASK_VADDR)
259#define XT2000_ISTAT_REG (*(volatile unsigned*) XT2000_ISTAT_VADDR)
260#define XT2000_V3CFG_REG (*(volatile unsigned*) XT2000_V3CFG_VADDR)
261#endif
262
263/* DATECD (date code) bit fields: */
264
265/* BCD-coded month (01..12): */
266#define XT2000_DATECD_MONTH_SHIFT 24
267#define XT2000_DATECD_MONTH_BITS 8
268#define XT2000_DATECD_MONTH_MASK 0xFF000000
269/* BCD-coded day (01..31): */
270#define XT2000_DATECD_DAY_SHIFT 16
271#define XT2000_DATECD_DAY_BITS 8
272#define XT2000_DATECD_DAY_MASK 0x00FF0000
273/* BCD-coded year (2001..9999): */
274#define XT2000_DATECD_YEAR_SHIFT 0
275#define XT2000_DATECD_YEAR_BITS 16
276#define XT2000_DATECD_YEAR_MASK 0x0000FFFF
277
278/* STSREG (status) bit fields: */
279
280/* Switch SW3 setting bit fields (0=off/up, 1=on/down): */
281#define XT2000_STSREG_SW3_SHIFT 0
282#define XT2000_STSREG_SW3_BITS 4
283#define XT2000_STSREG_SW3_MASK 0x0000000F
284/* Boot-select bits of switch SW3: */
285#define XT2000_STSREG_BOOTSEL_SHIFT 0
286#define XT2000_STSREG_BOOTSEL_BITS 2
287#define XT2000_STSREG_BOOTSEL_MASK 0x00000003
288/* Boot-select values: */
289#define XT2000_STSREG_BOOTSEL_FLASH 0
290#define XT2000_STSREG_BOOTSEL_EPROM16 1
291#define XT2000_STSREG_BOOTSEL_PROM8 2
292#define XT2000_STSREG_BOOTSEL_ASRAM 3
293/* User-defined bits of switch SW3: */
294#define XT2000_STSREG_SW3_2_SHIFT 2
295#define XT2000_STSREG_SW3_2_MASK 0x00000004
296#define XT2000_STSREG_SW3_3_SHIFT 3
297#define XT2000_STSREG_SW3_3_MASK 0x00000008
298
299/* SYSLED (system LED) bit fields: */
300
301/* LED control bit (0=off, 1=on): */
302#define XT2000_SYSLED_LEDON_SHIFT 0
303#define XT2000_SYSLED_LEDON_MASK 0x00000001
304
305/* WRPROT (write protect) bit fields (0=writable, 1=write-protected [default]): */
306
307/* Flash write protect: */
308#define XT2000_WRPROT_FLWP_SHIFT 0
309#define XT2000_WRPROT_FLWP_MASK 0x00000001
310/* Reserved but present write protect bits: */
311#define XT2000_WRPROT_WRP_SHIFT 1
312#define XT2000_WRPROT_WRP_BITS 7
313#define XT2000_WRPROT_WRP_MASK 0x000000FE
314
315/* SWRST (software reset; allows s/w to generate power-on equivalent reset): */
316
317/* Software reset bits: */
318#define XT2000_SWRST_SWR_SHIFT 0
319#define XT2000_SWRST_SWR_BITS 16
320#define XT2000_SWRST_SWR_MASK 0x0000FFFF
321/* Software reset value -- writing this value resets the board: */
322#define XT2000_SWRST_RESETVALUE 0x0000DEAD
323
324/* SYSRST (system reset; controls reset of individual peripherals): */
325
326/* All-device reset: */
327#define XT2000_SYSRST_ALL_SHIFT 0
328#define XT2000_SYSRST_ALL_BITS 4
329#define XT2000_SYSRST_ALL_MASK 0x0000000F
330/* HDSP-2534 LED display reset (1=reset, 0=nothing): */
331#define XT2000_SYSRST_LED_SHIFT 0
332#define XT2000_SYSRST_LED_MASK 0x00000001
333/* Sonic DP83934 Ethernet controller reset (1=reset, 0=nothing): */
334#define XT2000_SYSRST_SONIC_SHIFT 1
335#define XT2000_SYSRST_SONIC_MASK 0x00000002
336/* DP16552 DUART reset (1=reset, 0=nothing): */
337#define XT2000_SYSRST_DUART_SHIFT 2
338#define XT2000_SYSRST_DUART_MASK 0x00000004
339/* V3 V320 PCI bridge controller reset (1=reset, 0=nothing): */
340#define XT2000_SYSRST_V3_SHIFT 3
341#define XT2000_SYSRST_V3_MASK 0x00000008
342
343/* IMASK (interrupt mask; 0=disable, 1=enable): */
344/* ISTAT (interrupt status; 0=inactive, 1=pending): */
345
346/* PCI INTP interrupt: */
347#define XT2000_INTMUX_PCI_INTP_SHIFT 2
348#define XT2000_INTMUX_PCI_INTP_MASK 0x00000004
349/* PCI INTS interrupt: */
350#define XT2000_INTMUX_PCI_INTS_SHIFT 3
351#define XT2000_INTMUX_PCI_INTS_MASK 0x00000008
352/* PCI INTD interrupt: */
353#define XT2000_INTMUX_PCI_INTD_SHIFT 4
354#define XT2000_INTMUX_PCI_INTD_MASK 0x00000010
355/* V320 PCI controller interrupt: */
356#define XT2000_INTMUX_V3_SHIFT 5
357#define XT2000_INTMUX_V3_MASK 0x00000020
358/* PCI ENUM interrupt: */
359#define XT2000_INTMUX_PCI_ENUM_SHIFT 6
360#define XT2000_INTMUX_PCI_ENUM_MASK 0x00000040
361/* PCI DEG interrupt: */
362#define XT2000_INTMUX_PCI_DEG_SHIFT 7
363#define XT2000_INTMUX_PCI_DEG_MASK 0x00000080
364
365/* V3CFG (V3 config, V320 PCI controller): */
366
367/* V3 address control (0=pass-thru, 1=V3 address bits 31:28 set to 4'b0001 [default]): */
368#define XT2000_V3CFG_V3ADC_SHIFT 0
369#define XT2000_V3CFG_V3ADC_MASK 0x00000001
370
371/* I2C Devices */
372
373#define XT2000_I2C_RTC_ID 0x68
374#define XT2000_I2C_NVRAM0_ID 0x56 /* 1st 256 byte block */
375#define XT2000_I2C_NVRAM1_ID 0x57 /* 2nd 256 byte block */
376
377/* NVRAM Board Info structure: */
378
379#define XT2000_NVRAM_SIZE 512
380
381#define XT2000_NVRAM_BINFO_START 0x100
382#define XT2000_NVRAM_BINFO_SIZE 0x20
383#define XT2000_NVRAM_BINFO_VERSION 0x10 /* version 1.0 */
384#if 0
385#define XT2000_NVRAM_BINFO_VERSION_OFFSET 0x00
386#define XT2000_NVRAM_BINFO_VERSION_SIZE 0x1
387#define XT2000_NVRAM_BINFO_ETH_ADDR_OFFSET 0x02
388#define XT2000_NVRAM_BINFO_ETH_ADDR_SIZE 0x6
389#define XT2000_NVRAM_BINFO_SN_OFFSET 0x10
390#define XT2000_NVRAM_BINFO_SN_SIZE 0xE
391#define XT2000_NVRAM_BINFO_CRC_OFFSET 0x1E
392#define XT2000_NVRAM_BINFO_CRC_SIZE 0x2
393#endif /*0*/
394
395#if !defined(__ASSEMBLY__) && !defined(_NOCLANGUAGE)
396typedef struct xt2000_nvram_binfo {
397 unsigned char version;
398 unsigned char reserved1;
399 unsigned char eth_addr[6];
400 unsigned char reserved8[8];
401 unsigned char serialno[14];
402 unsigned char crc[2]; /* 16-bit CRC */
403} xt2000_nvram_binfo;
404#endif /*!__ASSEMBLY__ && !_NOCLANGUAGE*/
405
406
407#endif /*_INC_XT2000_H_*/
408
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