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1#ifndef XTENSA_HAL_H
2#define XTENSA_HAL_H
3
4/*
5 * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
6 *
7 * include/asm-xtensa/xtensa/hal.h -- contains a definition of the
8 * Core HAL interface.
9 *
10 * All definitions in this header file are independent of any specific
11 * Xtensa processor configuration. Thus an OS or other software can
12 * include this header file and be compiled into configuration-
13 * independent objects that can be distributed and eventually linked
14 * to the HAL library (libhal.a) to create a configuration-specific
15 * final executable.
16 *
17 * Certain definitions, however, are release-specific -- such as the
18 * XTHAL_RELEASE_xxx macros (or additions made in later releases).
19 *
20 * This file is subject to the terms and conditions of the GNU General Public
21 * License. See the file "COPYING" in the main directory of this archive
22 * for more details.
23 *
24 * Copyright (C) 2002 Tensilica Inc.
25 */
26
27
28/*----------------------------------------------------------------------
29 Constant Definitions
30 (shared with assembly)
31 ----------------------------------------------------------------------*/
32
33/* Software release information (not configuration-specific!): */
34#define XTHAL_RELEASE_MAJOR 1050
35#define XTHAL_RELEASE_MINOR 0
36#define XTHAL_RELEASE_NAME "T1050.0-2002-08-06-eng0"
37#define XTHAL_RELEASE_INTERNAL "2002-08-06-eng0"
38#define XTHAL_REL_T1050 1
39#define XTHAL_REL_T1050_0 1
40#define XTHAL_REL_T1050_0_2002 1
41#define XTHAL_REL_T1050_0_2002_08 1
42#define XTHAL_REL_T1050_0_2002_08_06 1
43#define XTHAL_REL_T1050_0_2002_08_06_ENG0 1
44
45/* HAL version numbers (these names are for backward compatibility): */
46#define XTHAL_MAJOR_REV XTHAL_RELEASE_MAJOR
47#define XTHAL_MINOR_REV XTHAL_RELEASE_MINOR
48/*
49 * A bit of software release history on values of XTHAL_{MAJOR,MINOR}_REV:
50 *
51 * Release MAJOR MINOR Comment
52 * ======= ===== ===== =======
53 * T1015.n n/a n/a (HAL not yet available)
54 * T1020.{0,1,2} 0 1 (HAL beta)
55 * T1020.{3,4} 0 2 First release.
56 * T1020.n (n>4) 0 2 or >3 (TBD)
57 * T1030.0 0 1 (HAL beta)
58 * T1030.{1,2} 0 3 Equivalent to first release.
59 * T1030.n (n>=3) 0 >= 3 (TBD)
60 * T1040.n 1040 n Full CHAL available from T1040.2
61 * T1050.n 1050 n Current release.
62 *
63 *
64 * Note: there is a distinction between the software release with
65 * which something is compiled (accessible using XTHAL_RELEASE_* macros)
66 * and the software release with which the HAL library was compiled
67 * (accessible using Xthal_release_* global variables). This
68 * distinction is particularly relevant for vendors that distribute
69 * configuration-independent binaries (eg. an OS), where their customer
70 * might link it with a HAL of a different Xtensa software release.
71 * In this case, it may be appropriate for the OS to verify at run-time
72 * whether XTHAL_RELEASE_* and Xthal_release_* are compatible.
73 * [Guidelines as to which release is compatible with which are not
74 * currently provided explicitly, but might be inferred from reading
75 * OSKit documentation for all releases -- compatibility is also highly
76 * dependent on which HAL features are used. Each release is usually
77 * backward compatible, with very few exceptions if any.]
78 *
79 * Notes:
80 * Tornado 2.0 supported in T1020.3+, T1030.1+, and T1040.{0,1} only.
81 * Tornado 2.0.2 supported in T1040.2+, and T1050.
82 * Compile-time HAL port of NucleusPlus supported by T1040.2+ and T1050.
83 */
84
85
86/*
87 * Architectural limits, independent of configuration.
88 * Note that these are ISA-defined limits, not micro-architecture implementation
89 * limits enforced by the Xtensa Processor Generator (which may be stricter than
90 * these below).
91 */
92#define XTHAL_MAX_CPS 8 /* max number of coprocessors (0..7) */
93#define XTHAL_MAX_INTERRUPTS 32 /* max number of interrupts (0..31) */
94#define XTHAL_MAX_INTLEVELS 16 /* max number of interrupt levels (0..15) */
95 /* (as of T1040, implementation limit is 7: 0..6) */
96#define XTHAL_MAX_TIMERS 4 /* max number of timers (CCOMPARE0..CCOMPARE3) */
97 /* (as of T1040, implementation limit is 3: 0..2) */
98
99/* Misc: */
100#define XTHAL_LITTLEENDIAN 0
101#define XTHAL_BIGENDIAN 1
102
103
104/* Interrupt types: */
105#define XTHAL_INTTYPE_UNCONFIGURED 0
106#define XTHAL_INTTYPE_SOFTWARE 1
107#define XTHAL_INTTYPE_EXTERN_EDGE 2
108#define XTHAL_INTTYPE_EXTERN_LEVEL 3
109#define XTHAL_INTTYPE_TIMER 4
110#define XTHAL_INTTYPE_NMI 5
111#define XTHAL_MAX_INTTYPES 6 /* number of interrupt types */
112
113/* Timer related: */
114#define XTHAL_TIMER_UNCONFIGURED -1 /* Xthal_timer_interrupt[] value for non-existent timers */
115#define XTHAL_TIMER_UNASSIGNED XTHAL_TIMER_UNCONFIGURED /* (for backwards compatibility only) */
116
117
118/* Access Mode bits (tentative): */ /* bit abbr unit short_name PPC equ - Description */
119#define XTHAL_AMB_EXCEPTION 0 /* 001 E EX fls: EXception none - generate exception on any access (aka "illegal") */
120#define XTHAL_AMB_HITCACHE 1 /* 002 C CH fls: use Cache on Hit ~(I CI) - use cache on hit -- way from tag match [or H HC, or U UC] (ISA: same, except for Isolate case) */
121#define XTHAL_AMB_ALLOCATE 2 /* 004 A AL fl?: ALlocate none - refill cache on miss -- way from LRU [or F FI fill] (ISA: Read/Write Miss Refill) */
122#define XTHAL_AMB_WRITETHRU 3 /* 008 W WT --s: WriteThrough W WT - store immediately to memory (ISA: same) */
123#define XTHAL_AMB_ISOLATE 4 /* 010 I IS fls: ISolate none - use cache regardless of hit-vs-miss -- way from vaddr (ISA: use-cache-on-miss+hit) */
124#define XTHAL_AMB_GUARD 5 /* 020 G GU ?l?: GUard G * - non-speculative; spec/replay refs not permitted */
125#if 0
126#define XTHAL_AMB_ORDERED x /* 000 O OR fls: ORdered G * - mem accesses cannot be out of order */
127#define XTHAL_AMB_FUSEWRITES x /* 000 F FW --s: FuseWrites none - allow combining/merging multiple writes (to same datapath data unit) into one (implied by writeback) */
128#define XTHAL_AMB_COHERENT x /* 000 M MC fl?: Mem/MP Coherent M - on reads, other CPUs/bus-masters may need to supply data */
129#define XTHAL_AMB_TRUSTED x /* 000 T TR ?l?: TRusted none - memory will not bus error (if it does, handle as fatal imprecise interrupt) */
130#define XTHAL_AMB_PREFETCH x /* 000 P PR fl?: PRefetch none - on refill, read line+1 into prefetch buffers */
131#define XTHAL_AMB_STREAM x /* 000 S ST ???: STreaming none - access one of N stream buffers */
132#endif /*0*/
133
134#define XTHAL_AM_EXCEPTION (1<<XTHAL_AMB_EXCEPTION)
135#define XTHAL_AM_HITCACHE (1<<XTHAL_AMB_HITCACHE)
136#define XTHAL_AM_ALLOCATE (1<<XTHAL_AMB_ALLOCATE)
137#define XTHAL_AM_WRITETHRU (1<<XTHAL_AMB_WRITETHRU)
138#define XTHAL_AM_ISOLATE (1<<XTHAL_AMB_ISOLATE)
139#define XTHAL_AM_GUARD (1<<XTHAL_AMB_GUARD)
140#if 0
141#define XTHAL_AM_ORDERED (1<<XTHAL_AMB_ORDERED)
142#define XTHAL_AM_FUSEWRITES (1<<XTHAL_AMB_FUSEWRITES)
143#define XTHAL_AM_COHERENT (1<<XTHAL_AMB_COHERENT)
144#define XTHAL_AM_TRUSTED (1<<XTHAL_AMB_TRUSTED)
145#define XTHAL_AM_PREFETCH (1<<XTHAL_AMB_PREFETCH)
146#define XTHAL_AM_STREAM (1<<XTHAL_AMB_STREAM)
147#endif /*0*/
148
149/*
150 * Allowed Access Modes (bit combinations).
151 *
152 * Columns are:
153 * "FOGIWACE"
154 * Access mode bits (see XTHAL_AMB_xxx above).
155 * <letter> = bit is set
156 * '-' = bit is clear
157 * '.' = bit is irrelevant / don't care, as follows:
158 * E=1 makes all others irrelevant
159 * W,F relevant only for stores
160 * "2345"
161 * Indicates which Xtensa releases support the corresponding
162 * access mode. Releases for each character column are:
163 * 2 = prior to T1020.2: T1015 (V1.5), T1020.0, T1020.1
164 * 3 = T1020.2 and later: T1020.2+, T1030
165 * 4 = T1040
166 * 5 = T1050 (maybe)
167 * And the character column contents are:
168 * <number> = support by release(s)
169 * "." = unsupported by release(s)
170 * "?" = support unknown
171 */
172 /* FOGIWACE 2345 */
173/* For instruction fetch: */
174#define XTHAL_FAM_EXCEPTION 0x001 /* .......E 2345 exception */
175#define XTHAL_FAM_ISOLATE 0x012 /* .--I.-C- .... isolate */
176#define XTHAL_FAM_BYPASS 0x000 /* .---.--- 2345 bypass */
177#define XTHAL_FAM_NACACHED 0x002 /* .---.-C- .... cached no-allocate (frozen) */
178#define XTHAL_FAM_CACHED 0x006 /* .---.AC- 2345 cached */
179/* For data load: */
180#define XTHAL_LAM_EXCEPTION 0x001 /* .......E 2345 exception */
181#define XTHAL_LAM_ISOLATE 0x012 /* .--I.-C- 2345 isolate */
182#define XTHAL_LAM_BYPASS 0x000 /* .O--.--- 2... bypass speculative */
183#define XTHAL_LAM_BYPASSG 0x020 /* .OG-.--- .345 bypass guarded */
184#define XTHAL_LAM_NACACHED 0x002 /* .O--.-C- 2... cached no-allocate speculative */
185#define XTHAL_LAM_NACACHEDG 0x022 /* .OG-.-C- .345 cached no-allocate guarded */
186#define XTHAL_LAM_CACHED 0x006 /* .---.AC- 2345 cached speculative */
187#define XTHAL_LAM_CACHEDG 0x026 /* .?G-.AC- .... cached guarded */
188/* For data store: */
189#define XTHAL_SAM_EXCEPTION 0x001 /* .......E 2345 exception */
190#define XTHAL_SAM_ISOLATE 0x032 /* .-GI--C- 2345 isolate */
191#define XTHAL_SAM_BYPASS 0x028 /* -OG-W--- 2345 bypass */
192/*efine XTHAL_SAM_BYPASSF 0x028*/ /* F-G-W--- ...? bypass write-combined */
193#define XTHAL_SAM_WRITETHRU 0x02A /* -OG-W-C- 234? writethrough */
194/*efine XTHAL_SAM_WRITETHRUF 0x02A*/ /* F-G-W-C- ...5 writethrough write-combined */
195#define XTHAL_SAM_WRITEALLOC 0x02E /* -OG-WAC- ...? writethrough-allocate */
196/*efine XTHAL_SAM_WRITEALLOCF 0x02E*/ /* F-G-WAC- ...? writethrough-allocate write-combined */
197#define XTHAL_SAM_WRITEBACK 0x026 /* F-G--AC- ...5 writeback */
198
199#if 0
200/*
201 Cache attribute encoding for CACHEATTR (per ISA):
202 (Note: if this differs from ISA Ref Manual, ISA has precedence)
203
204 Inst-fetches Loads Stores
205 ------------- ------------ -------------
2060x0 FCA_EXCEPTION ?LCA_NACACHED_G* SCA_WRITETHRU "uncached"
2070x1 FCA_CACHED LCA_CACHED SCA_WRITETHRU cached
2080x2 FCA_BYPASS LCA_BYPASS_G* SCA_BYPASS bypass
2090x3 FCA_CACHED LCA_CACHED SCA_WRITEALLOCF write-allocate
210 or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented)
2110x4 FCA_CACHED LCA_CACHED SCA_WRITEBACK write-back
212 or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented)
2130x5..D FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION (reserved)
2140xE FCA_EXCEPTION LCA_ISOLATE SCA_ISOLATE isolate
2150xF FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION illegal
216 * Prior to T1020.2?, guard feature not supported, this defaulted to speculative (no _G)
217*/
218#endif /*0*/
219
220
221#if !defined(__ASSEMBLY__) && !defined(_NOCLANGUAGE)
222#ifdef __cplusplus
223extern "C" {
224#endif
225
226/*----------------------------------------------------------------------
227 HAL
228 ----------------------------------------------------------------------*/
229
230/* Constant to be checked in build = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV */
231extern const unsigned int Xthal_rev_no;
232
233
234/*----------------------------------------------------------------------
235 Processor State
236 ----------------------------------------------------------------------*/
237/* save & restore the extra processor state */
238extern void xthal_save_extra(void *base);
239extern void xthal_restore_extra(void *base);
240
241extern void xthal_save_cpregs(void *base, int);
242extern void xthal_restore_cpregs(void *base, int);
243
244/*extern void xthal_save_all_extra(void *base);*/
245/*extern void xthal_restore_all_extra(void *base);*/
246
247/* space for processor state */
248extern const unsigned int Xthal_extra_size;
249extern const unsigned int Xthal_extra_align;
250/* space for TIE register files */
251extern const unsigned int Xthal_cpregs_size[XTHAL_MAX_CPS];
252extern const unsigned int Xthal_cpregs_align[XTHAL_MAX_CPS];
253
254/* total of space for the processor state (for Tor2) */
255extern const unsigned int Xthal_all_extra_size;
256extern const unsigned int Xthal_all_extra_align;
257
258/* initialize the extra processor */
259/*extern void xthal_init_extra(void);*/
260/* initialize the TIE coprocessor */
261/*extern void xthal_init_cp(int);*/
262
263/* initialize the extra processor */
264extern void xthal_init_mem_extra(void *);
265/* initialize the TIE coprocessor */
266extern void xthal_init_mem_cp(void *, int);
267
268/* validate & invalidate the TIE register file */
269extern void xthal_validate_cp(int);
270extern void xthal_invalidate_cp(int);
271
272/* the number of TIE coprocessors contiguous from zero (for Tor2) */
273extern const unsigned int Xthal_num_coprocessors;
274
275/* actual number of coprocessors */
276extern const unsigned char Xthal_cp_num;
277/* index of highest numbered coprocessor, plus one */
278extern const unsigned char Xthal_cp_max;
279/* index of highest allowed coprocessor number, per cfg, plus one */
280/*extern const unsigned char Xthal_cp_maxcfg;*/
281/* bitmask of which coprocessors are present */
282extern const unsigned int Xthal_cp_mask;
283
284/* read and write cpenable register */
285extern void xthal_set_cpenable(unsigned);
286extern unsigned xthal_get_cpenable(void);
287
288/* read & write extra state register */
289/*extern int xthal_read_extra(void *base, unsigned reg, unsigned *value);*/
290/*extern int xthal_write_extra(void *base, unsigned reg, unsigned value);*/
291
292/* read & write a TIE coprocessor register */
293/*extern int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value);*/
294/*extern int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value);*/
295
296/* return coprocessor number based on register */
297/*extern int xthal_which_cp(unsigned reg);*/
298
299/*----------------------------------------------------------------------
300 Interrupts
301 ----------------------------------------------------------------------*/
302
303/* the number of interrupt levels */
304extern const unsigned char Xthal_num_intlevels;
305/* the number of interrupts */
306extern const unsigned char Xthal_num_interrupts;
307
308/* mask for level of interrupts */
309extern const unsigned int Xthal_intlevel_mask[XTHAL_MAX_INTLEVELS];
310/* mask for level 0 to N interrupts */
311extern const unsigned int Xthal_intlevel_andbelow_mask[XTHAL_MAX_INTLEVELS];
312
313/* level of each interrupt */
314extern const unsigned char Xthal_intlevel[XTHAL_MAX_INTERRUPTS];
315
316/* type per interrupt */
317extern const unsigned char Xthal_inttype[XTHAL_MAX_INTERRUPTS];
318
319/* masks of each type of interrupt */
320extern const unsigned int Xthal_inttype_mask[XTHAL_MAX_INTTYPES];
321
322/* interrupt numbers assigned to each timer interrupt */
323extern const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS];
324
325/*** Virtual interrupt prioritization: ***/
326
327/* Convert between interrupt levels (as per PS.INTLEVEL) and virtual interrupt priorities: */
328extern unsigned xthal_vpri_to_intlevel(unsigned vpri);
329extern unsigned xthal_intlevel_to_vpri(unsigned intlevel);
330
331/* Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints: */
332extern unsigned xthal_int_enable(unsigned);
333extern unsigned xthal_int_disable(unsigned);
334
335/* Set/get virtual priority of an interrupt: */
336extern int xthal_set_int_vpri(int intnum, int vpri);
337extern int xthal_get_int_vpri(int intnum);
338
339/* Set/get interrupt lockout level for exclusive access to virtual priority data structures: */
340extern void xthal_set_vpri_locklevel(unsigned intlevel);
341extern unsigned xthal_get_vpri_locklevel(void);
342
343/* Set/get current virtual interrupt priority: */
344extern unsigned xthal_set_vpri(unsigned vpri);
345extern unsigned xthal_get_vpri(unsigned vpri);
346extern unsigned xthal_set_vpri_intlevel(unsigned intlevel);
347extern unsigned xthal_set_vpri_lock(void);
348
349
350
351/*----------------------------------------------------------------------
352 Generic Interrupt Trampolining Support
353 ----------------------------------------------------------------------*/
354
355typedef void (XtHalVoidFunc)(void);
356
357/*
358 * Bitmask of interrupts currently trampolining down:
359 */
360extern unsigned Xthal_tram_pending;
361
362/*
363 * Bitmask of which interrupts currently trampolining down
364 * synchronously are actually enabled; this bitmask is necessary
365 * because INTENABLE cannot hold that state (sync-trampolining
366 * interrupts must be kept disabled while trampolining);
367 * in the current implementation, any bit set here is not set
368 * in INTENABLE, and vice-versa; once a sync-trampoline is
369 * handled (at level one), its enable bit must be moved from
370 * here to INTENABLE:
371 */
372extern unsigned Xthal_tram_enabled;
373
374/*
375 * Bitmask of interrupts configured for sync trampolining:
376 */
377extern unsigned Xthal_tram_sync;
378
379
380/* Trampoline support functions: */
381extern unsigned xthal_tram_pending_to_service( void );
382extern void xthal_tram_done( unsigned serviced_mask );
383extern int xthal_tram_set_sync( int intnum, int sync );
384extern XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn );
385
386/* INTENABLE,INTREAD,INTSET,INTCLEAR register access functions: */
387extern unsigned xthal_get_intenable( void );
388extern void xthal_set_intenable( unsigned );
389extern unsigned xthal_get_intread( void );
390extern void xthal_set_intset( unsigned );
391extern void xthal_set_intclear( unsigned );
392
393
394/*----------------------------------------------------------------------
395 Register Windows
396 ----------------------------------------------------------------------*/
397
398/* number of registers in register window */
399extern const unsigned int Xthal_num_aregs;
400extern const unsigned char Xthal_num_aregs_log2;
401
402/* This spill any live register windows (other than the caller's): */
403extern void xthal_window_spill( void );
404
405
406/*----------------------------------------------------------------------
407 Cache
408 ----------------------------------------------------------------------*/
409
410/* size of the cache lines in log2(bytes) */
411extern const unsigned char Xthal_icache_linewidth;
412extern const unsigned char Xthal_dcache_linewidth;
413/* size of the cache lines in bytes */
414extern const unsigned short Xthal_icache_linesize;
415extern const unsigned short Xthal_dcache_linesize;
416/* number of cache sets in log2(lines per way) */
417extern const unsigned char Xthal_icache_setwidth;
418extern const unsigned char Xthal_dcache_setwidth;
419/* cache set associativity (number of ways) */
420extern const unsigned int Xthal_icache_ways;
421extern const unsigned int Xthal_dcache_ways;
422/* size of the caches in bytes (ways * 2^(linewidth + setwidth)) */
423extern const unsigned int Xthal_icache_size;
424extern const unsigned int Xthal_dcache_size;
425/* cache features */
426extern const unsigned char Xthal_dcache_is_writeback;
427extern const unsigned char Xthal_icache_line_lockable;
428extern const unsigned char Xthal_dcache_line_lockable;
429
430/* cache attribute register control (used by other HAL routines) */
431extern unsigned xthal_get_cacheattr( void );
432extern unsigned xthal_get_icacheattr( void );
433extern unsigned xthal_get_dcacheattr( void );
434extern void xthal_set_cacheattr( unsigned );
435extern void xthal_set_icacheattr( unsigned );
436extern void xthal_set_dcacheattr( unsigned );
437
438/* initialize cache support (must be called once at startup, before all other cache calls) */
439/*extern void xthal_cache_startinit( void );*/
440/* reset caches */
441/*extern void xthal_icache_reset( void );*/
442/*extern void xthal_dcache_reset( void );*/
443/* enable caches */
444extern void xthal_icache_enable( void ); /* DEPRECATED */
445extern void xthal_dcache_enable( void ); /* DEPRECATED */
446/* disable caches */
447extern void xthal_icache_disable( void ); /* DEPRECATED */
448extern void xthal_dcache_disable( void ); /* DEPRECATED */
449
450/* invalidate the caches */
451extern void xthal_icache_all_invalidate( void );
452extern void xthal_dcache_all_invalidate( void );
453extern void xthal_icache_region_invalidate( void *addr, unsigned size );
454extern void xthal_dcache_region_invalidate( void *addr, unsigned size );
455extern void xthal_icache_line_invalidate(void *addr);
456extern void xthal_dcache_line_invalidate(void *addr);
457/* write dirty data back */
458extern void xthal_dcache_all_writeback( void );
459extern void xthal_dcache_region_writeback( void *addr, unsigned size );
460extern void xthal_dcache_line_writeback(void *addr);
461/* write dirty data back and invalidate */
462extern void xthal_dcache_all_writeback_inv( void );
463extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size );
464extern void xthal_dcache_line_writeback_inv(void *addr);
465/* prefetch and lock specified memory range into cache */
466extern void xthal_icache_region_lock( void *addr, unsigned size );
467extern void xthal_dcache_region_lock( void *addr, unsigned size );
468extern void xthal_icache_line_lock(void *addr);
469extern void xthal_dcache_line_lock(void *addr);
470/* unlock from cache */
471extern void xthal_icache_all_unlock( void );
472extern void xthal_dcache_all_unlock( void );
473extern void xthal_icache_region_unlock( void *addr, unsigned size );
474extern void xthal_dcache_region_unlock( void *addr, unsigned size );
475extern void xthal_icache_line_unlock(void *addr);
476extern void xthal_dcache_line_unlock(void *addr);
477
478
479/* sync icache and memory */
480extern void xthal_icache_sync( void );
481/* sync dcache and memory */
482extern void xthal_dcache_sync( void );
483
484/*----------------------------------------------------------------------
485 Debug
486 ----------------------------------------------------------------------*/
487
488/* 1 if debug option configured, 0 if not: */
489extern const int Xthal_debug_configured;
490
491/* Number of instruction and data break registers: */
492extern const int Xthal_num_ibreak;
493extern const int Xthal_num_dbreak;
494
495/* Set (plant) and remove software breakpoint, both synchronizing cache: */
496extern unsigned int xthal_set_soft_break(void *addr);
497extern void xthal_remove_soft_break(void *addr, unsigned int);
498
499
500/*----------------------------------------------------------------------
501 Disassembler
502 ----------------------------------------------------------------------*/
503
504/* Max expected size of the return buffer for a disassembled instruction (hint only): */
505#define XTHAL_DISASM_BUFSIZE 80
506
507/* Disassembly option bits for selecting what to return: */
508#define XTHAL_DISASM_OPT_ADDR 0x0001 /* display address */
509#define XTHAL_DISASM_OPT_OPHEX 0x0002 /* display opcode bytes in hex */
510#define XTHAL_DISASM_OPT_OPCODE 0x0004 /* display opcode name (mnemonic) */
511#define XTHAL_DISASM_OPT_PARMS 0x0008 /* display parameters */
512#define XTHAL_DISASM_OPT_ALL 0x0FFF /* display everything */
513
514/* routine to get a string for the disassembled instruction */
515extern int xthal_disassemble( unsigned char *instr_buf, void *tgt_addr,
516 char *buffer, unsigned buflen, unsigned options );
517
518/* routine to get the size of the next instruction. Returns 0 for
519 illegal instruction */
520extern int xthal_disassemble_size( unsigned char *instr_buf );
521
522
523/*----------------------------------------------------------------------
524 Core Counter
525 ----------------------------------------------------------------------*/
526
527/* counter info */
528extern const unsigned char Xthal_have_ccount; /* set if CCOUNT register present */
529extern const unsigned char Xthal_num_ccompare; /* number of CCOMPAREn registers */
530
531/* get CCOUNT register (if not present return 0) */
532extern unsigned xthal_get_ccount(void);
533
534/* set and get CCOMPAREn registers (if not present, get returns 0) */
535extern void xthal_set_ccompare(int, unsigned);
536extern unsigned xthal_get_ccompare(int);
537
538
539/*----------------------------------------------------------------------
540 Instruction/Data RAM/ROM Access
541 ----------------------------------------------------------------------*/
542
543extern void* xthal_memcpy(void *dst, const void *src, unsigned len);
544extern void* xthal_bcopy(const void *src, void *dst, unsigned len);
545
546/*----------------------------------------------------------------------
547 MP Synchronization
548 ----------------------------------------------------------------------*/
549extern int xthal_compare_and_set( int *addr, int test_val, int compare_val );
550extern unsigned xthal_get_prid( void );
551
552/*extern const char Xthal_have_s32c1i;*/
553extern const unsigned char Xthal_have_prid;
554
555
556/*----------------------------------------------------------------------
557 Miscellaneous
558 ----------------------------------------------------------------------*/
559
560extern const unsigned int Xthal_release_major;
561extern const unsigned int Xthal_release_minor;
562extern const char * const Xthal_release_name;
563extern const char * const Xthal_release_internal;
564
565extern const unsigned char Xthal_memory_order;
566extern const unsigned char Xthal_have_windowed;
567extern const unsigned char Xthal_have_density;
568extern const unsigned char Xthal_have_booleans;
569extern const unsigned char Xthal_have_loops;
570extern const unsigned char Xthal_have_nsa;
571extern const unsigned char Xthal_have_minmax;
572extern const unsigned char Xthal_have_sext;
573extern const unsigned char Xthal_have_clamps;
574extern const unsigned char Xthal_have_mac16;
575extern const unsigned char Xthal_have_mul16;
576extern const unsigned char Xthal_have_fp;
577extern const unsigned char Xthal_have_speculation;
578extern const unsigned char Xthal_have_exceptions;
579extern const unsigned char Xthal_xea_version;
580extern const unsigned char Xthal_have_interrupts;
581extern const unsigned char Xthal_have_highlevel_interrupts;
582extern const unsigned char Xthal_have_nmi;
583
584extern const unsigned short Xthal_num_writebuffer_entries;
585
586extern const unsigned int Xthal_build_unique_id;
587/* Release info for hardware targeted by software upgrades: */
588extern const unsigned int Xthal_hw_configid0;
589extern const unsigned int Xthal_hw_configid1;
590extern const unsigned int Xthal_hw_release_major;
591extern const unsigned int Xthal_hw_release_minor;
592extern const char * const Xthal_hw_release_name;
593extern const char * const Xthal_hw_release_internal;
594
595
596/* Internal memories... */
597
598extern const unsigned char Xthal_num_instrom;
599extern const unsigned char Xthal_num_instram;
600extern const unsigned char Xthal_num_datarom;
601extern const unsigned char Xthal_num_dataram;
602extern const unsigned char Xthal_num_xlmi;
603extern const unsigned int Xthal_instrom_vaddr[1];
604extern const unsigned int Xthal_instrom_paddr[1];
605extern const unsigned int Xthal_instrom_size [1];
606extern const unsigned int Xthal_instram_vaddr[1];
607extern const unsigned int Xthal_instram_paddr[1];
608extern const unsigned int Xthal_instram_size [1];
609extern const unsigned int Xthal_datarom_vaddr[1];
610extern const unsigned int Xthal_datarom_paddr[1];
611extern const unsigned int Xthal_datarom_size [1];
612extern const unsigned int Xthal_dataram_vaddr[1];
613extern const unsigned int Xthal_dataram_paddr[1];
614extern const unsigned int Xthal_dataram_size [1];
615extern const unsigned int Xthal_xlmi_vaddr[1];
616extern const unsigned int Xthal_xlmi_paddr[1];
617extern const unsigned int Xthal_xlmi_size [1];
618
619
620
621/*----------------------------------------------------------------------
622 Memory Management Unit
623 ----------------------------------------------------------------------*/
624
625extern const unsigned char Xthal_have_spanning_way;
626extern const unsigned char Xthal_have_identity_map;
627extern const unsigned char Xthal_have_mimic_cacheattr;
628extern const unsigned char Xthal_have_xlt_cacheattr;
629extern const unsigned char Xthal_have_cacheattr;
630extern const unsigned char Xthal_have_tlbs;
631
632extern const unsigned char Xthal_mmu_asid_bits; /* 0 .. 8 */
633extern const unsigned char Xthal_mmu_asid_kernel;
634extern const unsigned char Xthal_mmu_rings; /* 1 .. 4 (perhaps 0 if no MMU and/or no protection?) */
635extern const unsigned char Xthal_mmu_ring_bits;
636extern const unsigned char Xthal_mmu_sr_bits;
637extern const unsigned char Xthal_mmu_ca_bits;
638extern const unsigned int Xthal_mmu_max_pte_page_size;
639extern const unsigned int Xthal_mmu_min_pte_page_size;
640
641extern const unsigned char Xthal_itlb_way_bits;
642extern const unsigned char Xthal_itlb_ways;
643extern const unsigned char Xthal_itlb_arf_ways;
644extern const unsigned char Xthal_dtlb_way_bits;
645extern const unsigned char Xthal_dtlb_ways;
646extern const unsigned char Xthal_dtlb_arf_ways;
647
648/* Convert between virtual and physical addresses (through static maps only): */
649/*** WARNING: these two functions may go away in a future release; don't depend on them! ***/
650extern int xthal_static_v2p( unsigned vaddr, unsigned *paddrp );
651extern int xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached );
652
653#if 0
654/******************* EXPERIMENTAL AND TENTATIVE ONLY ********************/
655
656#define XTHAL_MMU_PAGESZ_COUNT_MAX 8 /* maximum number of different page sizes */
657extern const char Xthal_mmu_pagesz_count; /* 0 .. 8 number of different page sizes configured */
658
659/* Note: the following table doesn't necessarily have page sizes in increasing order: */
660extern const char Xthal_mmu_pagesz_log2[XTHAL_MMU_PAGESZ_COUNT_MAX]; /* 10 .. 28 (0 past count) */
661
662/* Sorted (increasing) table of page sizes, that indexes into the above table: */
663extern const char Xthal_mmu_pagesz_sorted[XTHAL_MMU_PAGESZ_COUNT_MAX]; /* 0 .. 7 (0 past count) */
664
665/*u32 Xthal_virtual_exceptions;*/ /* bitmask of which exceptions execute in virtual mode... */
666
667extern const char Xthal_mmu_pte_pagesz_log2_min; /* ?? minimum page size in PTEs */
668extern const char Xthal_mmu_pte_pagesz_log2_max; /* ?? maximum page size in PTEs */
669
670/* Cache Attribute Bits Implemented by the Cache (part of the cache abstraction) */
671extern const char Xthal_icache_fca_bits_implemented; /* ITLB/UTLB only! */
672extern const char Xthal_dcache_lca_bits_implemented; /* DTLB/UTLB only! */
673extern const char Xthal_dcache_sca_bits_implemented; /* DTLB/UTLB only! */
674
675/* Per TLB Parameters (Instruction, Data, Unified) */
676struct XtHalMmuTlb Xthal_itlb; /* description of MMU I-TLB generic features */
677struct XtHalMmuTlb Xthal_dtlb; /* description of MMU D-TLB generic features */
678struct XtHalMmuTlb Xthal_utlb; /* description of MMU U-TLB generic features */
679
680#define XTHAL_MMU_WAYS_MAX 8 /* maximum number of ways (associativities) for each TLB */
681
682/* Structure for common information described for each possible TLB (instruction, data and unified): */
683typedef struct XtHalMmuTlb {
684 u8 va_bits; /* 32 (number of virtual address bits) */
685 u8 pa_bits; /* 32 (number of physical address bits) */
686 bool tlb_va_indexed; /* 1 (set if TLB is indexed by virtual address) */
687 bool tlb_va_tagged; /* 0 (set if TLB is tagged by virtual address) */
688 bool cache_va_indexed; /* 1 (set if cache is indexed by virtual address) */
689 bool cache_va_tagged; /* 0 (set if cache is tagged by virtual address) */
690 /*bool (whether page tables are traversed in vaddr sorted order, paddr sorted order, ...) */
691 /*u8 (set of available page attribute bits, other than cache attribute bits defined above) */
692 /*u32 (various masks for pages, MMU table/TLB entries, etc.) */
693 u8 way_count; /* 0 .. 8 (number of ways, a.k.a. associativities, for this TLB) */
694 XtHalMmuTlbWay * ways[XTHAL_MMU_WAYS_MAX]; /* pointers to per-way parms for each way */
695} XtHalMmuTlb;
696
697/* Per TLB Way (Per Associativity) Parameters */
698typedef struct XtHalMmuTlbWay {
699 u32 index_count_log2; /* 0 .. 4 */
700 u32 pagesz_mask; /* 0 .. 2^pagesz_count - 1 (each bit corresponds to a size */
701 /* defined in the Xthal_mmu_pagesz_log2[] table) */
702 u32 vpn_const_mask;
703 u32 vpn_const_value;
704 u64 ppn_const_mask; /* future may support pa_bits > 32 */
705 u64 ppn_const_value;
706 u32 ppn_id_mask; /* paddr bits taken directly from vaddr */
707 bool backgnd_match; /* 0 or 1 */
708 /* These are defined in terms of the XTHAL_CACHE_xxx bits: */
709 u8 fca_const_mask; /* ITLB/UTLB only! */
710 u8 fca_const_value; /* ITLB/UTLB only! */
711 u8 lca_const_mask; /* DTLB/UTLB only! */
712 u8 lca_const_value; /* DTLB/UTLB only! */
713 u8 sca_const_mask; /* DTLB/UTLB only! */
714 u8 sca_const_value; /* DTLB/UTLB only! */
715 /* These define an encoding that map 5 bits in TLB and PTE entries to */
716 /* 8 bits (FCA, ITLB), 16 bits (LCA+SCA, DTLB) or 24 bits (FCA+LCA+SCA, UTLB): */
717 /* (they may be moved to struct XtHalMmuTlb) */
718 u8 ca_bits; /* number of bits in TLB/PTE entries for cache attributes */
719 u32 * ca_map; /* pointer to array of 2^ca_bits entries of FCA+LCA+SCA bits */
720} XtHalMmuTlbWay;
721
722/*
723 * The way to determine whether protection support is present in core
724 * is to [look at Xthal_mmu_rings ???].
725 * Give info on memory requirements for MMU tables and other in-memory
726 * data structures (globally, per task, base and per page, etc.) - whatever bounds can be calculated.
727 */
728
729
730/* Default vectors: */
731xthal_immu_fetch_miss_vector
732xthal_dmmu_load_miss_vector
733xthal_dmmu_store_miss_vector
734
735/* Functions called when a fault is detected: */
736typedef void (XtHalMmuFaultFunc)( unsigned vaddr, ...context... );
737/* Or, */
738/* a? = vaddr */
739/* a? = context... */
740/* PS.xxx = xxx */
741XtHalMMuFaultFunc *Xthal_immu_fetch_fault_func;
742XtHalMMuFaultFunc *Xthal_dmmu_load_fault_func;
743XtHalMMuFaultFunc *Xthal_dmmu_store_fault_func;
744
745/* Default Handlers: */
746/* The user and/or kernel exception handlers may jump to these handlers to handle the relevant exceptions,
747 * according to the value of EXCCAUSE. The exact register state on entry to these handlers is TBD. */
748/* When multiple TLB entries match (hit) on the same access: */
749xthal_immu_fetch_multihit_handler
750xthal_dmmu_load_multihit_handler
751xthal_dmmu_store_multihit_handler
752/* Protection violations according to cache attributes, and other cache attribute mismatches: */
753xthal_immu_fetch_attr_handler
754xthal_dmmu_load_attr_handler
755xthal_dmmu_store_attr_handler
756/* Protection violations due to insufficient ring level: */
757xthal_immu_fetch_priv_handler
758xthal_dmmu_load_priv_handler
759xthal_dmmu_store_priv_handler
760/* Alignment exception handlers (if supported by the particular Xtensa MMU configuration): */
761xthal_dmmu_load_align_handler
762xthal_dmmu_store_align_handler
763
764/* Or, alternatively, the OS user and/or kernel exception handlers may simply jump to the
765 * following entry points which will handle any values of EXCCAUSE not handled by the OS: */
766xthal_user_exc_default_handler
767xthal_kernel_exc_default_handler
768
769#endif /*0*/
770
771#ifdef INCLUDE_DEPRECATED_HAL_CODE
772extern const unsigned char Xthal_have_old_exc_arch;
773extern const unsigned char Xthal_have_mmu;
774extern const unsigned int Xthal_num_regs;
775extern const unsigned char Xthal_num_iroms;
776extern const unsigned char Xthal_num_irams;
777extern const unsigned char Xthal_num_droms;
778extern const unsigned char Xthal_num_drams;
779extern const unsigned int Xthal_configid0;
780extern const unsigned int Xthal_configid1;
781#endif
782
783#ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE
784#define XTHAL_24_BIT_BREAK 0x80000000
785#define XTHAL_16_BIT_BREAK 0x40000000
786extern const unsigned short Xthal_ill_inst_16[16];
787#define XTHAL_DEST_REG 0xf0000000 /* Mask for destination register */
788#define XTHAL_DEST_REG_INST 0x08000000 /* Branch address is in register */
789#define XTHAL_DEST_REL_INST 0x04000000 /* Branch address is relative */
790#define XTHAL_RFW_INST 0x00000800
791#define XTHAL_RFUE_INST 0x00000400
792#define XTHAL_RFI_INST 0x00000200
793#define XTHAL_RFE_INST 0x00000100
794#define XTHAL_RET_INST 0x00000080
795#define XTHAL_BREAK_INST 0x00000040
796#define XTHAL_SYSCALL_INST 0x00000020
797#define XTHAL_LOOP_END 0x00000010 /* Not set by xthal_inst_type */
798#define XTHAL_JUMP_INST 0x00000008 /* Call or jump instruction */
799#define XTHAL_BRANCH_INST 0x00000004 /* Branch instruction */
800#define XTHAL_24_BIT_INST 0x00000002
801#define XTHAL_16_BIT_INST 0x00000001
802typedef struct xthal_state {
803 unsigned pc;
804 unsigned ar[16];
805 unsigned lbeg;
806 unsigned lend;
807 unsigned lcount;
808 unsigned extra_ptr;
809 unsigned cpregs_ptr[XTHAL_MAX_CPS];
810} XTHAL_STATE;
811extern unsigned int xthal_inst_type(void *addr);
812extern unsigned int xthal_branch_addr(void *addr);
813extern unsigned int xthal_get_npc(XTHAL_STATE *user_state);
814#endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */
815
816#ifdef __cplusplus
817}
818#endif
819#endif /*!__ASSEMBLY__ */
820
821#endif /*XTENSA_HAL_H*/
822
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