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-rw-r--r--include/asm-xtensa/xtensa/config-linux_be/core.h1270
-rw-r--r--include/asm-xtensa/xtensa/config-linux_be/defs.h270
-rw-r--r--include/asm-xtensa/xtensa/config-linux_be/specreg.h99
-rw-r--r--include/asm-xtensa/xtensa/config-linux_be/system.h198
-rw-r--r--include/asm-xtensa/xtensa/config-linux_be/tie.h275
5 files changed, 0 insertions, 2112 deletions
diff --git a/include/asm-xtensa/xtensa/config-linux_be/core.h b/include/asm-xtensa/xtensa/config-linux_be/core.h
deleted file mode 100644
index d54fe5eb1064..000000000000
--- a/include/asm-xtensa/xtensa/config-linux_be/core.h
+++ /dev/null
@@ -1,1270 +0,0 @@
1/*
2 * xtensa/config/core.h -- HAL definitions that are dependent on CORE configuration
3 *
4 * This header file is sometimes referred to as the "compile-time HAL" or CHAL.
5 * It was generated for a specific Xtensa processor configuration.
6 *
7 * Source for configuration-independent binaries (which link in a
8 * configuration-specific HAL library) must NEVER include this file.
9 * It is perfectly normal, however, for the HAL source itself to include this file.
10 */
11
12/*
13 * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of version 2.1 of the GNU Lesser General Public
17 * License as published by the Free Software Foundation.
18 *
19 * This program is distributed in the hope that it would be useful, but
20 * WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
22 *
23 * Further, this software is distributed without any warranty that it is
24 * free of the rightful claim of any third person regarding infringement
25 * or the like. Any license provided herein, whether implied or
26 * otherwise, applies only to this software file. Patent licenses, if
27 * any, provided herein do not apply to combinations of this program with
28 * other software, or any other product whatsoever.
29 *
30 * You should have received a copy of the GNU Lesser General Public
31 * License along with this program; if not, write the Free Software
32 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
33 * USA.
34 */
35
36
37#ifndef XTENSA_CONFIG_CORE_H
38#define XTENSA_CONFIG_CORE_H
39
40#include <xtensa/hal.h>
41
42
43/*----------------------------------------------------------------------
44 GENERAL
45 ----------------------------------------------------------------------*/
46
47/*
48 * Separators for macros that expand into arrays.
49 * These can be predefined by files that #include this one,
50 * when different separators are required.
51 */
52/* Element separator for macros that expand into 1-dimensional arrays: */
53#ifndef XCHAL_SEP
54#define XCHAL_SEP ,
55#endif
56/* Array separator for macros that expand into 2-dimensional arrays: */
57#ifndef XCHAL_SEP2
58#define XCHAL_SEP2 },{
59#endif
60
61
62/*----------------------------------------------------------------------
63 ENDIANNESS
64 ----------------------------------------------------------------------*/
65
66#define XCHAL_HAVE_BE 1
67#define XCHAL_HAVE_LE 0
68#define XCHAL_MEMORY_ORDER XTHAL_BIGENDIAN
69
70
71/*----------------------------------------------------------------------
72 REGISTER WINDOWS
73 ----------------------------------------------------------------------*/
74
75#define XCHAL_HAVE_WINDOWED 1 /* 1 if windowed registers option configured, 0 otherwise */
76#define XCHAL_NUM_AREGS 64 /* number of physical address regs */
77#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
78
79
80/*----------------------------------------------------------------------
81 ADDRESS ALIGNMENT
82 ----------------------------------------------------------------------*/
83
84/* These apply to a selected set of core load and store instructions only (see ISA): */
85#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* 1 if unaligned loads cause an exception, 0 otherwise */
86#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* 1 if unaligned stores cause an exception, 0 otherwise */
87
88
89/*----------------------------------------------------------------------
90 INTERRUPTS
91 ----------------------------------------------------------------------*/
92
93#define XCHAL_HAVE_INTERRUPTS 1 /* 1 if interrupt option configured, 0 otherwise */
94#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* 1 if high-priority interrupt option configured, 0 otherwise */
95#define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS
96#define XCHAL_HAVE_NMI 0 /* 1 if NMI option configured, 0 otherwise */
97#define XCHAL_NUM_INTERRUPTS 17 /* number of interrupts */
98#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* number of bits to hold an interrupt number: roundup(log2(number of interrupts)) */
99#define XCHAL_NUM_EXTINTERRUPTS 10 /* number of external interrupts */
100#define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels (not including level zero!) */
101#define XCHAL_NUM_LOWPRI_LEVELS 1 /* number of low-priority interrupt levels (always 1) */
102#define XCHAL_FIRST_HIGHPRI_LEVEL (XCHAL_NUM_LOWPRI_LEVELS+1) /* level of first high-priority interrupt (always 2) */
103#define XCHAL_EXCM_LEVEL 1 /* level of interrupts masked by PS.EXCM (XEA2 only; always 1 in T10xx);
104 for XEA1, where there is no PS.EXCM, this is always 1;
105 interrupts at levels FIRST_HIGHPRI <= n <= EXCM_LEVEL, if any,
106 are termed "medium priority" interrupts (post T10xx only) */
107/* Note: 1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15 */
108
109/* Masks of interrupts at each interrupt level: */
110#define XCHAL_INTLEVEL0_MASK 0x00000000
111#define XCHAL_INTLEVEL1_MASK 0x000064F9
112#define XCHAL_INTLEVEL2_MASK 0x00008902
113#define XCHAL_INTLEVEL3_MASK 0x00011204
114#define XCHAL_INTLEVEL4_MASK 0x00000000
115#define XCHAL_INTLEVEL5_MASK 0x00000000
116#define XCHAL_INTLEVEL6_MASK 0x00000000
117#define XCHAL_INTLEVEL7_MASK 0x00000000
118#define XCHAL_INTLEVEL8_MASK 0x00000000
119#define XCHAL_INTLEVEL9_MASK 0x00000000
120#define XCHAL_INTLEVEL10_MASK 0x00000000
121#define XCHAL_INTLEVEL11_MASK 0x00000000
122#define XCHAL_INTLEVEL12_MASK 0x00000000
123#define XCHAL_INTLEVEL13_MASK 0x00000000
124#define XCHAL_INTLEVEL14_MASK 0x00000000
125#define XCHAL_INTLEVEL15_MASK 0x00000000
126/* As an array of entries (eg. for C constant arrays): */
127#define XCHAL_INTLEVEL_MASKS 0x00000000 XCHAL_SEP \
128 0x000064F9 XCHAL_SEP \
129 0x00008902 XCHAL_SEP \
130 0x00011204 XCHAL_SEP \
131 0x00000000 XCHAL_SEP \
132 0x00000000 XCHAL_SEP \
133 0x00000000 XCHAL_SEP \
134 0x00000000 XCHAL_SEP \
135 0x00000000 XCHAL_SEP \
136 0x00000000 XCHAL_SEP \
137 0x00000000 XCHAL_SEP \
138 0x00000000 XCHAL_SEP \
139 0x00000000 XCHAL_SEP \
140 0x00000000 XCHAL_SEP \
141 0x00000000 XCHAL_SEP \
142 0x00000000
143
144/* Masks of interrupts at each range 1..n of interrupt levels: */
145#define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000
146#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000064F9
147#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x0000EDFB
148#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x0001FFFF
149#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x0001FFFF
150#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x0001FFFF
151#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x0001FFFF
152#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x0001FFFF
153#define XCHAL_INTLEVEL8_ANDBELOW_MASK 0x0001FFFF
154#define XCHAL_INTLEVEL9_ANDBELOW_MASK 0x0001FFFF
155#define XCHAL_INTLEVEL10_ANDBELOW_MASK 0x0001FFFF
156#define XCHAL_INTLEVEL11_ANDBELOW_MASK 0x0001FFFF
157#define XCHAL_INTLEVEL12_ANDBELOW_MASK 0x0001FFFF
158#define XCHAL_INTLEVEL13_ANDBELOW_MASK 0x0001FFFF
159#define XCHAL_INTLEVEL14_ANDBELOW_MASK 0x0001FFFF
160#define XCHAL_INTLEVEL15_ANDBELOW_MASK 0x0001FFFF
161#define XCHAL_LOWPRI_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK /* mask of all low-priority interrupts */
162#define XCHAL_EXCM_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK /* mask of all interrupts masked by PS.EXCM (or CEXCM) */
163/* As an array of entries (eg. for C constant arrays): */
164#define XCHAL_INTLEVEL_ANDBELOW_MASKS 0x00000000 XCHAL_SEP \
165 0x000064F9 XCHAL_SEP \
166 0x0000EDFB XCHAL_SEP \
167 0x0001FFFF XCHAL_SEP \
168 0x0001FFFF XCHAL_SEP \
169 0x0001FFFF XCHAL_SEP \
170 0x0001FFFF XCHAL_SEP \
171 0x0001FFFF XCHAL_SEP \
172 0x0001FFFF XCHAL_SEP \
173 0x0001FFFF XCHAL_SEP \
174 0x0001FFFF XCHAL_SEP \
175 0x0001FFFF XCHAL_SEP \
176 0x0001FFFF XCHAL_SEP \
177 0x0001FFFF XCHAL_SEP \
178 0x0001FFFF XCHAL_SEP \
179 0x0001FFFF
180
181/* Interrupt numbers for each interrupt level at which only one interrupt was configured: */
182/*#define XCHAL_INTLEVEL1_NUM ...more than one interrupt at this level...*/
183/*#define XCHAL_INTLEVEL2_NUM ...more than one interrupt at this level...*/
184/*#define XCHAL_INTLEVEL3_NUM ...more than one interrupt at this level...*/
185
186/* Level of each interrupt: */
187#define XCHAL_INT0_LEVEL 1
188#define XCHAL_INT1_LEVEL 2
189#define XCHAL_INT2_LEVEL 3
190#define XCHAL_INT3_LEVEL 1
191#define XCHAL_INT4_LEVEL 1
192#define XCHAL_INT5_LEVEL 1
193#define XCHAL_INT6_LEVEL 1
194#define XCHAL_INT7_LEVEL 1
195#define XCHAL_INT8_LEVEL 2
196#define XCHAL_INT9_LEVEL 3
197#define XCHAL_INT10_LEVEL 1
198#define XCHAL_INT11_LEVEL 2
199#define XCHAL_INT12_LEVEL 3
200#define XCHAL_INT13_LEVEL 1
201#define XCHAL_INT14_LEVEL 1
202#define XCHAL_INT15_LEVEL 2
203#define XCHAL_INT16_LEVEL 3
204#define XCHAL_INT17_LEVEL 0
205#define XCHAL_INT18_LEVEL 0
206#define XCHAL_INT19_LEVEL 0
207#define XCHAL_INT20_LEVEL 0
208#define XCHAL_INT21_LEVEL 0
209#define XCHAL_INT22_LEVEL 0
210#define XCHAL_INT23_LEVEL 0
211#define XCHAL_INT24_LEVEL 0
212#define XCHAL_INT25_LEVEL 0
213#define XCHAL_INT26_LEVEL 0
214#define XCHAL_INT27_LEVEL 0
215#define XCHAL_INT28_LEVEL 0
216#define XCHAL_INT29_LEVEL 0
217#define XCHAL_INT30_LEVEL 0
218#define XCHAL_INT31_LEVEL 0
219/* As an array of entries (eg. for C constant arrays): */
220#define XCHAL_INT_LEVELS 1 XCHAL_SEP \
221 2 XCHAL_SEP \
222 3 XCHAL_SEP \
223 1 XCHAL_SEP \
224 1 XCHAL_SEP \
225 1 XCHAL_SEP \
226 1 XCHAL_SEP \
227 1 XCHAL_SEP \
228 2 XCHAL_SEP \
229 3 XCHAL_SEP \
230 1 XCHAL_SEP \
231 2 XCHAL_SEP \
232 3 XCHAL_SEP \
233 1 XCHAL_SEP \
234 1 XCHAL_SEP \
235 2 XCHAL_SEP \
236 3 XCHAL_SEP \
237 0 XCHAL_SEP \
238 0 XCHAL_SEP \
239 0 XCHAL_SEP \
240 0 XCHAL_SEP \
241 0 XCHAL_SEP \
242 0 XCHAL_SEP \
243 0 XCHAL_SEP \
244 0 XCHAL_SEP \
245 0 XCHAL_SEP \
246 0 XCHAL_SEP \
247 0 XCHAL_SEP \
248 0 XCHAL_SEP \
249 0 XCHAL_SEP \
250 0 XCHAL_SEP \
251 0
252
253/* Type of each interrupt: */
254#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
255#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
256#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
257#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
258#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
259#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
260#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
261#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_EDGE
262#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_EDGE
263#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_EDGE
264#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
265#define XCHAL_INT11_TYPE XTHAL_INTTYPE_TIMER
266#define XCHAL_INT12_TYPE XTHAL_INTTYPE_TIMER
267#define XCHAL_INT13_TYPE XTHAL_INTTYPE_SOFTWARE
268#define XCHAL_INT14_TYPE XTHAL_INTTYPE_SOFTWARE
269#define XCHAL_INT15_TYPE XTHAL_INTTYPE_SOFTWARE
270#define XCHAL_INT16_TYPE XTHAL_INTTYPE_SOFTWARE
271#define XCHAL_INT17_TYPE XTHAL_INTTYPE_UNCONFIGURED
272#define XCHAL_INT18_TYPE XTHAL_INTTYPE_UNCONFIGURED
273#define XCHAL_INT19_TYPE XTHAL_INTTYPE_UNCONFIGURED
274#define XCHAL_INT20_TYPE XTHAL_INTTYPE_UNCONFIGURED
275#define XCHAL_INT21_TYPE XTHAL_INTTYPE_UNCONFIGURED
276#define XCHAL_INT22_TYPE XTHAL_INTTYPE_UNCONFIGURED
277#define XCHAL_INT23_TYPE XTHAL_INTTYPE_UNCONFIGURED
278#define XCHAL_INT24_TYPE XTHAL_INTTYPE_UNCONFIGURED
279#define XCHAL_INT25_TYPE XTHAL_INTTYPE_UNCONFIGURED
280#define XCHAL_INT26_TYPE XTHAL_INTTYPE_UNCONFIGURED
281#define XCHAL_INT27_TYPE XTHAL_INTTYPE_UNCONFIGURED
282#define XCHAL_INT28_TYPE XTHAL_INTTYPE_UNCONFIGURED
283#define XCHAL_INT29_TYPE XTHAL_INTTYPE_UNCONFIGURED
284#define XCHAL_INT30_TYPE XTHAL_INTTYPE_UNCONFIGURED
285#define XCHAL_INT31_TYPE XTHAL_INTTYPE_UNCONFIGURED
286/* As an array of entries (eg. for C constant arrays): */
287#define XCHAL_INT_TYPES XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
288 XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
289 XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
290 XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
291 XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
292 XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
293 XTHAL_INTTYPE_EXTERN_LEVEL XCHAL_SEP \
294 XTHAL_INTTYPE_EXTERN_EDGE XCHAL_SEP \
295 XTHAL_INTTYPE_EXTERN_EDGE XCHAL_SEP \
296 XTHAL_INTTYPE_EXTERN_EDGE XCHAL_SEP \
297 XTHAL_INTTYPE_TIMER XCHAL_SEP \
298 XTHAL_INTTYPE_TIMER XCHAL_SEP \
299 XTHAL_INTTYPE_TIMER XCHAL_SEP \
300 XTHAL_INTTYPE_SOFTWARE XCHAL_SEP \
301 XTHAL_INTTYPE_SOFTWARE XCHAL_SEP \
302 XTHAL_INTTYPE_SOFTWARE XCHAL_SEP \
303 XTHAL_INTTYPE_SOFTWARE XCHAL_SEP \
304 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
305 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
306 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
307 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
308 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
309 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
310 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
311 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
312 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
313 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
314 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
315 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
316 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
317 XTHAL_INTTYPE_UNCONFIGURED XCHAL_SEP \
318 XTHAL_INTTYPE_UNCONFIGURED
319
320/* Masks of interrupts for each type of interrupt: */
321#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFE0000
322#define XCHAL_INTTYPE_MASK_SOFTWARE 0x0001E000
323#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000380
324#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000007F
325#define XCHAL_INTTYPE_MASK_TIMER 0x00001C00
326#define XCHAL_INTTYPE_MASK_NMI 0x00000000
327/* As an array of entries (eg. for C constant arrays): */
328#define XCHAL_INTTYPE_MASKS 0xFFFE0000 XCHAL_SEP \
329 0x0001E000 XCHAL_SEP \
330 0x00000380 XCHAL_SEP \
331 0x0000007F XCHAL_SEP \
332 0x00001C00 XCHAL_SEP \
333 0x00000000
334
335/* Interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3), -1 if unassigned */
336#define XCHAL_TIMER0_INTERRUPT 10
337#define XCHAL_TIMER1_INTERRUPT 11
338#define XCHAL_TIMER2_INTERRUPT 12
339#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
340/* As an array of entries (eg. for C constant arrays): */
341#define XCHAL_TIMER_INTERRUPTS 10 XCHAL_SEP \
342 11 XCHAL_SEP \
343 12 XCHAL_SEP \
344 XTHAL_TIMER_UNCONFIGURED
345
346/* Indexing macros: */
347#define _XCHAL_INTLEVEL_MASK(n) XCHAL_INTLEVEL ## n ## _MASK
348#define XCHAL_INTLEVEL_MASK(n) _XCHAL_INTLEVEL_MASK(n) /* n = 0 .. 15 */
349#define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK
350#define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */
351#define _XCHAL_INT_LEVEL(n) XCHAL_INT ## n ## _LEVEL
352#define XCHAL_INT_LEVEL(n) _XCHAL_INT_LEVEL(n) /* n = 0 .. 31 */
353#define _XCHAL_INT_TYPE(n) XCHAL_INT ## n ## _TYPE
354#define XCHAL_INT_TYPE(n) _XCHAL_INT_TYPE(n) /* n = 0 .. 31 */
355#define _XCHAL_TIMER_INTERRUPT(n) XCHAL_TIMER ## n ## _INTERRUPT
356#define XCHAL_TIMER_INTERRUPT(n) _XCHAL_TIMER_INTERRUPT(n) /* n = 0 .. 3 */
357
358
359
360/*
361 * External interrupt vectors/levels.
362 * These macros describe how Xtensa processor interrupt numbers
363 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
364 * map to external BInterrupt<n> pins, for those interrupts
365 * configured as external (level-triggered, edge-triggered, or NMI).
366 * See the Xtensa processor databook for more details.
367 */
368
369/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
370#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
371#define XCHAL_EXTINT1_NUM 1 /* (intlevel 2) */
372#define XCHAL_EXTINT2_NUM 2 /* (intlevel 3) */
373#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
374#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
375#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
376#define XCHAL_EXTINT6_NUM 6 /* (intlevel 1) */
377#define XCHAL_EXTINT7_NUM 7 /* (intlevel 1) */
378#define XCHAL_EXTINT8_NUM 8 /* (intlevel 2) */
379#define XCHAL_EXTINT9_NUM 9 /* (intlevel 3) */
380
381/* Corresponding interrupt masks: */
382#define XCHAL_EXTINT0_MASK 0x00000001
383#define XCHAL_EXTINT1_MASK 0x00000002
384#define XCHAL_EXTINT2_MASK 0x00000004
385#define XCHAL_EXTINT3_MASK 0x00000008
386#define XCHAL_EXTINT4_MASK 0x00000010
387#define XCHAL_EXTINT5_MASK 0x00000020
388#define XCHAL_EXTINT6_MASK 0x00000040
389#define XCHAL_EXTINT7_MASK 0x00000080
390#define XCHAL_EXTINT8_MASK 0x00000100
391#define XCHAL_EXTINT9_MASK 0x00000200
392
393/* Core config interrupt levels mapped to each external interrupt: */
394#define XCHAL_EXTINT0_LEVEL 1 /* (int number 0) */
395#define XCHAL_EXTINT1_LEVEL 2 /* (int number 1) */
396#define XCHAL_EXTINT2_LEVEL 3 /* (int number 2) */
397#define XCHAL_EXTINT3_LEVEL 1 /* (int number 3) */
398#define XCHAL_EXTINT4_LEVEL 1 /* (int number 4) */
399#define XCHAL_EXTINT5_LEVEL 1 /* (int number 5) */
400#define XCHAL_EXTINT6_LEVEL 1 /* (int number 6) */
401#define XCHAL_EXTINT7_LEVEL 1 /* (int number 7) */
402#define XCHAL_EXTINT8_LEVEL 2 /* (int number 8) */
403#define XCHAL_EXTINT9_LEVEL 3 /* (int number 9) */
404
405
406/*----------------------------------------------------------------------
407 EXCEPTIONS and VECTORS
408 ----------------------------------------------------------------------*/
409
410#define XCHAL_HAVE_EXCEPTIONS 1 /* 1 if exception option configured, 0 otherwise */
411
412#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture number: 1 for XEA1 (old), 2 for XEA2 (new) */
413#define XCHAL_HAVE_XEA1 0 /* 1 if XEA1, 0 otherwise */
414#define XCHAL_HAVE_XEA2 1 /* 1 if XEA2, 0 otherwise */
415/* For backward compatibility ONLY -- DO NOT USE (will be removed in future release): */
416#define XCHAL_HAVE_OLD_EXC_ARCH XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */
417#define XCHAL_HAVE_EXCM XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */
418
419#define XCHAL_RESET_VECTOR_VADDR 0xFE000020
420#define XCHAL_RESET_VECTOR_PADDR 0xFE000020
421#define XCHAL_USER_VECTOR_VADDR 0xD0000220
422#define XCHAL_PROGRAMEXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR /* for backward compatibility */
423#define XCHAL_USEREXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR /* for backward compatibility */
424#define XCHAL_USER_VECTOR_PADDR 0x00000220
425#define XCHAL_PROGRAMEXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR /* for backward compatibility */
426#define XCHAL_USEREXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR /* for backward compatibility */
427#define XCHAL_KERNEL_VECTOR_VADDR 0xD0000200
428#define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR /* for backward compatibility */
429#define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR /* for backward compatibility */
430#define XCHAL_KERNEL_VECTOR_PADDR 0x00000200
431#define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR /* for backward compatibility */
432#define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR /* for backward compatibility */
433#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xD0000290
434#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x00000290
435#define XCHAL_WINDOW_VECTORS_VADDR 0xD0000000
436#define XCHAL_WINDOW_VECTORS_PADDR 0x00000000
437#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xD0000240
438#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000240
439#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xD0000250
440#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x00000250
441#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xFE000520
442#define XCHAL_INTLEVEL4_VECTOR_PADDR 0xFE000520
443#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
444#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
445
446/* Indexing macros: */
447#define _XCHAL_INTLEVEL_VECTOR_VADDR(n) XCHAL_INTLEVEL ## n ## _VECTOR_VADDR
448#define XCHAL_INTLEVEL_VECTOR_VADDR(n) _XCHAL_INTLEVEL_VECTOR_VADDR(n) /* n = 0 .. 15 */
449
450/*
451 * General Exception Causes
452 * (values of EXCCAUSE special register set by general exceptions,
453 * which vector to the user, kernel, or double-exception vectors):
454 */
455#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction (IllegalInstruction) */
456#define XCHAL_EXCCAUSE_SYSTEM_CALL 1 /* System Call (SystemCall) */
457#define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 /* Instruction Fetch Error (InstructionFetchError) */
458#define XCHAL_EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error (LoadStoreError) */
459#define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt (Level1Interrupt) */
460#define XCHAL_EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (Alloca) */
461#define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero (IntegerDivideByZero) */
462#define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation (Speculation) */
463#define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction (Privileged) */
464#define XCHAL_EXCCAUSE_UNALIGNED 9 /* Unaligned Load Store (Unaligned) */
465#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception (ITlbMiss) */
466#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception (ITlbMultihit) */
467#define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception (ITlbPrivilege) */
468#define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb Size Restriction Exception (ITlbSizeRestriction) */
469#define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 /* Fetch Cache Attribute Exception (FetchCacheAttribute) */
470#define XCHAL_EXCCAUSE_DTLB_MISS 24 /* DTlb Miss Exception (DTlbMiss) */
471#define XCHAL_EXCCAUSE_DTLB_MULTIHIT 25 /* DTlb Multihit Exception (DTlbMultihit) */
472#define XCHAL_EXCCAUSE_DTLB_PRIVILEGE 26 /* DTlb Privilege Exception (DTlbPrivilege) */
473#define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION 27 /* DTlb Size Restriction Exception (DTlbSizeRestriction) */
474#define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 /* Load Cache Attribute Exception (LoadCacheAttribute) */
475#define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 /* Store Cache Attribute Exception (StoreCacheAttribute) */
476#define XCHAL_EXCCAUSE_FLOATING_POINT 40 /* Floating Point Exception (FloatingPoint) */
477
478
479
480/*----------------------------------------------------------------------
481 TIMERS
482 ----------------------------------------------------------------------*/
483
484#define XCHAL_HAVE_CCOUNT 1 /* 1 if have CCOUNT, 0 otherwise */
485/*#define XCHAL_HAVE_TIMERS XCHAL_HAVE_CCOUNT*/
486#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
487
488
489
490/*----------------------------------------------------------------------
491 DEBUG
492 ----------------------------------------------------------------------*/
493
494#define XCHAL_HAVE_DEBUG 1 /* 1 if debug option configured, 0 otherwise */
495#define XCHAL_HAVE_OCD 1 /* 1 if OnChipDebug option configured, 0 otherwise */
496#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
497#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
498#define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */
499/*DebugExternalInterrupt 0 0|1*/
500/*DebugUseDIRArray 0 0|1*/
501
502
503
504
505/*----------------------------------------------------------------------
506 COPROCESSORS and EXTRA STATE
507 ----------------------------------------------------------------------*/
508
509#define XCHAL_HAVE_CP 0 /* 1 if coprocessor option configured (CPENABLE present) */
510#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one (per cfg) */
511
512#include <xtensa/config/tie.h>
513
514
515
516
517/*----------------------------------------------------------------------
518 INTERNAL I/D RAM/ROMs and XLMI
519 ----------------------------------------------------------------------*/
520
521#define XCHAL_NUM_INSTROM 0 /* number of core instruction ROMs configured */
522#define XCHAL_NUM_INSTRAM 0 /* number of core instruction RAMs configured */
523#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs configured */
524#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs configured */
525#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports configured */
526#define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */
527#define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */
528#define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */
529#define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */
530
531
532
533/*----------------------------------------------------------------------
534 CACHE
535 ----------------------------------------------------------------------*/
536
537/* Size of the cache lines in log2(bytes): */
538#define XCHAL_ICACHE_LINEWIDTH 4
539#define XCHAL_DCACHE_LINEWIDTH 4
540/* Size of the cache lines in bytes: */
541#define XCHAL_ICACHE_LINESIZE 16
542#define XCHAL_DCACHE_LINESIZE 16
543/* Max for both I-cache and D-cache (used for general alignment): */
544#define XCHAL_CACHE_LINEWIDTH_MAX 4
545#define XCHAL_CACHE_LINESIZE_MAX 16
546
547/* Number of cache sets in log2(lines per way): */
548#define XCHAL_ICACHE_SETWIDTH 8
549#define XCHAL_DCACHE_SETWIDTH 8
550/* Max for both I-cache and D-cache (used for general cache-coherency page alignment): */
551#define XCHAL_CACHE_SETWIDTH_MAX 8
552#define XCHAL_CACHE_SETSIZE_MAX 256
553
554/* Cache set associativity (number of ways): */
555#define XCHAL_ICACHE_WAYS 2
556#define XCHAL_DCACHE_WAYS 2
557
558/* Size of the caches in bytes (ways * 2^(linewidth + setwidth)): */
559#define XCHAL_ICACHE_SIZE 8192
560#define XCHAL_DCACHE_SIZE 8192
561
562/* Cache features: */
563#define XCHAL_DCACHE_IS_WRITEBACK 0
564/* Whether cache locking feature is available: */
565#define XCHAL_ICACHE_LINE_LOCKABLE 0
566#define XCHAL_DCACHE_LINE_LOCKABLE 0
567
568/* Number of (encoded) cache attribute bits: */
569#define XCHAL_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
570/* (The number of access mode bits (decoded cache attribute bits) is defined by the architecture; see xtensa/hal.h?) */
571
572
573/* Cache Attribute encodings -- lists of access modes for each cache attribute: */
574#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
575 XTHAL_FAM_BYPASS XCHAL_SEP \
576 XTHAL_FAM_EXCEPTION XCHAL_SEP \
577 XTHAL_FAM_BYPASS XCHAL_SEP \
578 XTHAL_FAM_EXCEPTION XCHAL_SEP \
579 XTHAL_FAM_CACHED XCHAL_SEP \
580 XTHAL_FAM_EXCEPTION XCHAL_SEP \
581 XTHAL_FAM_CACHED XCHAL_SEP \
582 XTHAL_FAM_EXCEPTION XCHAL_SEP \
583 XTHAL_FAM_CACHED XCHAL_SEP \
584 XTHAL_FAM_EXCEPTION XCHAL_SEP \
585 XTHAL_FAM_CACHED XCHAL_SEP \
586 XTHAL_FAM_EXCEPTION XCHAL_SEP \
587 XTHAL_FAM_EXCEPTION XCHAL_SEP \
588 XTHAL_FAM_EXCEPTION XCHAL_SEP \
589 XTHAL_FAM_EXCEPTION
590#define XCHAL_LCA_LIST XTHAL_LAM_EXCEPTION XCHAL_SEP \
591 XTHAL_LAM_BYPASSG XCHAL_SEP \
592 XTHAL_LAM_EXCEPTION XCHAL_SEP \
593 XTHAL_LAM_BYPASSG XCHAL_SEP \
594 XTHAL_LAM_EXCEPTION XCHAL_SEP \
595 XTHAL_LAM_CACHED XCHAL_SEP \
596 XTHAL_LAM_EXCEPTION XCHAL_SEP \
597 XTHAL_LAM_CACHED XCHAL_SEP \
598 XTHAL_LAM_EXCEPTION XCHAL_SEP \
599 XTHAL_LAM_NACACHED XCHAL_SEP \
600 XTHAL_LAM_EXCEPTION XCHAL_SEP \
601 XTHAL_LAM_NACACHED XCHAL_SEP \
602 XTHAL_LAM_EXCEPTION XCHAL_SEP \
603 XTHAL_LAM_ISOLATE XCHAL_SEP \
604 XTHAL_LAM_EXCEPTION XCHAL_SEP \
605 XTHAL_LAM_CACHED
606#define XCHAL_SCA_LIST XTHAL_SAM_EXCEPTION XCHAL_SEP \
607 XTHAL_SAM_EXCEPTION XCHAL_SEP \
608 XTHAL_SAM_EXCEPTION XCHAL_SEP \
609 XTHAL_SAM_BYPASS XCHAL_SEP \
610 XTHAL_SAM_EXCEPTION XCHAL_SEP \
611 XTHAL_SAM_EXCEPTION XCHAL_SEP \
612 XTHAL_SAM_EXCEPTION XCHAL_SEP \
613 XTHAL_SAM_WRITETHRU XCHAL_SEP \
614 XTHAL_SAM_EXCEPTION XCHAL_SEP \
615 XTHAL_SAM_EXCEPTION XCHAL_SEP \
616 XTHAL_SAM_EXCEPTION XCHAL_SEP \
617 XTHAL_SAM_WRITETHRU XCHAL_SEP \
618 XTHAL_SAM_EXCEPTION XCHAL_SEP \
619 XTHAL_SAM_ISOLATE XCHAL_SEP \
620 XTHAL_SAM_EXCEPTION XCHAL_SEP \
621 XTHAL_SAM_WRITETHRU
622
623/* Test:
624 read/only: 0 + 1 + 2 + 4 + 5 + 6 + 8 + 9 + 10 + 12 + 14
625 read/only: 0 + 1 + 2 + 4 + 5 + 6 + 8 + 9 + 10 + 12 + 14
626 all: 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15
627 fault: 0 + 2 + 4 + 6 + 8 + 10 + 12 + 14
628 r/w/x cached:
629 r/w/x dcached:
630 I-bypass: 1 + 3
631
632 load guard bit set: 1 + 3
633 load guard bit clr: 0 + 2 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15
634 hit-cache r/w/x: 7 + 11
635
636 fams: 5
637 fams: 0 / 6 / 18 / 1 / 2
638 fams: Bypass / Isolate / Cached / Exception / NACached
639
640 MMU okay: yes
641*/
642
643
644/*----------------------------------------------------------------------
645 MMU
646 ----------------------------------------------------------------------*/
647
648/*
649 * General notes on MMU parameters.
650 *
651 * Terminology:
652 * ASID = address-space ID (acts as an "extension" of virtual addresses)
653 * VPN = virtual page number
654 * PPN = physical page number
655 * CA = encoded cache attribute (access modes)
656 * TLB = translation look-aside buffer (term is stretched somewhat here)
657 * I = instruction (fetch accesses)
658 * D = data (load and store accesses)
659 * way = each TLB (ITLB and DTLB) consists of a number of "ways"
660 * that simultaneously match the virtual address of an access;
661 * a TLB successfully translates a virtual address if exactly
662 * one way matches the vaddr; if none match, it is a miss;
663 * if multiple match, one gets a "multihit" exception;
664 * each way can be independently configured in terms of number of
665 * entries, page sizes, which fields are writable or constant, etc.
666 * set = group of contiguous ways with exactly identical parameters
667 * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
668 * from the page table and storing it in one of the auto-refill ways;
669 * if this PTE load also misses, a miss exception is posted for s/w.
670 * min-wired = a "min-wired" way can be used to map a single (minimum-sized)
671 * page arbitrarily under program control; it has a single entry,
672 * is non-auto-refill (some other way(s) must be auto-refill),
673 * all its fields (VPN, PPN, ASID, CA) are all writable, and it
674 * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
675 * restriction is that this be the only page size it supports).
676 *
677 * TLB way entries are virtually indexed.
678 * TLB ways that support multiple page sizes:
679 * - must have all writable VPN and PPN fields;
680 * - can only use one page size at any given time (eg. setup at startup),
681 * selected by the respective ITLBCFG or DTLBCFG special register,
682 * whose bits n*4+3 .. n*4 index the list of page sizes for way n
683 * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
684 * this list may be sparse for auto-refill ways because auto-refill
685 * ways have independent lists of supported page sizes sharing a
686 * common encoding with PTE entries; the encoding is the index into
687 * this list; unsupported sizes for a given way are zero in the list;
688 * selecting unsupported sizes results in undefined hardware behaviour;
689 * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
690 */
691
692#define XCHAL_HAVE_CACHEATTR 0 /* 1 if CACHEATTR register present, 0 if TLBs present instead */
693#define XCHAL_HAVE_TLBS 1 /* 1 if TLBs present, 0 if CACHEATTR present instead */
694#define XCHAL_HAVE_MMU XCHAL_HAVE_TLBS /* (DEPRECATED; use XCHAL_HAVE_TLBS instead; will be removed in future release) */
695#define XCHAL_HAVE_SPANNING_WAY 0 /* 1 if single way maps entire virtual address space in I+D */
696#define XCHAL_HAVE_IDENTITY_MAP 0 /* 1 if virtual addr == physical addr always, 0 otherwise */
697#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* 1 if have MMU that mimics a CACHEATTR config (CaMMU) */
698#define XCHAL_HAVE_XLT_CACHEATTR 0 /* 1 if have MMU that mimics a CACHEATTR config, but with translation (CaXltMMU) */
699
700#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs (address space IDs) */
701#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
702#define XCHAL_MMU_ASID_KERNEL 1 /* ASID value indicating kernel (ring 0) address space */
703#define XCHAL_MMU_RINGS 4 /* number of rings supported (1..4) */
704#define XCHAL_MMU_RING_BITS 2 /* number of bits needed to hold ring number */
705#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
706#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
707#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 12 /* max page size in a PTE structure (log2) */
708#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 /* min page size in a PTE structure (log2) */
709
710
711/*** Instruction TLB: ***/
712
713#define XCHAL_ITLB_WAY_BITS 3 /* number of bits holding the ways */
714#define XCHAL_ITLB_WAYS 7 /* number of ways (n-way set-associative TLB) */
715#define XCHAL_ITLB_ARF_WAYS 4 /* number of auto-refill ways */
716#define XCHAL_ITLB_SETS 4 /* number of sets (groups of ways with identical settings) */
717
718/* Way set to which each way belongs: */
719#define XCHAL_ITLB_WAY0_SET 0
720#define XCHAL_ITLB_WAY1_SET 0
721#define XCHAL_ITLB_WAY2_SET 0
722#define XCHAL_ITLB_WAY3_SET 0
723#define XCHAL_ITLB_WAY4_SET 1
724#define XCHAL_ITLB_WAY5_SET 2
725#define XCHAL_ITLB_WAY6_SET 3
726
727/* Ways sets that are used by hardware auto-refill (ARF): */
728#define XCHAL_ITLB_ARF_SETS 1 /* number of auto-refill sets */
729#define XCHAL_ITLB_ARF_SET0 0 /* index of n'th auto-refill set */
730
731/* Way sets that are "min-wired" (see terminology comment above): */
732#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
733
734
735/* ITLB way set 0 (group of ways 0 thru 3): */
736#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
737#define XCHAL_ITLB_SET0_WAYS 4 /* number of (contiguous) ways in this way set */
738#define XCHAL_ITLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
739#define XCHAL_ITLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */
740#define XCHAL_ITLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
741#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
742#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
743#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
744#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
745#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
746 2^PAGESZ_BITS entries in list, unsupported entries are zero */
747#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
748#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
749#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
750#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
751#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
752#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
753#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
754#define XCHAL_ITLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
755
756/* ITLB way set 1 (group of ways 4 thru 4): */
757#define XCHAL_ITLB_SET1_WAY 4 /* index of first way in this way set */
758#define XCHAL_ITLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */
759#define XCHAL_ITLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
760#define XCHAL_ITLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */
761#define XCHAL_ITLB_SET1_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
762#define XCHAL_ITLB_SET1_PAGESIZES 4 /* number of supported page sizes in this way */
763#define XCHAL_ITLB_SET1_PAGESZ_BITS 2 /* number of bits to encode the page size */
764#define XCHAL_ITLB_SET1_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */
765#define XCHAL_ITLB_SET1_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */
766#define XCHAL_ITLB_SET1_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP;
767 2^PAGESZ_BITS entries in list, unsupported entries are zero */
768#define XCHAL_ITLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
769#define XCHAL_ITLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
770#define XCHAL_ITLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
771#define XCHAL_ITLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
772#define XCHAL_ITLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
773#define XCHAL_ITLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
774#define XCHAL_ITLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
775#define XCHAL_ITLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
776
777/* ITLB way set 2 (group of ways 5 thru 5): */
778#define XCHAL_ITLB_SET2_WAY 5 /* index of first way in this way set */
779#define XCHAL_ITLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */
780#define XCHAL_ITLB_SET2_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
781#define XCHAL_ITLB_SET2_ENTRIES 2 /* number of entries in this way (always a power of 2) */
782#define XCHAL_ITLB_SET2_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
783#define XCHAL_ITLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */
784#define XCHAL_ITLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */
785#define XCHAL_ITLB_SET2_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */
786#define XCHAL_ITLB_SET2_PAGESZ_LOG2_MAX 27 /* log2(maximum supported page size) */
787#define XCHAL_ITLB_SET2_PAGESZ_LOG2_LIST 27 /* list of log2(page size)s, separated by XCHAL_SEP;
788 2^PAGESZ_BITS entries in list, unsupported entries are zero */
789#define XCHAL_ITLB_SET2_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
790#define XCHAL_ITLB_SET2_VPN_CONSTMASK 0xF0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
791#define XCHAL_ITLB_SET2_PPN_CONSTMASK 0xF8000000 /* constant PPN bits, including entry index bits; 0 if all writable */
792#define XCHAL_ITLB_SET2_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
793#define XCHAL_ITLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
794#define XCHAL_ITLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
795#define XCHAL_ITLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
796#define XCHAL_ITLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
797/* Constant ASID values for each entry of ITLB way set 2 (because ASID_CONSTMASK is non-zero): */
798#define XCHAL_ITLB_SET2_E0_ASID_CONST 0x01
799#define XCHAL_ITLB_SET2_E1_ASID_CONST 0x01
800/* Constant VPN values for each entry of ITLB way set 2 (because VPN_CONSTMASK is non-zero): */
801#define XCHAL_ITLB_SET2_E0_VPN_CONST 0xD0000000
802#define XCHAL_ITLB_SET2_E1_VPN_CONST 0xD8000000
803/* Constant PPN values for each entry of ITLB way set 2 (because PPN_CONSTMASK is non-zero): */
804#define XCHAL_ITLB_SET2_E0_PPN_CONST 0x00000000
805#define XCHAL_ITLB_SET2_E1_PPN_CONST 0x00000000
806/* Constant CA values for each entry of ITLB way set 2 (because CA_CONSTMASK is non-zero): */
807#define XCHAL_ITLB_SET2_E0_CA_CONST 0x07
808#define XCHAL_ITLB_SET2_E1_CA_CONST 0x03
809
810/* ITLB way set 3 (group of ways 6 thru 6): */
811#define XCHAL_ITLB_SET3_WAY 6 /* index of first way in this way set */
812#define XCHAL_ITLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */
813#define XCHAL_ITLB_SET3_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
814#define XCHAL_ITLB_SET3_ENTRIES 2 /* number of entries in this way (always a power of 2) */
815#define XCHAL_ITLB_SET3_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
816#define XCHAL_ITLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */
817#define XCHAL_ITLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */
818#define XCHAL_ITLB_SET3_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */
819#define XCHAL_ITLB_SET3_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */
820#define XCHAL_ITLB_SET3_PAGESZ_LOG2_LIST 28 /* list of log2(page size)s, separated by XCHAL_SEP;
821 2^PAGESZ_BITS entries in list, unsupported entries are zero */
822#define XCHAL_ITLB_SET3_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
823#define XCHAL_ITLB_SET3_VPN_CONSTMASK 0xE0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
824#define XCHAL_ITLB_SET3_PPN_CONSTMASK 0xF0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
825#define XCHAL_ITLB_SET3_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
826#define XCHAL_ITLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
827#define XCHAL_ITLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
828#define XCHAL_ITLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
829#define XCHAL_ITLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
830/* Constant ASID values for each entry of ITLB way set 3 (because ASID_CONSTMASK is non-zero): */
831#define XCHAL_ITLB_SET3_E0_ASID_CONST 0x01
832#define XCHAL_ITLB_SET3_E1_ASID_CONST 0x01
833/* Constant VPN values for each entry of ITLB way set 3 (because VPN_CONSTMASK is non-zero): */
834#define XCHAL_ITLB_SET3_E0_VPN_CONST 0xE0000000
835#define XCHAL_ITLB_SET3_E1_VPN_CONST 0xF0000000
836/* Constant PPN values for each entry of ITLB way set 3 (because PPN_CONSTMASK is non-zero): */
837#define XCHAL_ITLB_SET3_E0_PPN_CONST 0xF0000000
838#define XCHAL_ITLB_SET3_E1_PPN_CONST 0xF0000000
839/* Constant CA values for each entry of ITLB way set 3 (because CA_CONSTMASK is non-zero): */
840#define XCHAL_ITLB_SET3_E0_CA_CONST 0x07
841#define XCHAL_ITLB_SET3_E1_CA_CONST 0x03
842
843/* Indexing macros: */
844#define _XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what
845#define XCHAL_ITLB_SET(n,what) _XCHAL_ITLB_SET(n, _ ## what )
846#define _XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what
847#define XCHAL_ITLB_SET_E(n,i,what) _XCHAL_ITLB_SET_E(n,i, _ ## what )
848/*
849 * Example use: XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES)
850 * to get the value of XCHAL_ITLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
851 */
852
853
854/*** Data TLB: ***/
855
856#define XCHAL_DTLB_WAY_BITS 4 /* number of bits holding the ways */
857#define XCHAL_DTLB_WAYS 10 /* number of ways (n-way set-associative TLB) */
858#define XCHAL_DTLB_ARF_WAYS 4 /* number of auto-refill ways */
859#define XCHAL_DTLB_SETS 5 /* number of sets (groups of ways with identical settings) */
860
861/* Way set to which each way belongs: */
862#define XCHAL_DTLB_WAY0_SET 0
863#define XCHAL_DTLB_WAY1_SET 0
864#define XCHAL_DTLB_WAY2_SET 0
865#define XCHAL_DTLB_WAY3_SET 0
866#define XCHAL_DTLB_WAY4_SET 1
867#define XCHAL_DTLB_WAY5_SET 2
868#define XCHAL_DTLB_WAY6_SET 3
869#define XCHAL_DTLB_WAY7_SET 4
870#define XCHAL_DTLB_WAY8_SET 4
871#define XCHAL_DTLB_WAY9_SET 4
872
873/* Ways sets that are used by hardware auto-refill (ARF): */
874#define XCHAL_DTLB_ARF_SETS 1 /* number of auto-refill sets */
875#define XCHAL_DTLB_ARF_SET0 0 /* index of n'th auto-refill set */
876
877/* Way sets that are "min-wired" (see terminology comment above): */
878#define XCHAL_DTLB_MINWIRED_SETS 1 /* number of "min-wired" sets */
879#define XCHAL_DTLB_MINWIRED_SET0 4 /* index of n'th "min-wired" set */
880
881
882/* DTLB way set 0 (group of ways 0 thru 3): */
883#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
884#define XCHAL_DTLB_SET0_WAYS 4 /* number of (contiguous) ways in this way set */
885#define XCHAL_DTLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
886#define XCHAL_DTLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */
887#define XCHAL_DTLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
888#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
889#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
890#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
891#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
892#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
893 2^PAGESZ_BITS entries in list, unsupported entries are zero */
894#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
895#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
896#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
897#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
898#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
899#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
900#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
901#define XCHAL_DTLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
902
903/* DTLB way set 1 (group of ways 4 thru 4): */
904#define XCHAL_DTLB_SET1_WAY 4 /* index of first way in this way set */
905#define XCHAL_DTLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */
906#define XCHAL_DTLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
907#define XCHAL_DTLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */
908#define XCHAL_DTLB_SET1_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
909#define XCHAL_DTLB_SET1_PAGESIZES 4 /* number of supported page sizes in this way */
910#define XCHAL_DTLB_SET1_PAGESZ_BITS 2 /* number of bits to encode the page size */
911#define XCHAL_DTLB_SET1_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */
912#define XCHAL_DTLB_SET1_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */
913#define XCHAL_DTLB_SET1_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP;
914 2^PAGESZ_BITS entries in list, unsupported entries are zero */
915#define XCHAL_DTLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
916#define XCHAL_DTLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
917#define XCHAL_DTLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
918#define XCHAL_DTLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
919#define XCHAL_DTLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
920#define XCHAL_DTLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
921#define XCHAL_DTLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
922#define XCHAL_DTLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
923
924/* DTLB way set 2 (group of ways 5 thru 5): */
925#define XCHAL_DTLB_SET2_WAY 5 /* index of first way in this way set */
926#define XCHAL_DTLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */
927#define XCHAL_DTLB_SET2_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
928#define XCHAL_DTLB_SET2_ENTRIES 2 /* number of entries in this way (always a power of 2) */
929#define XCHAL_DTLB_SET2_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
930#define XCHAL_DTLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */
931#define XCHAL_DTLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */
932#define XCHAL_DTLB_SET2_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */
933#define XCHAL_DTLB_SET2_PAGESZ_LOG2_MAX 27 /* log2(maximum supported page size) */
934#define XCHAL_DTLB_SET2_PAGESZ_LOG2_LIST 27 /* list of log2(page size)s, separated by XCHAL_SEP;
935 2^PAGESZ_BITS entries in list, unsupported entries are zero */
936#define XCHAL_DTLB_SET2_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
937#define XCHAL_DTLB_SET2_VPN_CONSTMASK 0xF0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
938#define XCHAL_DTLB_SET2_PPN_CONSTMASK 0xF8000000 /* constant PPN bits, including entry index bits; 0 if all writable */
939#define XCHAL_DTLB_SET2_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
940#define XCHAL_DTLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
941#define XCHAL_DTLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
942#define XCHAL_DTLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
943#define XCHAL_DTLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
944/* Constant ASID values for each entry of DTLB way set 2 (because ASID_CONSTMASK is non-zero): */
945#define XCHAL_DTLB_SET2_E0_ASID_CONST 0x01
946#define XCHAL_DTLB_SET2_E1_ASID_CONST 0x01
947/* Constant VPN values for each entry of DTLB way set 2 (because VPN_CONSTMASK is non-zero): */
948#define XCHAL_DTLB_SET2_E0_VPN_CONST 0xD0000000
949#define XCHAL_DTLB_SET2_E1_VPN_CONST 0xD8000000
950/* Constant PPN values for each entry of DTLB way set 2 (because PPN_CONSTMASK is non-zero): */
951#define XCHAL_DTLB_SET2_E0_PPN_CONST 0x00000000
952#define XCHAL_DTLB_SET2_E1_PPN_CONST 0x00000000
953/* Constant CA values for each entry of DTLB way set 2 (because CA_CONSTMASK is non-zero): */
954#define XCHAL_DTLB_SET2_E0_CA_CONST 0x07
955#define XCHAL_DTLB_SET2_E1_CA_CONST 0x03
956
957/* DTLB way set 3 (group of ways 6 thru 6): */
958#define XCHAL_DTLB_SET3_WAY 6 /* index of first way in this way set */
959#define XCHAL_DTLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */
960#define XCHAL_DTLB_SET3_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
961#define XCHAL_DTLB_SET3_ENTRIES 2 /* number of entries in this way (always a power of 2) */
962#define XCHAL_DTLB_SET3_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
963#define XCHAL_DTLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */
964#define XCHAL_DTLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */
965#define XCHAL_DTLB_SET3_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */
966#define XCHAL_DTLB_SET3_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */
967#define XCHAL_DTLB_SET3_PAGESZ_LOG2_LIST 28 /* list of log2(page size)s, separated by XCHAL_SEP;
968 2^PAGESZ_BITS entries in list, unsupported entries are zero */
969#define XCHAL_DTLB_SET3_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
970#define XCHAL_DTLB_SET3_VPN_CONSTMASK 0xE0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
971#define XCHAL_DTLB_SET3_PPN_CONSTMASK 0xF0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
972#define XCHAL_DTLB_SET3_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
973#define XCHAL_DTLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
974#define XCHAL_DTLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
975#define XCHAL_DTLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
976#define XCHAL_DTLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
977/* Constant ASID values for each entry of DTLB way set 3 (because ASID_CONSTMASK is non-zero): */
978#define XCHAL_DTLB_SET3_E0_ASID_CONST 0x01
979#define XCHAL_DTLB_SET3_E1_ASID_CONST 0x01
980/* Constant VPN values for each entry of DTLB way set 3 (because VPN_CONSTMASK is non-zero): */
981#define XCHAL_DTLB_SET3_E0_VPN_CONST 0xE0000000
982#define XCHAL_DTLB_SET3_E1_VPN_CONST 0xF0000000
983/* Constant PPN values for each entry of DTLB way set 3 (because PPN_CONSTMASK is non-zero): */
984#define XCHAL_DTLB_SET3_E0_PPN_CONST 0xF0000000
985#define XCHAL_DTLB_SET3_E1_PPN_CONST 0xF0000000
986/* Constant CA values for each entry of DTLB way set 3 (because CA_CONSTMASK is non-zero): */
987#define XCHAL_DTLB_SET3_E0_CA_CONST 0x07
988#define XCHAL_DTLB_SET3_E1_CA_CONST 0x03
989
990/* DTLB way set 4 (group of ways 7 thru 9): */
991#define XCHAL_DTLB_SET4_WAY 7 /* index of first way in this way set */
992#define XCHAL_DTLB_SET4_WAYS 3 /* number of (contiguous) ways in this way set */
993#define XCHAL_DTLB_SET4_ENTRIES_LOG2 0 /* log2(number of entries in this way) */
994#define XCHAL_DTLB_SET4_ENTRIES 1 /* number of entries in this way (always a power of 2) */
995#define XCHAL_DTLB_SET4_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
996#define XCHAL_DTLB_SET4_PAGESIZES 1 /* number of supported page sizes in this way */
997#define XCHAL_DTLB_SET4_PAGESZ_BITS 0 /* number of bits to encode the page size */
998#define XCHAL_DTLB_SET4_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
999#define XCHAL_DTLB_SET4_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
1000#define XCHAL_DTLB_SET4_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
1001 2^PAGESZ_BITS entries in list, unsupported entries are zero */
1002#define XCHAL_DTLB_SET4_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
1003#define XCHAL_DTLB_SET4_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
1004#define XCHAL_DTLB_SET4_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
1005#define XCHAL_DTLB_SET4_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
1006#define XCHAL_DTLB_SET4_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
1007#define XCHAL_DTLB_SET4_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
1008#define XCHAL_DTLB_SET4_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
1009#define XCHAL_DTLB_SET4_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
1010
1011/* Indexing macros: */
1012#define _XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what
1013#define XCHAL_DTLB_SET(n,what) _XCHAL_DTLB_SET(n, _ ## what )
1014#define _XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what
1015#define XCHAL_DTLB_SET_E(n,i,what) _XCHAL_DTLB_SET_E(n,i, _ ## what )
1016/*
1017 * Example use: XCHAL_DTLB_SET(XCHAL_DTLB_ARF_SET0,ENTRIES)
1018 * to get the value of XCHAL_DTLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
1019 */
1020
1021
1022/*
1023 * Determine whether we have a full MMU (with Page Table and Protection)
1024 * usable for an MMU-based OS:
1025 */
1026#if XCHAL_HAVE_TLBS && !XCHAL_HAVE_SPANNING_WAY && XCHAL_ITLB_ARF_WAYS > 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2
1027# define XCHAL_HAVE_PTP_MMU 1 /* have full MMU (with page table [autorefill] and protection) */
1028#else
1029# define XCHAL_HAVE_PTP_MMU 0 /* don't have full MMU */
1030#endif
1031
1032/*
1033 * For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings:
1034 */
1035#if XCHAL_HAVE_PTP_MMU
1036#define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel RAM cached static map */
1037#define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of kseg_cached */
1038#define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of kseg_cached (assumed power of 2!!!) */
1039#define XCHAL_KSEG_BYPASS_VADDR 0xD8000000 /* virt.addr of kernel RAM bypass (uncached) static map */
1040#define XCHAL_KSEG_BYPASS_PADDR 0x00000000 /* phys.addr of kseg_bypass */
1041#define XCHAL_KSEG_BYPASS_SIZE 0x08000000 /* size in bytes of kseg_bypass (assumed power of 2!!!) */
1042
1043#define XCHAL_KIO_CACHED_VADDR 0xE0000000 /* virt.addr of kernel I/O cached static map */
1044#define XCHAL_KIO_CACHED_PADDR 0xF0000000 /* phys.addr of kio_cached */
1045#define XCHAL_KIO_CACHED_SIZE 0x10000000 /* size in bytes of kio_cached (assumed power of 2!!!) */
1046#define XCHAL_KIO_BYPASS_VADDR 0xF0000000 /* virt.addr of kernel I/O bypass (uncached) static map */
1047#define XCHAL_KIO_BYPASS_PADDR 0xF0000000 /* phys.addr of kio_bypass */
1048#define XCHAL_KIO_BYPASS_SIZE 0x10000000 /* size in bytes of kio_bypass (assumed power of 2!!!) */
1049
1050#define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest non-static-mapped virtual addr area */
1051#define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */
1052/* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size. */
1053#endif
1054
1055
1056/*----------------------------------------------------------------------
1057 MISC
1058 ----------------------------------------------------------------------*/
1059
1060#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* number of write buffer entries */
1061
1062#define XCHAL_CORE_ID "linux_be" /* configuration's alphanumeric core identifier
1063 (CoreID) set in the Xtensa Processor Generator */
1064
1065#define XCHAL_BUILD_UNIQUE_ID 0x00003256 /* software build-unique ID (22-bit) */
1066
1067/* These definitions describe the hardware targeted by this software: */
1068#define XCHAL_HW_CONFIGID0 0xC103D1FF /* config ID reg 0 value (upper 32 of 64 bits) */
1069#define XCHAL_HW_CONFIGID1 0x00803256 /* config ID reg 1 value (lower 32 of 64 bits) */
1070#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
1071#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
1072#define XCHAL_HW_RELEASE_MAJOR 1050 /* major release of targeted hardware */
1073#define XCHAL_HW_RELEASE_MINOR 1 /* minor release of targeted hardware */
1074#define XCHAL_HW_RELEASE_NAME "T1050.1" /* full release name of targeted hardware */
1075#define XTHAL_HW_REL_T1050 1
1076#define XTHAL_HW_REL_T1050_1 1
1077#define XCHAL_HW_CONFIGID_RELIABLE 1
1078
1079
1080/*
1081 * Miscellaneous special register fields:
1082 */
1083
1084
1085/* DBREAKC (special register number 160): */
1086#define XCHAL_DBREAKC_VALIDMASK 0xC000003F /* bits of DBREAKC that are defined */
1087/* MASK field: */
1088#define XCHAL_DBREAKC_MASK_BITS 6 /* number of bits in MASK field */
1089#define XCHAL_DBREAKC_MASK_NUM 64 /* max number of possible causes (2^bits) */
1090#define XCHAL_DBREAKC_MASK_SHIFT 0 /* position of MASK bits in DBREAKC, starting from lsbit */
1091#define XCHAL_DBREAKC_MASK_MASK 0x0000003F /* mask of bits in MASK field of DBREAKC */
1092/* LOADBREAK field: */
1093#define XCHAL_DBREAKC_LOADBREAK_BITS 1 /* number of bits in LOADBREAK field */
1094#define XCHAL_DBREAKC_LOADBREAK_NUM 2 /* max number of possible causes (2^bits) */
1095#define XCHAL_DBREAKC_LOADBREAK_SHIFT 30 /* position of LOADBREAK bits in DBREAKC, starting from lsbit */
1096#define XCHAL_DBREAKC_LOADBREAK_MASK 0x40000000 /* mask of bits in LOADBREAK field of DBREAKC */
1097/* STOREBREAK field: */
1098#define XCHAL_DBREAKC_STOREBREAK_BITS 1 /* number of bits in STOREBREAK field */
1099#define XCHAL_DBREAKC_STOREBREAK_NUM 2 /* max number of possible causes (2^bits) */
1100#define XCHAL_DBREAKC_STOREBREAK_SHIFT 31 /* position of STOREBREAK bits in DBREAKC, starting from lsbit */
1101#define XCHAL_DBREAKC_STOREBREAK_MASK 0x80000000 /* mask of bits in STOREBREAK field of DBREAKC */
1102
1103/* PS (special register number 230): */
1104#define XCHAL_PS_VALIDMASK 0x00070FFF /* bits of PS that are defined */
1105/* INTLEVEL field: */
1106#define XCHAL_PS_INTLEVEL_BITS 4 /* number of bits in INTLEVEL field */
1107#define XCHAL_PS_INTLEVEL_NUM 16 /* max number of possible causes (2^bits) */
1108#define XCHAL_PS_INTLEVEL_SHIFT 0 /* position of INTLEVEL bits in PS, starting from lsbit */
1109#define XCHAL_PS_INTLEVEL_MASK 0x0000000F /* mask of bits in INTLEVEL field of PS */
1110/* EXCM field: */
1111#define XCHAL_PS_EXCM_BITS 1 /* number of bits in EXCM field */
1112#define XCHAL_PS_EXCM_NUM 2 /* max number of possible causes (2^bits) */
1113#define XCHAL_PS_EXCM_SHIFT 4 /* position of EXCM bits in PS, starting from lsbit */
1114#define XCHAL_PS_EXCM_MASK 0x00000010 /* mask of bits in EXCM field of PS */
1115/* PROGSTACK field: */
1116#define XCHAL_PS_PROGSTACK_BITS 1 /* number of bits in PROGSTACK field */
1117#define XCHAL_PS_PROGSTACK_NUM 2 /* max number of possible causes (2^bits) */
1118#define XCHAL_PS_PROGSTACK_SHIFT 5 /* position of PROGSTACK bits in PS, starting from lsbit */
1119#define XCHAL_PS_PROGSTACK_MASK 0x00000020 /* mask of bits in PROGSTACK field of PS */
1120/* RING field: */
1121#define XCHAL_PS_RING_BITS 2 /* number of bits in RING field */
1122#define XCHAL_PS_RING_NUM 4 /* max number of possible causes (2^bits) */
1123#define XCHAL_PS_RING_SHIFT 6 /* position of RING bits in PS, starting from lsbit */
1124#define XCHAL_PS_RING_MASK 0x000000C0 /* mask of bits in RING field of PS */
1125/* OWB field: */
1126#define XCHAL_PS_OWB_BITS 4 /* number of bits in OWB field */
1127#define XCHAL_PS_OWB_NUM 16 /* max number of possible causes (2^bits) */
1128#define XCHAL_PS_OWB_SHIFT 8 /* position of OWB bits in PS, starting from lsbit */
1129#define XCHAL_PS_OWB_MASK 0x00000F00 /* mask of bits in OWB field of PS */
1130/* CALLINC field: */
1131#define XCHAL_PS_CALLINC_BITS 2 /* number of bits in CALLINC field */
1132#define XCHAL_PS_CALLINC_NUM 4 /* max number of possible causes (2^bits) */
1133#define XCHAL_PS_CALLINC_SHIFT 16 /* position of CALLINC bits in PS, starting from lsbit */
1134#define XCHAL_PS_CALLINC_MASK 0x00030000 /* mask of bits in CALLINC field of PS */
1135/* WOE field: */
1136#define XCHAL_PS_WOE_BITS 1 /* number of bits in WOE field */
1137#define XCHAL_PS_WOE_NUM 2 /* max number of possible causes (2^bits) */
1138#define XCHAL_PS_WOE_SHIFT 18 /* position of WOE bits in PS, starting from lsbit */
1139#define XCHAL_PS_WOE_MASK 0x00040000 /* mask of bits in WOE field of PS */
1140
1141/* EXCCAUSE (special register number 232): */
1142#define XCHAL_EXCCAUSE_VALIDMASK 0x0000003F /* bits of EXCCAUSE that are defined */
1143/* EXCCAUSE field: */
1144#define XCHAL_EXCCAUSE_BITS 6 /* number of bits in EXCCAUSE register */
1145#define XCHAL_EXCCAUSE_NUM 64 /* max number of possible causes (2^bits) */
1146#define XCHAL_EXCCAUSE_SHIFT 0 /* position of EXCCAUSE bits in register, starting from lsbit */
1147#define XCHAL_EXCCAUSE_MASK 0x0000003F /* mask of bits in EXCCAUSE register */
1148
1149/* DEBUGCAUSE (special register number 233): */
1150#define XCHAL_DEBUGCAUSE_VALIDMASK 0x0000003F /* bits of DEBUGCAUSE that are defined */
1151/* ICOUNT field: */
1152#define XCHAL_DEBUGCAUSE_ICOUNT_BITS 1 /* number of bits in ICOUNT field */
1153#define XCHAL_DEBUGCAUSE_ICOUNT_NUM 2 /* max number of possible causes (2^bits) */
1154#define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT 0 /* position of ICOUNT bits in DEBUGCAUSE, starting from lsbit */
1155#define XCHAL_DEBUGCAUSE_ICOUNT_MASK 0x00000001 /* mask of bits in ICOUNT field of DEBUGCAUSE */
1156/* IBREAK field: */
1157#define XCHAL_DEBUGCAUSE_IBREAK_BITS 1 /* number of bits in IBREAK field */
1158#define XCHAL_DEBUGCAUSE_IBREAK_NUM 2 /* max number of possible causes (2^bits) */
1159#define XCHAL_DEBUGCAUSE_IBREAK_SHIFT 1 /* position of IBREAK bits in DEBUGCAUSE, starting from lsbit */
1160#define XCHAL_DEBUGCAUSE_IBREAK_MASK 0x00000002 /* mask of bits in IBREAK field of DEBUGCAUSE */
1161/* DBREAK field: */
1162#define XCHAL_DEBUGCAUSE_DBREAK_BITS 1 /* number of bits in DBREAK field */
1163#define XCHAL_DEBUGCAUSE_DBREAK_NUM 2 /* max number of possible causes (2^bits) */
1164#define XCHAL_DEBUGCAUSE_DBREAK_SHIFT 2 /* position of DBREAK bits in DEBUGCAUSE, starting from lsbit */
1165#define XCHAL_DEBUGCAUSE_DBREAK_MASK 0x00000004 /* mask of bits in DBREAK field of DEBUGCAUSE */
1166/* BREAK field: */
1167#define XCHAL_DEBUGCAUSE_BREAK_BITS 1 /* number of bits in BREAK field */
1168#define XCHAL_DEBUGCAUSE_BREAK_NUM 2 /* max number of possible causes (2^bits) */
1169#define XCHAL_DEBUGCAUSE_BREAK_SHIFT 3 /* position of BREAK bits in DEBUGCAUSE, starting from lsbit */
1170#define XCHAL_DEBUGCAUSE_BREAK_MASK 0x00000008 /* mask of bits in BREAK field of DEBUGCAUSE */
1171/* BREAKN field: */
1172#define XCHAL_DEBUGCAUSE_BREAKN_BITS 1 /* number of bits in BREAKN field */
1173#define XCHAL_DEBUGCAUSE_BREAKN_NUM 2 /* max number of possible causes (2^bits) */
1174#define XCHAL_DEBUGCAUSE_BREAKN_SHIFT 4 /* position of BREAKN bits in DEBUGCAUSE, starting from lsbit */
1175#define XCHAL_DEBUGCAUSE_BREAKN_MASK 0x00000010 /* mask of bits in BREAKN field of DEBUGCAUSE */
1176/* DEBUGINT field: */
1177#define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 1 /* number of bits in DEBUGINT field */
1178#define XCHAL_DEBUGCAUSE_DEBUGINT_NUM 2 /* max number of possible causes (2^bits) */
1179#define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5 /* position of DEBUGINT bits in DEBUGCAUSE, starting from lsbit */
1180#define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 0x00000020 /* mask of bits in DEBUGINT field of DEBUGCAUSE */
1181
1182
1183
1184/*----------------------------------------------------------------------
1185 ISA
1186 ----------------------------------------------------------------------*/
1187
1188#define XCHAL_HAVE_DENSITY 1 /* 1 if density option configured, 0 otherwise */
1189#define XCHAL_HAVE_LOOPS 1 /* 1 if zero-overhead loops option configured, 0 otherwise */
1190/* Misc instructions: */
1191#define XCHAL_HAVE_NSA 0 /* 1 if NSA/NSAU instructions option configured, 0 otherwise */
1192#define XCHAL_HAVE_MINMAX 0 /* 1 if MIN/MAX instructions option configured, 0 otherwise */
1193#define XCHAL_HAVE_SEXT 0 /* 1 if sign-extend instruction option configured, 0 otherwise */
1194#define XCHAL_HAVE_CLAMPS 0 /* 1 if CLAMPS instruction option configured, 0 otherwise */
1195#define XCHAL_HAVE_MAC16 0 /* 1 if MAC16 option configured, 0 otherwise */
1196#define XCHAL_HAVE_MUL16 0 /* 1 if 16-bit integer multiply option configured, 0 otherwise */
1197/*#define XCHAL_HAVE_POPC 0*/ /* 1 if CRC instruction option configured, 0 otherwise */
1198/*#define XCHAL_HAVE_CRC 0*/ /* 1 if POPC instruction option configured, 0 otherwise */
1199
1200#define XCHAL_HAVE_SPECULATION 0 /* 1 if speculation option configured, 0 otherwise */
1201/*#define XCHAL_HAVE_MP_SYNC 0*/ /* 1 if multiprocessor sync. option configured, 0 otherwise */
1202#define XCHAL_HAVE_PRID 0 /* 1 if processor ID register configured, 0 otherwise */
1203
1204#define XCHAL_NUM_MISC_REGS 2 /* number of miscellaneous registers (0..4) */
1205
1206/* These relate a bit more to TIE: */
1207#define XCHAL_HAVE_BOOLEANS 0 /* 1 if booleans option configured, 0 otherwise */
1208#define XCHAL_HAVE_MUL32 0 /* 1 if 32-bit integer multiply option configured, 0 otherwise */
1209#define XCHAL_HAVE_MUL32_HIGH 0 /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
1210#define XCHAL_HAVE_FP 0 /* 1 if floating point option configured, 0 otherwise */
1211
1212
1213/*----------------------------------------------------------------------
1214 DERIVED
1215 ----------------------------------------------------------------------*/
1216
1217#if XCHAL_HAVE_BE
1218#define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, msb-first */
1219#define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, 1st byte */
1220#define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, 2nd byte */
1221#else
1222#define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, lsb-first */
1223#define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, 1st byte */
1224#define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, 2nd byte */
1225#endif
1226/* Belongs in xtensa/hal.h: */
1227#define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */
1228
1229
1230/*
1231 * Because information as to exactly which hardware release is targeted
1232 * by a given software build is not always available, compile-time HAL
1233 * Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE):
1234 */
1235#ifndef XCHAL_HW_RELEASE_MAJOR
1236# define XCHAL_HW_CONFIGID_RELIABLE 0
1237#endif
1238#if XCHAL_HW_CONFIGID_RELIABLE
1239# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
1240# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
1241# define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
1242# define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_RELEASE_MAJOR == (major)) ? 1 : 0)
1243#else
1244# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \
1245 : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \
1246 : XTHAL_MAYBE )
1247# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \
1248 : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \
1249 : XTHAL_MAYBE )
1250# define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \
1251 ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE)
1252# define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0)
1253#endif
1254
1255/*
1256 * Specific errata:
1257 */
1258
1259/*
1260 * Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1;
1261 * relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled):
1262 */
1263#define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN (XCHAL_HAVE_XEA1 && \
1264 (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \
1265 || XCHAL_HW_RELEASE_AT(1050,0)))
1266
1267
1268
1269#endif /*XTENSA_CONFIG_CORE_H*/
1270
diff --git a/include/asm-xtensa/xtensa/config-linux_be/defs.h b/include/asm-xtensa/xtensa/config-linux_be/defs.h
deleted file mode 100644
index f7c58b273371..000000000000
--- a/include/asm-xtensa/xtensa/config-linux_be/defs.h
+++ /dev/null
@@ -1,270 +0,0 @@
1/* Definitions for Xtensa instructions, types, and protos. */
2
3/*
4 * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of version 2.1 of the GNU Lesser General Public
8 * License as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it would be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 * Further, this software is distributed without any warranty that it is
15 * free of the rightful claim of any third person regarding infringement
16 * or the like. Any license provided herein, whether implied or
17 * otherwise, applies only to this software file. Patent licenses, if
18 * any, provided herein do not apply to combinations of this program with
19 * other software, or any other product whatsoever.
20 *
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with this program; if not, write the Free Software
23 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
24 * USA.
25 */
26
27/* Do not modify. This is automatically generated.*/
28
29#ifndef _XTENSA_BASE_HEADER
30#define _XTENSA_BASE_HEADER
31
32#ifdef __XTENSA__
33#if defined(__GNUC__) && !defined(__XCC__)
34
35#define L8UI_ASM(arr, ars, imm) { \
36 __asm__ volatile("l8ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
37}
38
39#define XT_L8UI(ars, imm) \
40({ \
41 unsigned char _arr; \
42 const unsigned char *_ars = ars; \
43 L8UI_ASM(_arr, _ars, imm); \
44 _arr; \
45})
46
47#define L16UI_ASM(arr, ars, imm) { \
48 __asm__ volatile("l16ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
49}
50
51#define XT_L16UI(ars, imm) \
52({ \
53 unsigned short _arr; \
54 const unsigned short *_ars = ars; \
55 L16UI_ASM(_arr, _ars, imm); \
56 _arr; \
57})
58
59#define L16SI_ASM(arr, ars, imm) {\
60 __asm__ volatile("l16si %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
61}
62
63#define XT_L16SI(ars, imm) \
64({ \
65 signed short _arr; \
66 const signed short *_ars = ars; \
67 L16SI_ASM(_arr, _ars, imm); \
68 _arr; \
69})
70
71#define L32I_ASM(arr, ars, imm) { \
72 __asm__ volatile("l32i %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
73}
74
75#define XT_L32I(ars, imm) \
76({ \
77 unsigned _arr; \
78 const unsigned *_ars = ars; \
79 L32I_ASM(_arr, _ars, imm); \
80 _arr; \
81})
82
83#define S8I_ASM(arr, ars, imm) {\
84 __asm__ volatile("s8i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
85}
86
87#define XT_S8I(arr, ars, imm) \
88({ \
89 signed char _arr = arr; \
90 const signed char *_ars = ars; \
91 S8I_ASM(_arr, _ars, imm); \
92})
93
94#define S16I_ASM(arr, ars, imm) {\
95 __asm__ volatile("s16i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
96}
97
98#define XT_S16I(arr, ars, imm) \
99({ \
100 signed short _arr = arr; \
101 const signed short *_ars = ars; \
102 S16I_ASM(_arr, _ars, imm); \
103})
104
105#define S32I_ASM(arr, ars, imm) { \
106 __asm__ volatile("s32i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
107}
108
109#define XT_S32I(arr, ars, imm) \
110({ \
111 signed int _arr = arr; \
112 const signed int *_ars = ars; \
113 S32I_ASM(_arr, _ars, imm); \
114})
115
116#define ADDI_ASM(art, ars, imm) {\
117 __asm__ ("addi %0, %1, %2" : "=a" (art) : "a" (ars), "i" (imm)); \
118}
119
120#define XT_ADDI(ars, imm) \
121({ \
122 unsigned _art; \
123 unsigned _ars = ars; \
124 ADDI_ASM(_art, _ars, imm); \
125 _art; \
126})
127
128#define ABS_ASM(arr, art) {\
129 __asm__ ("abs %0, %1" : "=a" (arr) : "a" (art)); \
130}
131
132#define XT_ABS(art) \
133({ \
134 unsigned _arr; \
135 signed _art = art; \
136 ABS_ASM(_arr, _art); \
137 _arr; \
138})
139
140/* Note: In the following macros that reference SAR, the magic "state"
141 register is used to capture the dependency on SAR. This is because
142 SAR is a 5-bit register and thus there are no C types that can be
143 used to represent it. It doesn't appear that the SAR register is
144 even relevant to GCC, but it is marked as "clobbered" just in
145 case. */
146
147#define SRC_ASM(arr, ars, art) {\
148 register int _xt_sar __asm__ ("state"); \
149 __asm__ ("src %0, %1, %2" \
150 : "=a" (arr) : "a" (ars), "a" (art), "t" (_xt_sar)); \
151}
152
153#define XT_SRC(ars, art) \
154({ \
155 unsigned _arr; \
156 unsigned _ars = ars; \
157 unsigned _art = art; \
158 SRC_ASM(_arr, _ars, _art); \
159 _arr; \
160})
161
162#define SSR_ASM(ars) {\
163 register int _xt_sar __asm__ ("state"); \
164 __asm__ ("ssr %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
165}
166
167#define XT_SSR(ars) \
168({ \
169 unsigned _ars = ars; \
170 SSR_ASM(_ars); \
171})
172
173#define SSL_ASM(ars) {\
174 register int _xt_sar __asm__ ("state"); \
175 __asm__ ("ssl %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
176}
177
178#define XT_SSL(ars) \
179({ \
180 unsigned _ars = ars; \
181 SSL_ASM(_ars); \
182})
183
184#define SSA8B_ASM(ars) {\
185 register int _xt_sar __asm__ ("state"); \
186 __asm__ ("ssa8b %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
187}
188
189#define XT_SSA8B(ars) \
190({ \
191 unsigned _ars = ars; \
192 SSA8B_ASM(_ars); \
193})
194
195#define SSA8L_ASM(ars) {\
196 register int _xt_sar __asm__ ("state"); \
197 __asm__ ("ssa8l %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
198}
199
200#define XT_SSA8L(ars) \
201({ \
202 unsigned _ars = ars; \
203 SSA8L_ASM(_ars); \
204})
205
206#define SSAI_ASM(imm) {\
207 register int _xt_sar __asm__ ("state"); \
208 __asm__ ("ssai %1" : "=t" (_xt_sar) : "i" (imm) : "sar"); \
209}
210
211#define XT_SSAI(imm) \
212({ \
213 SSAI_ASM(imm); \
214})
215
216
217
218
219
220
221
222
223#endif /* __GNUC__ && !__XCC__ */
224
225#ifdef __XCC__
226
227/* Core load/store instructions */
228extern unsigned char _TIE_L8UI(const unsigned char * ars, immediate imm);
229extern unsigned short _TIE_L16UI(const unsigned short * ars, immediate imm);
230extern signed short _TIE_L16SI(const signed short * ars, immediate imm);
231extern unsigned _TIE_L32I(const unsigned * ars, immediate imm);
232extern void _TIE_S8I(unsigned char arr, unsigned char * ars, immediate imm);
233extern void _TIE_S16I(unsigned short arr, unsigned short * ars, immediate imm);
234extern void _TIE_S32I(unsigned arr, unsigned * ars, immediate imm);
235
236#define XT_L8UI _TIE_L8UI
237#define XT_L16UI _TIE_L16UI
238#define XT_L16SI _TIE_L16SI
239#define XT_L32I _TIE_L32I
240#define XT_S8I _TIE_S8I
241#define XT_S16I _TIE_S16I
242#define XT_S32I _TIE_S32I
243
244/* Add-immediate instruction */
245extern unsigned _TIE_ADDI(unsigned ars, immediate imm);
246#define XT_ADDI _TIE_ADDI
247
248/* Absolute value instruction */
249extern unsigned _TIE_ABS(int art);
250#define XT_ABS _TIE_ABS
251
252/* funnel shift instructions */
253extern unsigned _TIE_SRC(unsigned ars, unsigned art);
254#define XT_SRC _TIE_SRC
255extern void _TIE_SSR(unsigned ars);
256#define XT_SSR _TIE_SSR
257extern void _TIE_SSL(unsigned ars);
258#define XT_SSL _TIE_SSL
259extern void _TIE_SSA8B(unsigned ars);
260#define XT_SSA8B _TIE_SSA8B
261extern void _TIE_SSA8L(unsigned ars);
262#define XT_SSA8L _TIE_SSA8L
263extern void _TIE_SSAI(immediate imm);
264#define XT_SSAI _TIE_SSAI
265
266
267#endif /* __XCC__ */
268
269#endif /* __XTENSA__ */
270#endif /* !_XTENSA_BASE_HEADER */
diff --git a/include/asm-xtensa/xtensa/config-linux_be/specreg.h b/include/asm-xtensa/xtensa/config-linux_be/specreg.h
deleted file mode 100644
index fa4106aa9a02..000000000000
--- a/include/asm-xtensa/xtensa/config-linux_be/specreg.h
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * Xtensa Special Register symbolic names
3 */
4
5/* $Id: specreg.h,v 1.2 2003/03/07 19:15:18 joetaylor Exp $ */
6
7/*
8 * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2.1 of the GNU Lesser General Public
12 * License as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it would be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
17 *
18 * Further, this software is distributed without any warranty that it is
19 * free of the rightful claim of any third person regarding infringement
20 * or the like. Any license provided herein, whether implied or
21 * otherwise, applies only to this software file. Patent licenses, if
22 * any, provided herein do not apply to combinations of this program with
23 * other software, or any other product whatsoever.
24 *
25 * You should have received a copy of the GNU Lesser General Public
26 * License along with this program; if not, write the Free Software
27 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
28 * USA.
29 */
30
31#ifndef XTENSA_SPECREG_H
32#define XTENSA_SPECREG_H
33
34/* Include these special register bitfield definitions, for historical reasons: */
35#include <xtensa/corebits.h>
36
37
38/* Special registers: */
39#define LBEG 0
40#define LEND 1
41#define LCOUNT 2
42#define SAR 3
43#define WINDOWBASE 72
44#define WINDOWSTART 73
45#define PTEVADDR 83
46#define RASID 90
47#define ITLBCFG 91
48#define DTLBCFG 92
49#define IBREAKENABLE 96
50#define DDR 104
51#define IBREAKA_0 128
52#define IBREAKA_1 129
53#define DBREAKA_0 144
54#define DBREAKA_1 145
55#define DBREAKC_0 160
56#define DBREAKC_1 161
57#define EPC_1 177
58#define EPC_2 178
59#define EPC_3 179
60#define EPC_4 180
61#define DEPC 192
62#define EPS_2 194
63#define EPS_3 195
64#define EPS_4 196
65#define EXCSAVE_1 209
66#define EXCSAVE_2 210
67#define EXCSAVE_3 211
68#define EXCSAVE_4 212
69#define INTERRUPT 226
70#define INTENABLE 228
71#define PS 230
72#define EXCCAUSE 232
73#define DEBUGCAUSE 233
74#define CCOUNT 234
75#define ICOUNT 236
76#define ICOUNTLEVEL 237
77#define EXCVADDR 238
78#define CCOMPARE_0 240
79#define CCOMPARE_1 241
80#define CCOMPARE_2 242
81#define MISC_REG_0 244
82#define MISC_REG_1 245
83
84/* Special cases (bases of special register series): */
85#define IBREAKA 128
86#define DBREAKA 144
87#define DBREAKC 160
88#define EPC 176
89#define EPS 192
90#define EXCSAVE 208
91#define CCOMPARE 240
92
93/* Special names for read-only and write-only interrupt registers: */
94#define INTREAD 226
95#define INTSET 226
96#define INTCLEAR 227
97
98#endif /* XTENSA_SPECREG_H */
99
diff --git a/include/asm-xtensa/xtensa/config-linux_be/system.h b/include/asm-xtensa/xtensa/config-linux_be/system.h
deleted file mode 100644
index cf9d4d308e3a..000000000000
--- a/include/asm-xtensa/xtensa/config-linux_be/system.h
+++ /dev/null
@@ -1,198 +0,0 @@
1/*
2 * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
3 *
4 * NOTE: The location and contents of this file are highly subject to change.
5 *
6 * Source for configuration-independent binaries (which link in a
7 * configuration-specific HAL library) must NEVER include this file.
8 * The HAL itself has historically included this file in some instances,
9 * but this is not appropriate either, because the HAL is meant to be
10 * core-specific but system independent.
11 */
12
13/*
14 * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of version 2.1 of the GNU Lesser General Public
18 * License as published by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it would be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
23 *
24 * Further, this software is distributed without any warranty that it is
25 * free of the rightful claim of any third person regarding infringement
26 * or the like. Any license provided herein, whether implied or
27 * otherwise, applies only to this software file. Patent licenses, if
28 * any, provided herein do not apply to combinations of this program with
29 * other software, or any other product whatsoever.
30 *
31 * You should have received a copy of the GNU Lesser General Public
32 * License along with this program; if not, write the Free Software
33 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
34 * USA.
35 */
36
37
38#ifndef XTENSA_CONFIG_SYSTEM_H
39#define XTENSA_CONFIG_SYSTEM_H
40
41/*#include <xtensa/hal.h>*/
42
43
44
45/*----------------------------------------------------------------------
46 DEVICE ADDRESSES
47 ----------------------------------------------------------------------*/
48
49/*
50 * Strange place to find these, but the configuration GUI
51 * allows moving these around to account for various core
52 * configurations. Specific boards (and their BSP software)
53 * will have specific meanings for these components.
54 */
55
56/* I/O Block areas: */
57#define XSHAL_IOBLOCK_CACHED_VADDR 0xE0000000
58#define XSHAL_IOBLOCK_CACHED_PADDR 0xF0000000
59#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000
60
61#define XSHAL_IOBLOCK_BYPASS_VADDR 0xF0000000
62#define XSHAL_IOBLOCK_BYPASS_PADDR 0xF0000000
63#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
64
65/* System ROM: */
66#define XSHAL_ROM_VADDR 0xEE000000
67#define XSHAL_ROM_PADDR 0xFE000000
68#define XSHAL_ROM_SIZE 0x00400000
69/* Largest available area (free of vectors): */
70#define XSHAL_ROM_AVAIL_VADDR 0xEE00052C
71#define XSHAL_ROM_AVAIL_VSIZE 0x003FFAD4
72
73/* System RAM: */
74#define XSHAL_RAM_VADDR 0xD0000000
75#define XSHAL_RAM_PADDR 0x00000000
76#define XSHAL_RAM_VSIZE 0x08000000
77#define XSHAL_RAM_PSIZE 0x10000000
78#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
79/* Largest available area (free of vectors): */
80#define XSHAL_RAM_AVAIL_VADDR 0xD0000370
81#define XSHAL_RAM_AVAIL_VSIZE 0x07FFFC90
82
83/*
84 * Shadow system RAM (same device as system RAM, at different address).
85 * (Emulation boards need this for the SONIC Ethernet driver
86 * when data caches are configured for writeback mode.)
87 * NOTE: on full MMU configs, this points to the BYPASS virtual address
88 * of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
89 * addresses are viewed through the BYPASS static map rather than
90 * the CACHED static map.
91 */
92#define XSHAL_RAM_BYPASS_VADDR 0xD8000000
93#define XSHAL_RAM_BYPASS_PADDR 0x00000000
94#define XSHAL_RAM_BYPASS_PSIZE 0x08000000
95
96/* Alternate system RAM (different device than system RAM): */
97#define XSHAL_ALTRAM_VADDR 0xCEE00000
98#define XSHAL_ALTRAM_PADDR 0xC0000000
99#define XSHAL_ALTRAM_SIZE 0x00200000
100
101
102/*----------------------------------------------------------------------
103 * DEVICE-ADDRESS DEPENDENT...
104 *
105 * Values written to CACHEATTR special register (or its equivalent)
106 * to enable and disable caches in various modes.
107 *----------------------------------------------------------------------*/
108
109/*----------------------------------------------------------------------
110 BACKWARD COMPATIBILITY ...
111 ----------------------------------------------------------------------*/
112
113/*
114 * NOTE: the following two macros are DEPRECATED. Use the latter
115 * board-specific macros instead, which are specially tuned for the
116 * particular target environments' memory maps.
117 */
118#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
119#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */
120
121/*----------------------------------------------------------------------
122 ISS (Instruction Set Simulator) SPECIFIC ...
123 ----------------------------------------------------------------------*/
124
125#define XSHAL_ISS_CACHEATTR_WRITEBACK 0x1122222F /* enable caches in write-back mode */
126#define XSHAL_ISS_CACHEATTR_WRITEALLOC 0x1122222F /* enable caches in write-allocate mode */
127#define XSHAL_ISS_CACHEATTR_WRITETHRU 0x1122222F /* enable caches in write-through mode */
128#define XSHAL_ISS_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
129#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_ISS_CACHEATTR_WRITEBACK /* default setting to enable caches */
130
131/* For Coware only: */
132#define XSHAL_COWARE_CACHEATTR_WRITEBACK 0x11222222 /* enable caches in write-back mode */
133#define XSHAL_COWARE_CACHEATTR_WRITEALLOC 0x11222222 /* enable caches in write-allocate mode */
134#define XSHAL_COWARE_CACHEATTR_WRITETHRU 0x11222222 /* enable caches in write-through mode */
135#define XSHAL_COWARE_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */
136#define XSHAL_COWARE_CACHEATTR_DEFAULT XSHAL_COWARE_CACHEATTR_WRITEBACK /* default setting to enable caches */
137
138/* For BFM and other purposes: */
139#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x11222222 /* enable caches without any invalid regions */
140#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting for caches without any invalid regions */
141
142#define XSHAL_ISS_PIPE_REGIONS 0
143#define XSHAL_ISS_SDRAM_REGIONS 0
144
145
146/*----------------------------------------------------------------------
147 XT2000 BOARD SPECIFIC ...
148 ----------------------------------------------------------------------*/
149
150#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0x22FFFFFF /* enable caches in write-back mode */
151#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0x22FFFFFF /* enable caches in write-allocate mode */
152#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0x22FFFFFF /* enable caches in write-through mode */
153#define XSHAL_XT2000_CACHEATTR_BYPASS 0x22FFFFFF /* disable caches in bypass mode */
154#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */
155
156#define XSHAL_XT2000_PIPE_REGIONS 0x00001000 /* BusInt pipeline regions */
157#define XSHAL_XT2000_SDRAM_REGIONS 0x00000005 /* BusInt SDRAM regions */
158
159
160/*----------------------------------------------------------------------
161 VECTOR SIZES
162 ----------------------------------------------------------------------*/
163
164/*
165 * Sizes allocated to vectors by the system (memory map) configuration.
166 * These sizes are constrained by core configuration (eg. one vector's
167 * code cannot overflow into another vector) but are dependent on the
168 * system or board (or LSP) memory map configuration.
169 *
170 * Whether or not each vector happens to be in a system ROM is also
171 * a system configuration matter, sometimes useful, included here also:
172 */
173#define XSHAL_RESET_VECTOR_SIZE 0x000004E0
174#define XSHAL_RESET_VECTOR_ISROM 1
175#define XSHAL_USER_VECTOR_SIZE 0x0000001C
176#define XSHAL_USER_VECTOR_ISROM 0
177#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
178#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
179#define XSHAL_KERNEL_VECTOR_SIZE 0x0000001C
180#define XSHAL_KERNEL_VECTOR_ISROM 0
181#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
182#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
183#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x000000E0
184#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
185#define XSHAL_WINDOW_VECTORS_SIZE 0x00000180
186#define XSHAL_WINDOW_VECTORS_ISROM 0
187#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x0000000C
188#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
189#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x0000000C
190#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
191#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x0000000C
192#define XSHAL_INTLEVEL4_VECTOR_ISROM 1
193#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL4_VECTOR_SIZE
194#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL4_VECTOR_ISROM
195
196
197#endif /*XTENSA_CONFIG_SYSTEM_H*/
198
diff --git a/include/asm-xtensa/xtensa/config-linux_be/tie.h b/include/asm-xtensa/xtensa/config-linux_be/tie.h
deleted file mode 100644
index 07c6d1ca4589..000000000000
--- a/include/asm-xtensa/xtensa/config-linux_be/tie.h
+++ /dev/null
@@ -1,275 +0,0 @@
1/*
2 * xtensa/config/tie.h -- HAL definitions that are dependent on CORE and TIE configuration
3 *
4 * This header file is sometimes referred to as the "compile-time HAL" or CHAL.
5 * It was generated for a specific Xtensa processor configuration,
6 * and furthermore for a specific set of TIE source files that extend
7 * basic core functionality.
8 *
9 * Source for configuration-independent binaries (which link in a
10 * configuration-specific HAL library) must NEVER include this file.
11 * It is perfectly normal, however, for the HAL source itself to include this file.
12 */
13
14/*
15 * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of version 2.1 of the GNU Lesser General Public
19 * License as published by the Free Software Foundation.
20 *
21 * This program is distributed in the hope that it would be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
24 *
25 * Further, this software is distributed without any warranty that it is
26 * free of the rightful claim of any third person regarding infringement
27 * or the like. Any license provided herein, whether implied or
28 * otherwise, applies only to this software file. Patent licenses, if
29 * any, provided herein do not apply to combinations of this program with
30 * other software, or any other product whatsoever.
31 *
32 * You should have received a copy of the GNU Lesser General Public
33 * License along with this program; if not, write the Free Software
34 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
35 * USA.
36 */
37
38
39#ifndef XTENSA_CONFIG_TIE_H
40#define XTENSA_CONFIG_TIE_H
41
42#include <xtensa/hal.h>
43
44
45/*----------------------------------------------------------------------
46 GENERAL
47 ----------------------------------------------------------------------*/
48
49/*
50 * Separators for macros that expand into arrays.
51 * These can be predefined by files that #include this one,
52 * when different separators are required.
53 */
54/* Element separator for macros that expand into 1-dimensional arrays: */
55#ifndef XCHAL_SEP
56#define XCHAL_SEP ,
57#endif
58/* Array separator for macros that expand into 2-dimensional arrays: */
59#ifndef XCHAL_SEP2
60#define XCHAL_SEP2 },{
61#endif
62
63
64
65
66
67
68/*----------------------------------------------------------------------
69 COPROCESSORS and EXTRA STATE
70 ----------------------------------------------------------------------*/
71
72#define XCHAL_CP_NUM 0 /* number of coprocessors */
73#define XCHAL_CP_MAX 0 /* max coprocessor id plus one (0 if none) */
74#define XCHAL_CP_MASK 0x00 /* bitmask of coprocessors by id */
75
76/* Space for coprocessors' state save areas: */
77#define XCHAL_CP0_SA_SIZE 0
78#define XCHAL_CP1_SA_SIZE 0
79#define XCHAL_CP2_SA_SIZE 0
80#define XCHAL_CP3_SA_SIZE 0
81#define XCHAL_CP4_SA_SIZE 0
82#define XCHAL_CP5_SA_SIZE 0
83#define XCHAL_CP6_SA_SIZE 0
84#define XCHAL_CP7_SA_SIZE 0
85/* Minimum required alignments of CP state save areas: */
86#define XCHAL_CP0_SA_ALIGN 1
87#define XCHAL_CP1_SA_ALIGN 1
88#define XCHAL_CP2_SA_ALIGN 1
89#define XCHAL_CP3_SA_ALIGN 1
90#define XCHAL_CP4_SA_ALIGN 1
91#define XCHAL_CP5_SA_ALIGN 1
92#define XCHAL_CP6_SA_ALIGN 1
93#define XCHAL_CP7_SA_ALIGN 1
94
95/* Indexing macros: */
96#define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE
97#define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */
98#define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN
99#define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */
100
101
102/* Space for "extra" state (user special registers and non-cp TIE) save area: */
103#define XCHAL_EXTRA_SA_SIZE 0
104#define XCHAL_EXTRA_SA_ALIGN 1
105
106/* Total save area size (extra + all coprocessors) */
107/* (not useful until xthal_{save,restore}_all_extra() is implemented, */
108/* but included for Tor2 beta; doesn't account for alignment!): */
109#define XCHAL_CPEXTRA_SA_SIZE_TOR2 0 /* Tor2Beta temporary definition -- do not use */
110
111/* Combined required alignment for all CP and EXTRA state save areas */
112/* (does not include required alignment for any base config registers): */
113#define XCHAL_CPEXTRA_SA_ALIGN 1
114
115/* ... */
116
117
118#ifdef __ASSEMBLER__
119/*
120 * Assembly-language specific definitions (assembly macros, etc.).
121 */
122#include <xtensa/config/specreg.h>
123
124/********************
125 * Macros to save and restore the non-coprocessor TIE portion of EXTRA state.
126 */
127
128/* (none) */
129
130
131/********************
132 * Macros to create functions that save and restore all EXTRA (non-coprocessor) state
133 * (does not include zero-overhead loop registers and non-optional registers).
134 */
135
136 /*
137 * Macro that expands to the body of a function that
138 * stores the extra (non-coprocessor) optional/custom state.
139 * Entry: a2 = ptr to save area in which to save extra state
140 * Exit: any register a2-a15 (?) may have been clobbered.
141 */
142 .macro xchal_extra_store_funcbody
143 .endm
144
145
146 /*
147 * Macro that expands to the body of a function that
148 * loads the extra (non-coprocessor) optional/custom state.
149 * Entry: a2 = ptr to save area from which to restore extra state
150 * Exit: any register a2-a15 (?) may have been clobbered.
151 */
152 .macro xchal_extra_load_funcbody
153 .endm
154
155
156/********************
157 * Macros to save and restore the state of each TIE coprocessor.
158 */
159
160
161
162/********************
163 * Macros to create functions that save and restore the state of *any* TIE coprocessor.
164 */
165
166 /*
167 * Macro that expands to the body of a function
168 * that stores the selected coprocessor's state (registers etc).
169 * Entry: a2 = ptr to save area in which to save cp state
170 * a3 = coprocessor number
171 * Exit: any register a2-a15 (?) may have been clobbered.
172 */
173 .macro xchal_cpi_store_funcbody
174 .endm
175
176
177 /*
178 * Macro that expands to the body of a function
179 * that loads the selected coprocessor's state (registers etc).
180 * Entry: a2 = ptr to save area from which to restore cp state
181 * a3 = coprocessor number
182 * Exit: any register a2-a15 (?) may have been clobbered.
183 */
184 .macro xchal_cpi_load_funcbody
185 .endm
186
187#endif /*_ASMLANGUAGE*/
188
189
190/*
191 * Contents of save areas in terms of libdb register numbers.
192 * NOTE: CONTENTS_LIBDB_{UREG,REGF} macros are not defined in this file;
193 * it is up to the user of this header file to define these macros
194 * usefully before each expansion of the CONTENTS_LIBDB macros.
195 * (Fields rsv[123] are reserved for future additions; they are currently
196 * set to zero but may be set to some useful values in the future.)
197 *
198 * CONTENTS_LIBDB_SREG(libdbnum, offset, size, align, rsv1, name, sregnum, bitmask, rsv2, rsv3)
199 * CONTENTS_LIBDB_UREG(libdbnum, offset, size, align, rsv1, name, uregnum, bitmask, rsv2, rsv3)
200 * CONTENTS_LIBDB_REGF(libdbnum, offset, size, align, rsv1, name, index, numentries, contentsize, regname_base, regfile_name, rsv2, rsv3)
201 */
202
203#define XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM 0
204#define XCHAL_EXTRA_SA_CONTENTS_LIBDB /* empty */
205
206#define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0
207#define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */
208
209#define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
210#define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */
211
212#define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0
213#define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */
214
215#define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
216#define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */
217
218#define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
219#define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */
220
221#define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0
222#define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */
223
224#define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0
225#define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */
226
227#define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
228#define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */
229
230
231
232
233
234
235/*----------------------------------------------------------------------
236 MISC
237 ----------------------------------------------------------------------*/
238
239#if 0 /* is there something equivalent for user TIE? */
240#define XCHAL_CORE_ID "linux_be" /* configuration's alphanumeric core identifier
241 (CoreID) set in the Xtensa Processor Generator */
242
243#define XCHAL_BUILD_UNIQUE_ID 0x00003256 /* software build-unique ID (22-bit) */
244
245/* These definitions describe the hardware targeted by this software: */
246#define XCHAL_HW_CONFIGID0 0xC103D1FF /* config ID reg 0 value (upper 32 of 64 bits) */
247#define XCHAL_HW_CONFIGID1 0x00803256 /* config ID reg 1 value (lower 32 of 64 bits) */
248#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
249#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
250#define XCHAL_HW_RELEASE_MAJOR 1050 /* major release of targeted hardware */
251#define XCHAL_HW_RELEASE_MINOR 1 /* minor release of targeted hardware */
252#define XCHAL_HW_RELEASE_NAME "T1050.1" /* full release name of targeted hardware */
253#define XTHAL_HW_REL_T1050 1
254#define XTHAL_HW_REL_T1050_1 1
255#define XCHAL_HW_CONFIGID_RELIABLE 1
256#endif /*0*/
257
258
259
260/*----------------------------------------------------------------------
261 ISA
262 ----------------------------------------------------------------------*/
263
264#if 0 /* these probably don't belong here, but are related to or implemented using TIE */
265#define XCHAL_HAVE_BOOLEANS 0 /* 1 if booleans option configured, 0 otherwise */
266/* Misc instructions: */
267#define XCHAL_HAVE_MUL32 0 /* 1 if 32-bit integer multiply option configured, 0 otherwise */
268#define XCHAL_HAVE_MUL32_HIGH 0 /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
269
270#define XCHAL_HAVE_FP 0 /* 1 if floating point option configured, 0 otherwise */
271#endif /*0*/
272
273
274#endif /*XTENSA_CONFIG_TIE_H*/
275
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