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-rw-r--r--include/asm-x86_64/hardirq.h3
-rw-r--r--include/asm-x86_64/hw_irq.h8
-rw-r--r--include/asm-x86_64/hypertransport.h42
-rw-r--r--include/asm-x86_64/io_apic.h43
-rw-r--r--include/asm-x86_64/irq.h7
-rw-r--r--include/asm-x86_64/msi.h24
-rw-r--r--include/asm-x86_64/msidef.h47
7 files changed, 97 insertions, 77 deletions
diff --git a/include/asm-x86_64/hardirq.h b/include/asm-x86_64/hardirq.h
index 64a65ce2f41f..95d5e090ed89 100644
--- a/include/asm-x86_64/hardirq.h
+++ b/include/asm-x86_64/hardirq.h
@@ -6,6 +6,9 @@
6#include <asm/pda.h> 6#include <asm/pda.h>
7#include <asm/apic.h> 7#include <asm/apic.h>
8 8
9/* We can have at most NR_VECTORS irqs routed to a cpu at a time */
10#define MAX_HARDIRQS_PER_CPU NR_VECTORS
11
9#define __ARCH_IRQ_STAT 1 12#define __ARCH_IRQ_STAT 1
10 13
11#define local_softirq_pending() read_pda(__softirq_pending) 14#define local_softirq_pending() read_pda(__softirq_pending)
diff --git a/include/asm-x86_64/hw_irq.h b/include/asm-x86_64/hw_irq.h
index 48a4a5364e85..53d0d9fd10d6 100644
--- a/include/asm-x86_64/hw_irq.h
+++ b/include/asm-x86_64/hw_irq.h
@@ -19,8 +19,7 @@
19#include <asm/irq.h> 19#include <asm/irq.h>
20#include <linux/profile.h> 20#include <linux/profile.h>
21#include <linux/smp.h> 21#include <linux/smp.h>
22 22#include <linux/percpu.h>
23struct hw_interrupt_type;
24#endif 23#endif
25 24
26#define NMI_VECTOR 0x02 25#define NMI_VECTOR 0x02
@@ -75,9 +74,10 @@ struct hw_interrupt_type;
75 74
76 75
77#ifndef __ASSEMBLY__ 76#ifndef __ASSEMBLY__
78extern u8 irq_vector[NR_IRQ_VECTORS]; 77extern unsigned int irq_vector[NR_IRQ_VECTORS];
78typedef int vector_irq_t[NR_VECTORS];
79DECLARE_PER_CPU(vector_irq_t, vector_irq);
79#define IO_APIC_VECTOR(irq) (irq_vector[irq]) 80#define IO_APIC_VECTOR(irq) (irq_vector[irq])
80#define AUTO_ASSIGN -1
81 81
82/* 82/*
83 * Various low-level irq details needed by irq.c, process.c, 83 * Various low-level irq details needed by irq.c, process.c,
diff --git a/include/asm-x86_64/hypertransport.h b/include/asm-x86_64/hypertransport.h
new file mode 100644
index 000000000000..c16c6ff4bdd7
--- /dev/null
+++ b/include/asm-x86_64/hypertransport.h
@@ -0,0 +1,42 @@
1#ifndef ASM_HYPERTRANSPORT_H
2#define ASM_HYPERTRANSPORT_H
3
4/*
5 * Constants for x86 Hypertransport Interrupts.
6 */
7
8#define HT_IRQ_LOW_BASE 0xf8000000
9
10#define HT_IRQ_LOW_VECTOR_SHIFT 16
11#define HT_IRQ_LOW_VECTOR_MASK 0x00ff0000
12#define HT_IRQ_LOW_VECTOR(v) (((v) << HT_IRQ_LOW_VECTOR_SHIFT) & HT_IRQ_LOW_VECTOR_MASK)
13
14#define HT_IRQ_LOW_DEST_ID_SHIFT 8
15#define HT_IRQ_LOW_DEST_ID_MASK 0x0000ff00
16#define HT_IRQ_LOW_DEST_ID(v) (((v) << HT_IRQ_LOW_DEST_ID_SHIFT) & HT_IRQ_LOW_DEST_ID_MASK)
17
18#define HT_IRQ_LOW_DM_PHYSICAL 0x0000000
19#define HT_IRQ_LOW_DM_LOGICAL 0x0000040
20
21#define HT_IRQ_LOW_RQEOI_EDGE 0x0000000
22#define HT_IRQ_LOW_RQEOI_LEVEL 0x0000020
23
24
25#define HT_IRQ_LOW_MT_FIXED 0x0000000
26#define HT_IRQ_LOW_MT_ARBITRATED 0x0000004
27#define HT_IRQ_LOW_MT_SMI 0x0000008
28#define HT_IRQ_LOW_MT_NMI 0x000000c
29#define HT_IRQ_LOW_MT_INIT 0x0000010
30#define HT_IRQ_LOW_MT_STARTUP 0x0000014
31#define HT_IRQ_LOW_MT_EXTINT 0x0000018
32#define HT_IRQ_LOW_MT_LINT1 0x000008c
33#define HT_IRQ_LOW_MT_LINT0 0x0000098
34
35#define HT_IRQ_LOW_IRQ_MASKED 0x0000001
36
37
38#define HT_IRQ_HIGH_DEST_ID_SHIFT 0
39#define HT_IRQ_HIGH_DEST_ID_MASK 0x00ffffff
40#define HT_IRQ_HIGH_DEST_ID(v) ((((v) >> 8) << HT_IRQ_HIGH_DEST_ID_SHIFT) & HT_IRQ_HIGH_DEST_ID_MASK)
41
42#endif /* ASM_HYPERTRANSPORT_H */
diff --git a/include/asm-x86_64/io_apic.h b/include/asm-x86_64/io_apic.h
index 5d1b5c68e36e..171ec2dc8c04 100644
--- a/include/asm-x86_64/io_apic.h
+++ b/include/asm-x86_64/io_apic.h
@@ -10,46 +10,6 @@
10 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar 10 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
11 */ 11 */
12 12
13#ifdef CONFIG_PCI_MSI
14static inline int use_pci_vector(void) {return 1;}
15static inline void disable_edge_ioapic_vector(unsigned int vector) { }
16static inline void mask_and_ack_level_ioapic_vector(unsigned int vector) { }
17static inline void end_edge_ioapic_vector (unsigned int vector) { }
18#define startup_level_ioapic startup_level_ioapic_vector
19#define shutdown_level_ioapic mask_IO_APIC_vector
20#define enable_level_ioapic unmask_IO_APIC_vector
21#define disable_level_ioapic mask_IO_APIC_vector
22#define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_vector
23#define end_level_ioapic end_level_ioapic_vector
24#define set_ioapic_affinity set_ioapic_affinity_vector
25
26#define startup_edge_ioapic startup_edge_ioapic_vector
27#define shutdown_edge_ioapic disable_edge_ioapic_vector
28#define enable_edge_ioapic unmask_IO_APIC_vector
29#define disable_edge_ioapic disable_edge_ioapic_vector
30#define ack_edge_ioapic ack_edge_ioapic_vector
31#define end_edge_ioapic end_edge_ioapic_vector
32#else
33static inline int use_pci_vector(void) {return 0;}
34static inline void disable_edge_ioapic_irq(unsigned int irq) { }
35static inline void mask_and_ack_level_ioapic_irq(unsigned int irq) { }
36static inline void end_edge_ioapic_irq (unsigned int irq) { }
37#define startup_level_ioapic startup_level_ioapic_irq
38#define shutdown_level_ioapic mask_IO_APIC_irq
39#define enable_level_ioapic unmask_IO_APIC_irq
40#define disable_level_ioapic mask_IO_APIC_irq
41#define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_irq
42#define end_level_ioapic end_level_ioapic_irq
43#define set_ioapic_affinity set_ioapic_affinity_irq
44
45#define startup_edge_ioapic startup_edge_ioapic_irq
46#define shutdown_edge_ioapic disable_edge_ioapic_irq
47#define enable_edge_ioapic unmask_IO_APIC_irq
48#define disable_edge_ioapic disable_edge_ioapic_irq
49#define ack_edge_ioapic ack_edge_ioapic_irq
50#define end_edge_ioapic end_edge_ioapic_irq
51#endif
52
53#define APIC_MISMATCH_DEBUG 13#define APIC_MISMATCH_DEBUG
54 14
55#define IO_APIC_BASE(idx) \ 15#define IO_APIC_BASE(idx) \
@@ -202,13 +162,10 @@ extern int skip_ioapic_setup;
202extern int io_apic_get_version (int ioapic); 162extern int io_apic_get_version (int ioapic);
203extern int io_apic_get_redir_entries (int ioapic); 163extern int io_apic_get_redir_entries (int ioapic);
204extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int, int); 164extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int, int);
205extern int timer_uses_ioapic_pin_0;
206#endif 165#endif
207 166
208extern int sis_apic_bug; /* dummy */ 167extern int sis_apic_bug; /* dummy */
209 168
210extern int assign_irq_vector(int irq);
211
212void enable_NMI_through_LVT0 (void * dummy); 169void enable_NMI_through_LVT0 (void * dummy);
213 170
214extern spinlock_t i8259A_lock; 171extern spinlock_t i8259A_lock;
diff --git a/include/asm-x86_64/irq.h b/include/asm-x86_64/irq.h
index 43469d8ab71a..5006c6e75656 100644
--- a/include/asm-x86_64/irq.h
+++ b/include/asm-x86_64/irq.h
@@ -31,13 +31,8 @@
31 31
32#define FIRST_SYSTEM_VECTOR 0xef /* duplicated in hw_irq.h */ 32#define FIRST_SYSTEM_VECTOR 0xef /* duplicated in hw_irq.h */
33 33
34#ifdef CONFIG_PCI_MSI 34#define NR_IRQS (NR_VECTORS + (32 *NR_CPUS))
35#define NR_IRQS FIRST_SYSTEM_VECTOR
36#define NR_IRQ_VECTORS NR_IRQS 35#define NR_IRQ_VECTORS NR_IRQS
37#else
38#define NR_IRQS 224
39#define NR_IRQ_VECTORS (32 * NR_CPUS)
40#endif
41 36
42static __inline__ int irq_canonicalize(int irq) 37static __inline__ int irq_canonicalize(int irq)
43{ 38{
diff --git a/include/asm-x86_64/msi.h b/include/asm-x86_64/msi.h
deleted file mode 100644
index 3ad2346624b2..000000000000
--- a/include/asm-x86_64/msi.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * Copyright (C) 2003-2004 Intel
3 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
4 */
5
6#ifndef ASM_MSI_H
7#define ASM_MSI_H
8
9#include <asm/desc.h>
10#include <asm/mach_apic.h>
11#include <asm/smp.h>
12
13#define LAST_DEVICE_VECTOR (FIRST_SYSTEM_VECTOR - 1)
14#define MSI_TARGET_CPU_SHIFT 12
15
16extern struct msi_ops msi_apic_ops;
17
18static inline int msi_arch_init(void)
19{
20 msi_register(&msi_apic_ops);
21 return 0;
22}
23
24#endif /* ASM_MSI_H */
diff --git a/include/asm-x86_64/msidef.h b/include/asm-x86_64/msidef.h
new file mode 100644
index 000000000000..5b8acddb70fb
--- /dev/null
+++ b/include/asm-x86_64/msidef.h
@@ -0,0 +1,47 @@
1#ifndef ASM_MSIDEF_H
2#define ASM_MSIDEF_H
3
4/*
5 * Constants for Intel APIC based MSI messages.
6 */
7
8/*
9 * Shifts for MSI data
10 */
11
12#define MSI_DATA_VECTOR_SHIFT 0
13#define MSI_DATA_VECTOR_MASK 0x000000ff
14#define MSI_DATA_VECTOR(v) (((v) << MSI_DATA_VECTOR_SHIFT) & MSI_DATA_VECTOR_MASK)
15
16#define MSI_DATA_DELIVERY_MODE_SHIFT 8
17#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT)
18#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT)
19
20#define MSI_DATA_LEVEL_SHIFT 14
21#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT)
22#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT)
23
24#define MSI_DATA_TRIGGER_SHIFT 15
25#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT)
26#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT)
27
28/*
29 * Shift/mask fields for msi address
30 */
31
32#define MSI_ADDR_BASE_HI 0
33#define MSI_ADDR_BASE_LO 0xfee00000
34
35#define MSI_ADDR_DEST_MODE_SHIFT 2
36#define MSI_ADDR_DEST_MODE_PHYSICAL (0 << MSI_ADDR_DEST_MODE_SHIFT)
37#define MSI_ADDR_DEST_MODE_LOGICAL (1 << MSI_ADDR_DEST_MODE_SHIFT)
38
39#define MSI_ADDR_REDIRECTION_SHIFT 3
40#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT) /* dedicated cpu */
41#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT) /* lowest priority */
42
43#define MSI_ADDR_DEST_ID_SHIFT 12
44#define MSI_ADDR_DEST_ID_MASK 0x00ffff0
45#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & MSI_ADDR_DEST_ID_MASK)
46
47#endif /* ASM_MSIDEF_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 02:05:14 -0500