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Diffstat (limited to 'include/asm-x86_64/cpufeature.h')
-rw-r--r--include/asm-x86_64/cpufeature.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/include/asm-x86_64/cpufeature.h b/include/asm-x86_64/cpufeature.h
index ee792faaca01..0b3c686139f1 100644
--- a/include/asm-x86_64/cpufeature.h
+++ b/include/asm-x86_64/cpufeature.h
@@ -29,7 +29,7 @@
29#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */ 29#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
30#define X86_FEATURE_PN (0*32+18) /* Processor serial number */ 30#define X86_FEATURE_PN (0*32+18) /* Processor serial number */
31#define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */ 31#define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */
32#define X86_FEATURE_DTES (0*32+21) /* Debug Trace Store */ 32#define X86_FEATURE_DS (0*32+21) /* Debug Store */
33#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */ 33#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */
34#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ 34#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
35#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */ 35#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
@@ -68,6 +68,8 @@
68#define X86_FEATURE_FXSAVE_LEAK (3*32+7) /* FIP/FOP/FDP leaks through FXSAVE */ 68#define X86_FEATURE_FXSAVE_LEAK (3*32+7) /* FIP/FOP/FDP leaks through FXSAVE */
69#define X86_FEATURE_UP (3*32+8) /* SMP kernel running on UP */ 69#define X86_FEATURE_UP (3*32+8) /* SMP kernel running on UP */
70#define X86_FEATURE_ARCH_PERFMON (3*32+9) /* Intel Architectural PerfMon */ 70#define X86_FEATURE_ARCH_PERFMON (3*32+9) /* Intel Architectural PerfMon */
71#define X86_FEATURE_PEBS (3*32+10) /* Precise-Event Based Sampling */
72#define X86_FEATURE_BTS (3*32+11) /* Branch Trace Store */
71 73
72/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ 74/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
73#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ 75#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
@@ -112,5 +114,8 @@
112#define cpu_has_cyrix_arr 0 114#define cpu_has_cyrix_arr 0
113#define cpu_has_centaur_mcr 0 115#define cpu_has_centaur_mcr 0
114#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH) 116#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH)
117#define cpu_has_ds boot_cpu_has(X86_FEATURE_DS)
118#define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS)
119#define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS)
115 120
116#endif /* __ASM_X8664_CPUFEATURE_H */ 121#endif /* __ASM_X8664_CPUFEATURE_H */