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-rw-r--r--include/asm-x86/byteorder.h4
-rw-r--r--include/asm-x86/msr.h78
2 files changed, 45 insertions, 37 deletions
diff --git a/include/asm-x86/byteorder.h b/include/asm-x86/byteorder.h
index 1f2d6d5bf20d..fe2f2e5d51ba 100644
--- a/include/asm-x86/byteorder.h
+++ b/include/asm-x86/byteorder.h
@@ -30,13 +30,13 @@ static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 val)
30 } v; 30 } v;
31 v.u = val; 31 v.u = val;
32#ifdef CONFIG_X86_BSWAP 32#ifdef CONFIG_X86_BSWAP
33 asm("bswapl %0 ; bswapl %1 ; xchgl %0,%1" 33 __asm__("bswapl %0 ; bswapl %1 ; xchgl %0,%1"
34 : "=r" (v.s.a), "=r" (v.s.b) 34 : "=r" (v.s.a), "=r" (v.s.b)
35 : "0" (v.s.a), "1" (v.s.b)); 35 : "0" (v.s.a), "1" (v.s.b));
36#else 36#else
37 v.s.a = ___arch__swab32(v.s.a); 37 v.s.a = ___arch__swab32(v.s.a);
38 v.s.b = ___arch__swab32(v.s.b); 38 v.s.b = ___arch__swab32(v.s.b);
39 asm("xchgl %0,%1" : "=r" (v.s.a), "=r" (v.s.b) : "0" (v.s.a), "1" (v.s.b)); 39 __asm__("xchgl %0,%1" : "=r" (v.s.a), "=r" (v.s.b) : "0" (v.s.a), "1" (v.s.b));
40#endif 40#endif
41 return v.u; 41 return v.u;
42} 42}
diff --git a/include/asm-x86/msr.h b/include/asm-x86/msr.h
index ba4b31432120..80b027081b3c 100644
--- a/include/asm-x86/msr.h
+++ b/include/asm-x86/msr.h
@@ -3,6 +3,10 @@
3 3
4#include <asm/msr-index.h> 4#include <asm/msr-index.h>
5 5
6#ifndef __ASSEMBLY__
7# include <linux/types.h>
8#endif
9
6#ifdef __i386__ 10#ifdef __i386__
7 11
8#ifdef __KERNEL__ 12#ifdef __KERNEL__
@@ -191,38 +195,6 @@ static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
191 195
192#define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32) 196#define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
193 197
194/* wrmsr with exception handling */
195#define wrmsr_safe(msr,a,b) ({ int ret__; \
196 asm volatile("2: wrmsr ; xorl %0,%0\n" \
197 "1:\n\t" \
198 ".section .fixup,\"ax\"\n\t" \
199 "3: movl %4,%0 ; jmp 1b\n\t" \
200 ".previous\n\t" \
201 ".section __ex_table,\"a\"\n" \
202 " .align 8\n\t" \
203 " .quad 2b,3b\n\t" \
204 ".previous" \
205 : "=a" (ret__) \
206 : "c" (msr), "0" (a), "d" (b), "i" (-EFAULT)); \
207 ret__; })
208
209#define checking_wrmsrl(msr,val) wrmsr_safe(msr,(u32)(val),(u32)((val)>>32))
210
211#define rdmsr_safe(msr,a,b) \
212 ({ int ret__; \
213 asm volatile ("1: rdmsr\n" \
214 "2:\n" \
215 ".section .fixup,\"ax\"\n" \
216 "3: movl %4,%0\n" \
217 " jmp 2b\n" \
218 ".previous\n" \
219 ".section __ex_table,\"a\"\n" \
220 " .align 8\n" \
221 " .quad 1b,3b\n" \
222 ".previous":"=&bDS" (ret__), "=a"(*(a)), "=d"(*(b)) \
223 :"c"(msr), "i"(-EIO), "0"(0)); \
224 ret__; })
225
226#define rdtsc(low,high) \ 198#define rdtsc(low,high) \
227 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high)) 199 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
228 200
@@ -230,17 +202,17 @@ static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
230 __asm__ __volatile__ ("rdtsc" : "=a" (low) : : "edx") 202 __asm__ __volatile__ ("rdtsc" : "=a" (low) : : "edx")
231 203
232#define rdtscp(low,high,aux) \ 204#define rdtscp(low,high,aux) \
233 asm volatile (".byte 0x0f,0x01,0xf9" : "=a" (low), "=d" (high), "=c" (aux)) 205 __asm__ __volatile__ (".byte 0x0f,0x01,0xf9" : "=a" (low), "=d" (high), "=c" (aux))
234 206
235#define rdtscll(val) do { \ 207#define rdtscll(val) do { \
236 unsigned int __a,__d; \ 208 unsigned int __a,__d; \
237 asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \ 209 __asm__ __volatile__("rdtsc" : "=a" (__a), "=d" (__d)); \
238 (val) = ((unsigned long)__a) | (((unsigned long)__d)<<32); \ 210 (val) = ((unsigned long)__a) | (((unsigned long)__d)<<32); \
239} while(0) 211} while(0)
240 212
241#define rdtscpll(val, aux) do { \ 213#define rdtscpll(val, aux) do { \
242 unsigned long __a, __d; \ 214 unsigned long __a, __d; \
243 asm volatile (".byte 0x0f,0x01,0xf9" : "=a" (__a), "=d" (__d), "=c" (aux)); \ 215 __asm__ __volatile__ (".byte 0x0f,0x01,0xf9" : "=a" (__a), "=d" (__d), "=c" (aux)); \
244 (val) = (__d << 32) | __a; \ 216 (val) = (__d << 32) | __a; \
245} while (0) 217} while (0)
246 218
@@ -253,6 +225,7 @@ static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
253 : "=a" (low), "=d" (high) \ 225 : "=a" (low), "=d" (high) \
254 : "c" (counter)) 226 : "c" (counter))
255 227
228
256static inline void cpuid(int op, unsigned int *eax, unsigned int *ebx, 229static inline void cpuid(int op, unsigned int *eax, unsigned int *ebx,
257 unsigned int *ecx, unsigned int *edx) 230 unsigned int *ecx, unsigned int *edx)
258{ 231{
@@ -320,6 +293,40 @@ static inline unsigned int cpuid_edx(unsigned int op)
320 return edx; 293 return edx;
321} 294}
322 295
296#ifdef __KERNEL__
297
298/* wrmsr with exception handling */
299#define wrmsr_safe(msr,a,b) ({ int ret__; \
300 asm volatile("2: wrmsr ; xorl %0,%0\n" \
301 "1:\n\t" \
302 ".section .fixup,\"ax\"\n\t" \
303 "3: movl %4,%0 ; jmp 1b\n\t" \
304 ".previous\n\t" \
305 ".section __ex_table,\"a\"\n" \
306 " .align 8\n\t" \
307 " .quad 2b,3b\n\t" \
308 ".previous" \
309 : "=a" (ret__) \
310 : "c" (msr), "0" (a), "d" (b), "i" (-EFAULT)); \
311 ret__; })
312
313#define checking_wrmsrl(msr,val) wrmsr_safe(msr,(u32)(val),(u32)((val)>>32))
314
315#define rdmsr_safe(msr,a,b) \
316 ({ int ret__; \
317 asm volatile ("1: rdmsr\n" \
318 "2:\n" \
319 ".section .fixup,\"ax\"\n" \
320 "3: movl %4,%0\n" \
321 " jmp 2b\n" \
322 ".previous\n" \
323 ".section __ex_table,\"a\"\n" \
324 " .align 8\n" \
325 " .quad 1b,3b\n" \
326 ".previous":"=&bDS" (ret__), "=a"(*(a)), "=d"(*(b)) \
327 :"c"(msr), "i"(-EIO), "0"(0)); \
328 ret__; })
329
323#ifdef CONFIG_SMP 330#ifdef CONFIG_SMP
324void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); 331void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
325void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); 332void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
@@ -343,6 +350,7 @@ static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
343 return wrmsr_safe(msr_no, l, h); 350 return wrmsr_safe(msr_no, l, h);
344} 351}
345#endif /* CONFIG_SMP */ 352#endif /* CONFIG_SMP */
353#endif /* __KERNEL__ */
346#endif /* __ASSEMBLY__ */ 354#endif /* __ASSEMBLY__ */
347 355
348#endif /* !__i386__ */ 356#endif /* !__i386__ */