diff options
Diffstat (limited to 'include/asm-x86')
-rw-r--r-- | include/asm-x86/tlbflush_32.h | 7 | ||||
-rw-r--r-- | include/asm-x86/tlbflush_64.h | 9 |
2 files changed, 0 insertions, 16 deletions
diff --git a/include/asm-x86/tlbflush_32.h b/include/asm-x86/tlbflush_32.h index a50fa6741486..2bd5b95e2048 100644 --- a/include/asm-x86/tlbflush_32.h +++ b/include/asm-x86/tlbflush_32.h | |||
@@ -78,7 +78,6 @@ | |||
78 | * - flush_tlb_page(vma, vmaddr) flushes one page | 78 | * - flush_tlb_page(vma, vmaddr) flushes one page |
79 | * - flush_tlb_range(vma, start, end) flushes a range of pages | 79 | * - flush_tlb_range(vma, start, end) flushes a range of pages |
80 | * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages | 80 | * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages |
81 | * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables | ||
82 | * - flush_tlb_others(cpumask, mm, va) flushes a TLBs on other cpus | 81 | * - flush_tlb_others(cpumask, mm, va) flushes a TLBs on other cpus |
83 | * | 82 | * |
84 | * ..but the i386 has somewhat limited tlb flushing capabilities, | 83 | * ..but the i386 has somewhat limited tlb flushing capabilities, |
@@ -166,10 +165,4 @@ static inline void flush_tlb_kernel_range(unsigned long start, | |||
166 | flush_tlb_all(); | 165 | flush_tlb_all(); |
167 | } | 166 | } |
168 | 167 | ||
169 | static inline void flush_tlb_pgtables(struct mm_struct *mm, | ||
170 | unsigned long start, unsigned long end) | ||
171 | { | ||
172 | /* i386 does not keep any page table caches in TLB */ | ||
173 | } | ||
174 | |||
175 | #endif /* _I386_TLBFLUSH_H */ | 168 | #endif /* _I386_TLBFLUSH_H */ |
diff --git a/include/asm-x86/tlbflush_64.h b/include/asm-x86/tlbflush_64.h index 888eb4abdd07..7731fd23d572 100644 --- a/include/asm-x86/tlbflush_64.h +++ b/include/asm-x86/tlbflush_64.h | |||
@@ -31,7 +31,6 @@ static inline void __flush_tlb_all(void) | |||
31 | * - flush_tlb_page(vma, vmaddr) flushes one page | 31 | * - flush_tlb_page(vma, vmaddr) flushes one page |
32 | * - flush_tlb_range(vma, start, end) flushes a range of pages | 32 | * - flush_tlb_range(vma, start, end) flushes a range of pages |
33 | * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages | 33 | * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages |
34 | * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables | ||
35 | * | 34 | * |
36 | * x86-64 can only flush individual pages or full VMs. For a range flush | 35 | * x86-64 can only flush individual pages or full VMs. For a range flush |
37 | * we always do the full VM. Might be worth trying if for a small | 36 | * we always do the full VM. Might be worth trying if for a small |
@@ -98,12 +97,4 @@ static inline void flush_tlb_kernel_range(unsigned long start, | |||
98 | flush_tlb_all(); | 97 | flush_tlb_all(); |
99 | } | 98 | } |
100 | 99 | ||
101 | static inline void flush_tlb_pgtables(struct mm_struct *mm, | ||
102 | unsigned long start, unsigned long end) | ||
103 | { | ||
104 | /* x86_64 does not keep any page table caches in a software TLB. | ||
105 | The CPUs do in their hardware TLBs, but they are handled | ||
106 | by the normal TLB flushing algorithms. */ | ||
107 | } | ||
108 | |||
109 | #endif /* _X8664_TLBFLUSH_H */ | 100 | #endif /* _X8664_TLBFLUSH_H */ |