5 files changed, 31 insertions, 20 deletions

diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 2f5a792b0acc..9489283a4bcf 100644
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -72,14 +72,15 @@
 #define X86_FEATURE_UP          (3*32+ 9) /* smp kernel running on up */
 #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */
 #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
-#define X86_FEATURE_PEBS        (3*32+12)  /* Precise-Event Based Sampling */
-#define X86_FEATURE_BTS         (3*32+13)  /* Branch Trace Store */
-#define X86_FEATURE_SYSCALL32   (3*32+14)  /* syscall in ia32 userspace */
-#define X86_FEATURE_SYSENTER32  (3*32+15)  /* sysenter in ia32 userspace */
+#define X86_FEATURE_PEBS        (3*32+12) /* Precise-Event Based Sampling */
+#define X86_FEATURE_BTS         (3*32+13) /* Branch Trace Store */
+#define X86_FEATURE_SYSCALL32   (3*32+14) /* syscall in ia32 userspace */
+#define X86_FEATURE_SYSENTER32  (3*32+15) /* sysenter in ia32 userspace */
 #define X86_FEATURE_REP_GOOD    (3*32+16) /* rep microcode works well on this CPU */
 #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
 #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */
-#define X86_FEATURE_11AP        (3*32+19)  /* Bad local APIC aka 11AP */
+#define X86_FEATURE_11AP        (3*32+19) /* Bad local APIC aka 11AP */
+#define X86_FEATURE_NOPL        (3*32+20) /* The NOPL (0F 1F) instructions */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3        (4*32+ 0) /* Streaming SIMD Extensions-3 */
@@ -91,6 +92,7 @@
 #define X86_FEATURE_CX16        (4*32+13) /* CMPXCHG16B */
 #define X86_FEATURE_XTPR        (4*32+14) /* Send Task Priority Messages */
 #define X86_FEATURE_DCA         (4*32+18) /* Direct Cache Access */
+#define X86_FEATURE_XMM4_2      (4*32+20) /* Streaming SIMD Extensions-4.2 */
 
 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
 #define X86_FEATURE_XSTORE      (5*32+ 2) /* on-CPU RNG present (xstore insn) */
@@ -189,6 +191,7 @@ extern const char * const x86_power_flags[32];
 #define cpu_has_gbpages         boot_cpu_has(X86_FEATURE_GBPAGES)
 #define cpu_has_arch_perfmon    boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
 #define cpu_has_pat             boot_cpu_has(X86_FEATURE_PAT)
+#define cpu_has_xmm4_2          boot_cpu_has(X86_FEATURE_XMM4_2)
 
 #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
 # define cpu_has_invlpg         1
diff --git a/include/asm-x86/kvm_host.h b/include/asm-x86/kvm_host.h
index 0f3c53114614..c2e34c275900 100644
--- a/include/asm-x86/kvm_host.h
+++ b/include/asm-x86/kvm_host.h
@@ -722,7 +722,7 @@ asmlinkage void kvm_handle_fault_on_reboot(void);
 
 #define __kvm_handle_fault_on_reboot(insn) \
         "666: " insn "\n\t" \
-        ".pushsection .text.fixup, \"ax\" \n" \
+        ".pushsection .fixup, \"ax\" \n" \
         "667: \n\t" \
         KVM_EX_PUSH " $666b \n\t" \
         "jmp kvm_handle_fault_on_reboot \n\t" \
diff --git a/include/asm-x86/mce.h b/include/asm-x86/mce.h
index 94f1fd79e22a..531eaa587455 100644
--- a/include/asm-x86/mce.h
+++ b/include/asm-x86/mce.h
@@ -92,6 +92,7 @@ extern int mce_disabled;
 
 void mce_log(struct mce *m);
 DECLARE_PER_CPU(struct sys_device, device_mce);
+extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
 
 #ifdef CONFIG_X86_MCE_INTEL
 void mce_intel_feature_init(struct cpuinfo_x86 *c);
diff --git a/include/asm-x86/msr.h b/include/asm-x86/msr.h
index ca110ee73f07..2362cfda1fbc 100644
--- a/include/asm-x86/msr.h
+++ b/include/asm-x86/msr.h
@@ -52,14 +52,14 @@ static inline unsigned long long native_read_msr_safe(unsigned int msr,
 {
         DECLARE_ARGS(val, low, high);
 
-        asm volatile("2: rdmsr ; xor %0,%0\n"
+        asm volatile("2: rdmsr ; xor %[err],%[err]\n"
                      "1:\n\t"
                      ".section .fixup,\"ax\"\n\t"
-                     "3:  mov %3,%0 ; jmp 1b\n\t"
+                     "3:  mov %[fault],%[err] ; jmp 1b\n\t"
                      ".previous\n\t"
                      _ASM_EXTABLE(2b, 3b)
-                     : "=r" (*err), EAX_EDX_RET(val, low, high)
-                     : "c" (msr), "i" (-EFAULT));
+                     : [err] "=r" (*err), EAX_EDX_RET(val, low, high)
+                     : "c" (msr), [fault] "i" (-EFAULT));
         return EAX_EDX_VAL(val, low, high);
 }
 
@@ -73,15 +73,15 @@ static inline int native_write_msr_safe(unsigned int msr,
                                         unsigned low, unsigned high)
 {
         int err;
-        asm volatile("2: wrmsr ; xor %0,%0\n"
+        asm volatile("2: wrmsr ; xor %[err],%[err]\n"
                      "1:\n\t"
                      ".section .fixup,\"ax\"\n\t"
-                     "3:  mov %4,%0 ; jmp 1b\n\t"
+                     "3:  mov %[fault],%[err] ; jmp 1b\n\t"
                      ".previous\n\t"
                      _ASM_EXTABLE(2b, 3b)
-                     : "=a" (err)
+                     : [err] "=a" (err)
                      : "c" (msr), "0" (low), "d" (high),
-                       "i" (-EFAULT)
+                       [fault] "i" (-EFAULT)
                      : "memory");
         return err;
 }
@@ -192,19 +192,20 @@ do {                                                            \
 #define write_rdtscp_aux(val) wrmsr(0xc0000103, (val), 0)
 
 #ifdef CONFIG_SMP
-void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
-void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
+int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
+int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
-
 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
 #else  /*  CONFIG_SMP  */
-static inline void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
+static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
 {
         rdmsr(msr_no, *l, *h);
+        return 0;
 }
-static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
+static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
 {
         wrmsr(msr_no, l, h);
+        return 0;
 }
 static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no,
                                     u32 *l, u32 *h)
diff --git a/include/asm-x86/required-features.h b/include/asm-x86/required-features.h
index adec887dd7cd..5c2ff4bc2980 100644
--- a/include/asm-x86/required-features.h
+++ b/include/asm-x86/required-features.h
@@ -41,6 +41,12 @@
 # define NEED_3DNOW     0
 #endif
 
+#if defined(CONFIG_X86_P6_NOP) || defined(CONFIG_X86_64)
+# define NEED_NOPL      (1<<(X86_FEATURE_NOPL & 31))
+#else
+# define NEED_NOPL      0
+#endif
+
 #ifdef CONFIG_X86_64
 #define NEED_PSE        0
 #define NEED_MSR        (1<<(X86_FEATURE_MSR & 31))
@@ -67,7 +73,7 @@
 #define REQUIRED_MASK1  (NEED_LM|NEED_3DNOW)
 
 #define REQUIRED_MASK2  0
-#define REQUIRED_MASK3  0
+#define REQUIRED_MASK3  (NEED_NOPL)
 #define REQUIRED_MASK4  0
 #define REQUIRED_MASK5  0
 #define REQUIRED_MASK6  0