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-rw-r--r--include/asm-x86/bigsmp/apic.h15
-rw-r--r--include/asm-x86/es7000/apic.h3
-rw-r--r--include/asm-x86/genapic_32.h2
-rw-r--r--include/asm-x86/hw_irq.h6
-rw-r--r--include/asm-x86/irq_vectors.h15
-rw-r--r--include/asm-x86/mach-default/entry_arch.h1
-rw-r--r--include/asm-x86/mach-default/mach_apic.h15
-rw-r--r--include/asm-x86/mach-generic/mach_apic.h1
-rw-r--r--include/asm-x86/numaq/apic.h2
-rw-r--r--include/asm-x86/summit/apic.h1
10 files changed, 30 insertions, 31 deletions
diff --git a/include/asm-x86/bigsmp/apic.h b/include/asm-x86/bigsmp/apic.h
index 0a9cd7c5ca0c..1d9543b9d358 100644
--- a/include/asm-x86/bigsmp/apic.h
+++ b/include/asm-x86/bigsmp/apic.h
@@ -9,22 +9,17 @@ static inline int apic_id_registered(void)
9 return (1); 9 return (1);
10} 10}
11 11
12/* Round robin the irqs amoung the online cpus */
13static inline cpumask_t target_cpus(void) 12static inline cpumask_t target_cpus(void)
14{ 13{
15 static unsigned long cpu = NR_CPUS; 14#ifdef CONFIG_SMP
16 do { 15 return cpu_online_map;
17 if (cpu >= NR_CPUS) 16#else
18 cpu = first_cpu(cpu_online_map); 17 return cpumask_of_cpu(0);
19 else 18#endif
20 cpu = next_cpu(cpu, cpu_online_map);
21 } while (cpu >= NR_CPUS);
22 return cpumask_of_cpu(cpu);
23} 19}
24 20
25#undef APIC_DEST_LOGICAL 21#undef APIC_DEST_LOGICAL
26#define APIC_DEST_LOGICAL 0 22#define APIC_DEST_LOGICAL 0
27#define TARGET_CPUS (target_cpus())
28#define APIC_DFR_VALUE (APIC_DFR_FLAT) 23#define APIC_DFR_VALUE (APIC_DFR_FLAT)
29#define INT_DELIVERY_MODE (dest_Fixed) 24#define INT_DELIVERY_MODE (dest_Fixed)
30#define INT_DEST_MODE (0) /* phys delivery to target proc */ 25#define INT_DEST_MODE (0) /* phys delivery to target proc */
diff --git a/include/asm-x86/es7000/apic.h b/include/asm-x86/es7000/apic.h
index bd2c44d1f7ac..750afada5fbf 100644
--- a/include/asm-x86/es7000/apic.h
+++ b/include/asm-x86/es7000/apic.h
@@ -17,7 +17,6 @@ static inline cpumask_t target_cpus(void)
17 return cpumask_of_cpu(smp_processor_id()); 17 return cpumask_of_cpu(smp_processor_id());
18#endif 18#endif
19} 19}
20#define TARGET_CPUS (target_cpus())
21 20
22#if defined CONFIG_ES7000_CLUSTERED_APIC 21#if defined CONFIG_ES7000_CLUSTERED_APIC
23#define APIC_DFR_VALUE (APIC_DFR_CLUSTER) 22#define APIC_DFR_VALUE (APIC_DFR_CLUSTER)
@@ -81,7 +80,7 @@ static inline void setup_apic_routing(void)
81 int apic = per_cpu(x86_bios_cpu_apicid, smp_processor_id()); 80 int apic = per_cpu(x86_bios_cpu_apicid, smp_processor_id());
82 printk("Enabling APIC mode: %s. Using %d I/O APICs, target cpus %lx\n", 81 printk("Enabling APIC mode: %s. Using %d I/O APICs, target cpus %lx\n",
83 (apic_version[apic] == 0x14) ? 82 (apic_version[apic] == 0x14) ?
84 "Physical Cluster" : "Logical Cluster", nr_ioapics, cpus_addr(TARGET_CPUS)[0]); 83 "Physical Cluster" : "Logical Cluster", nr_ioapics, cpus_addr(target_cpus())[0]);
85} 84}
86 85
87static inline int multi_timer_check(int apic, int irq) 86static inline int multi_timer_check(int apic, int irq)
diff --git a/include/asm-x86/genapic_32.h b/include/asm-x86/genapic_32.h
index 34280f027664..6fe4f81bfcf9 100644
--- a/include/asm-x86/genapic_32.h
+++ b/include/asm-x86/genapic_32.h
@@ -57,6 +57,7 @@ struct genapic {
57 unsigned (*get_apic_id)(unsigned long x); 57 unsigned (*get_apic_id)(unsigned long x);
58 unsigned long apic_id_mask; 58 unsigned long apic_id_mask;
59 unsigned int (*cpu_mask_to_apicid)(cpumask_t cpumask); 59 unsigned int (*cpu_mask_to_apicid)(cpumask_t cpumask);
60 cpumask_t (*vector_allocation_domain)(int cpu);
60 61
61#ifdef CONFIG_SMP 62#ifdef CONFIG_SMP
62 /* ipi */ 63 /* ipi */
@@ -104,6 +105,7 @@ struct genapic {
104 APICFUNC(get_apic_id) \ 105 APICFUNC(get_apic_id) \
105 .apic_id_mask = APIC_ID_MASK, \ 106 .apic_id_mask = APIC_ID_MASK, \
106 APICFUNC(cpu_mask_to_apicid) \ 107 APICFUNC(cpu_mask_to_apicid) \
108 APICFUNC(vector_allocation_domain) \
107 APICFUNC(acpi_madt_oem_check) \ 109 APICFUNC(acpi_madt_oem_check) \
108 IPIFUNC(send_IPI_mask) \ 110 IPIFUNC(send_IPI_mask) \
109 IPIFUNC(send_IPI_allbutself) \ 111 IPIFUNC(send_IPI_allbutself) \
diff --git a/include/asm-x86/hw_irq.h b/include/asm-x86/hw_irq.h
index 50f6e0316b50..51c787d17cbc 100644
--- a/include/asm-x86/hw_irq.h
+++ b/include/asm-x86/hw_irq.h
@@ -116,12 +116,12 @@ extern asmlinkage void smp_invalidate_interrupt(struct pt_regs *);
116 116
117#ifdef CONFIG_X86_32 117#ifdef CONFIG_X86_32
118extern void (*const interrupt[NR_IRQS])(void); 118extern void (*const interrupt[NR_IRQS])(void);
119#else 119#endif
120
120typedef int vector_irq_t[NR_VECTORS]; 121typedef int vector_irq_t[NR_VECTORS];
121DECLARE_PER_CPU(vector_irq_t, vector_irq); 122DECLARE_PER_CPU(vector_irq_t, vector_irq);
122#endif
123 123
124#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_X86_64) 124#ifdef CONFIG_X86_IO_APIC
125extern void lock_vector_lock(void); 125extern void lock_vector_lock(void);
126extern void unlock_vector_lock(void); 126extern void unlock_vector_lock(void);
127extern void __setup_vector_irq(int cpu); 127extern void __setup_vector_irq(int cpu);
diff --git a/include/asm-x86/irq_vectors.h b/include/asm-x86/irq_vectors.h
index cb09802ce651..a8d065d85f57 100644
--- a/include/asm-x86/irq_vectors.h
+++ b/include/asm-x86/irq_vectors.h
@@ -19,19 +19,14 @@
19 19
20/* 20/*
21 * Reserve the lowest usable priority level 0x20 - 0x2f for triggering 21 * Reserve the lowest usable priority level 0x20 - 0x2f for triggering
22 * cleanup after irq migration on 64 bit. 22 * cleanup after irq migration.
23 */ 23 */
24#define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR 24#define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR
25 25
26/* 26/*
27 * Vectors 0x20-0x2f are used for ISA interrupts on 32 bit. 27 * Vectors 0x30-0x3f are used for ISA interrupts.
28 * Vectors 0x30-0x3f are used for ISA interrupts on 64 bit.
29 */ 28 */
30#ifdef CONFIG_X86_32
31#define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR)
32#else
33#define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR + 0x10) 29#define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR + 0x10)
34#endif
35#define IRQ1_VECTOR (IRQ0_VECTOR + 1) 30#define IRQ1_VECTOR (IRQ0_VECTOR + 1)
36#define IRQ2_VECTOR (IRQ0_VECTOR + 2) 31#define IRQ2_VECTOR (IRQ0_VECTOR + 2)
37#define IRQ3_VECTOR (IRQ0_VECTOR + 3) 32#define IRQ3_VECTOR (IRQ0_VECTOR + 3)
@@ -96,11 +91,7 @@
96 * start at 0x31(0x41) to spread out vectors evenly between priority 91 * start at 0x31(0x41) to spread out vectors evenly between priority
97 * levels. (0x80 is the syscall vector) 92 * levels. (0x80 is the syscall vector)
98 */ 93 */
99#ifdef CONFIG_X86_32 94#define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2)
100# define FIRST_DEVICE_VECTOR 0x31
101#else
102# define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2)
103#endif
104 95
105#define NR_VECTORS 256 96#define NR_VECTORS 256
106 97
diff --git a/include/asm-x86/mach-default/entry_arch.h b/include/asm-x86/mach-default/entry_arch.h
index 9283b60a1dd2..6b1add8e31dd 100644
--- a/include/asm-x86/mach-default/entry_arch.h
+++ b/include/asm-x86/mach-default/entry_arch.h
@@ -14,6 +14,7 @@ BUILD_INTERRUPT(reschedule_interrupt,RESCHEDULE_VECTOR)
14BUILD_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR) 14BUILD_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR)
15BUILD_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR) 15BUILD_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
16BUILD_INTERRUPT(call_function_single_interrupt,CALL_FUNCTION_SINGLE_VECTOR) 16BUILD_INTERRUPT(call_function_single_interrupt,CALL_FUNCTION_SINGLE_VECTOR)
17BUILD_INTERRUPT(irq_move_cleanup_interrupt,IRQ_MOVE_CLEANUP_VECTOR)
17#endif 18#endif
18 19
19/* 20/*
diff --git a/include/asm-x86/mach-default/mach_apic.h b/include/asm-x86/mach-default/mach_apic.h
index 2a330a41b3dd..3c66f2cdaec1 100644
--- a/include/asm-x86/mach-default/mach_apic.h
+++ b/include/asm-x86/mach-default/mach_apic.h
@@ -85,6 +85,20 @@ static inline int apicid_to_node(int logical_apicid)
85 return 0; 85 return 0;
86#endif 86#endif
87} 87}
88
89static inline cpumask_t vector_allocation_domain(int cpu)
90{
91 /* Careful. Some cpus do not strictly honor the set of cpus
92 * specified in the interrupt destination when using lowest
93 * priority interrupt delivery mode.
94 *
95 * In particular there was a hyperthreading cpu observed to
96 * deliver interrupts to the wrong hyperthread when only one
97 * hyperthread was specified in the interrupt desitination.
98 */
99 cpumask_t domain = { { [0] = APIC_ALL_CPUS, } };
100 return domain;
101}
88#endif 102#endif
89 103
90static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) 104static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
@@ -138,6 +152,5 @@ static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
138static inline void enable_apic_mode(void) 152static inline void enable_apic_mode(void)
139{ 153{
140} 154}
141
142#endif /* CONFIG_X86_LOCAL_APIC */ 155#endif /* CONFIG_X86_LOCAL_APIC */
143#endif /* ASM_X86__MACH_DEFAULT__MACH_APIC_H */ 156#endif /* ASM_X86__MACH_DEFAULT__MACH_APIC_H */
diff --git a/include/asm-x86/mach-generic/mach_apic.h b/include/asm-x86/mach-generic/mach_apic.h
index 5d010c6881dd..5085b52da301 100644
--- a/include/asm-x86/mach-generic/mach_apic.h
+++ b/include/asm-x86/mach-generic/mach_apic.h
@@ -24,6 +24,7 @@
24#define check_phys_apicid_present (genapic->check_phys_apicid_present) 24#define check_phys_apicid_present (genapic->check_phys_apicid_present)
25#define check_apicid_used (genapic->check_apicid_used) 25#define check_apicid_used (genapic->check_apicid_used)
26#define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid) 26#define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid)
27#define vector_allocation_domain (genapic->vector_allocation_domain)
27#define enable_apic_mode (genapic->enable_apic_mode) 28#define enable_apic_mode (genapic->enable_apic_mode)
28#define phys_pkg_id (genapic->phys_pkg_id) 29#define phys_pkg_id (genapic->phys_pkg_id)
29 30
diff --git a/include/asm-x86/numaq/apic.h b/include/asm-x86/numaq/apic.h
index a8344ba6ea15..0bf2a06b7a4e 100644
--- a/include/asm-x86/numaq/apic.h
+++ b/include/asm-x86/numaq/apic.h
@@ -12,8 +12,6 @@ static inline cpumask_t target_cpus(void)
12 return CPU_MASK_ALL; 12 return CPU_MASK_ALL;
13} 13}
14 14
15#define TARGET_CPUS (target_cpus())
16
17#define NO_BALANCE_IRQ (1) 15#define NO_BALANCE_IRQ (1)
18#define esr_disable (1) 16#define esr_disable (1)
19 17
diff --git a/include/asm-x86/summit/apic.h b/include/asm-x86/summit/apic.h
index c5b2e4b10358..0f68037b8f24 100644
--- a/include/asm-x86/summit/apic.h
+++ b/include/asm-x86/summit/apic.h
@@ -22,7 +22,6 @@ static inline cpumask_t target_cpus(void)
22 */ 22 */
23 return cpumask_of_cpu(0); 23 return cpumask_of_cpu(0);
24} 24}
25#define TARGET_CPUS (target_cpus())
26 25
27#define INT_DELIVERY_MODE (dest_LowestPrio) 26#define INT_DELIVERY_MODE (dest_LowestPrio)
28#define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */ 27#define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */