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-rw-r--r--include/asm-x86/spinlock_64.h186
1 files changed, 0 insertions, 186 deletions
diff --git a/include/asm-x86/spinlock_64.h b/include/asm-x86/spinlock_64.h
deleted file mode 100644
index f5ba90b7335c..000000000000
--- a/include/asm-x86/spinlock_64.h
+++ /dev/null
@@ -1,186 +0,0 @@
1#ifndef __ASM_SPINLOCK_H
2#define __ASM_SPINLOCK_H
3
4#include <asm/atomic.h>
5#include <asm/rwlock.h>
6#include <asm/page.h>
7#include <asm/processor.h>
8
9/*
10 * Your basic SMP spinlocks, allowing only a single CPU anywhere
11 *
12 * Simple spin lock operations. There are two variants, one clears IRQ's
13 * on the local processor, one does not.
14 *
15 * We make no fairness assumptions. They have a cost.
16 *
17 * (the type definitions are in asm/spinlock_types.h)
18 */
19
20typedef int _slock_t;
21#define LOCK_INS_DEC "decl"
22#define LOCK_INS_XCH "xchgl"
23#define LOCK_INS_MOV "movl"
24#define LOCK_INS_CMP "cmpl"
25#define LOCK_PTR_REG "D"
26
27static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
28{
29 return *(volatile _slock_t *)(&(lock)->slock) <= 0;
30}
31
32static inline void __raw_spin_lock(raw_spinlock_t *lock)
33{
34 asm volatile(
35 "\n1:\t"
36 LOCK_PREFIX " ; " LOCK_INS_DEC " %0\n\t"
37 "jns 3f\n"
38 "2:\t"
39 "rep;nop\n\t"
40 LOCK_INS_CMP " $0,%0\n\t"
41 "jle 2b\n\t"
42 "jmp 1b\n"
43 "3:\n\t"
44 : "+m" (lock->slock) : : "memory");
45}
46
47/*
48 * It is easier for the lock validator if interrupts are not re-enabled
49 * in the middle of a lock-acquire. This is a performance feature anyway
50 * so we turn it off:
51 *
52 * NOTE: there's an irqs-on section here, which normally would have to be
53 * irq-traced, but on CONFIG_TRACE_IRQFLAGS we never use this variant.
54 */
55#ifndef CONFIG_PROVE_LOCKING
56static inline void __raw_spin_lock_flags(raw_spinlock_t *lock,
57 unsigned long flags)
58{
59 asm volatile(
60 "\n1:\t"
61 LOCK_PREFIX " ; " LOCK_INS_DEC " %[slock]\n\t"
62 "jns 5f\n"
63 "testl $0x200, %[flags]\n\t"
64 "jz 4f\n\t"
65 STI_STRING "\n"
66 "3:\t"
67 "rep;nop\n\t"
68 LOCK_INS_CMP " $0, %[slock]\n\t"
69 "jle 3b\n\t"
70 CLI_STRING "\n\t"
71 "jmp 1b\n"
72 "4:\t"
73 "rep;nop\n\t"
74 LOCK_INS_CMP " $0, %[slock]\n\t"
75 "jg 1b\n\t"
76 "jmp 4b\n"
77 "5:\n\t"
78 : [slock] "+m" (lock->slock)
79 : [flags] "r" ((u32)flags)
80 CLI_STI_INPUT_ARGS
81 : "memory" CLI_STI_CLOBBERS);
82}
83#endif
84
85static inline int __raw_spin_trylock(raw_spinlock_t *lock)
86{
87 _slock_t oldval;
88
89 asm volatile(
90 LOCK_INS_XCH " %0,%1"
91 :"=q" (oldval), "+m" (lock->slock)
92 :"0" (0) : "memory");
93
94 return oldval > 0;
95}
96
97static inline void __raw_spin_unlock(raw_spinlock_t *lock)
98{
99 asm volatile(LOCK_INS_MOV " $1,%0" : "=m" (lock->slock) :: "memory");
100}
101
102static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
103{
104 while (__raw_spin_is_locked(lock))
105 cpu_relax();
106}
107
108/*
109 * Read-write spinlocks, allowing multiple readers
110 * but only one writer.
111 *
112 * NOTE! it is quite common to have readers in interrupts
113 * but no interrupt writers. For those circumstances we
114 * can "mix" irq-safe locks - any writer needs to get a
115 * irq-safe write-lock, but readers can get non-irqsafe
116 * read-locks.
117 *
118 * On x86, we implement read-write locks as a 32-bit counter
119 * with the high bit (sign) being the "contended" bit.
120 */
121
122static inline int __raw_read_can_lock(raw_rwlock_t *lock)
123{
124 return (int)(lock)->lock > 0;
125}
126
127static inline int __raw_write_can_lock(raw_rwlock_t *lock)
128{
129 return (lock)->lock == RW_LOCK_BIAS;
130}
131
132static inline void __raw_read_lock(raw_rwlock_t *rw)
133{
134 asm volatile(LOCK_PREFIX " subl $1,(%0)\n\t"
135 "jns 1f\n"
136 "call __read_lock_failed\n\t"
137 "1:\n"
138 ::LOCK_PTR_REG (rw) : "memory");
139}
140
141static inline void __raw_write_lock(raw_rwlock_t *rw)
142{
143 asm volatile(LOCK_PREFIX " subl %1,(%0)\n\t"
144 "jz 1f\n"
145 "call __write_lock_failed\n\t"
146 "1:\n"
147 ::LOCK_PTR_REG (rw), "i" (RW_LOCK_BIAS) : "memory");
148}
149
150static inline int __raw_read_trylock(raw_rwlock_t *lock)
151{
152 atomic_t *count = (atomic_t *)lock;
153
154 atomic_dec(count);
155 if (atomic_read(count) >= 0)
156 return 1;
157 atomic_inc(count);
158 return 0;
159}
160
161static inline int __raw_write_trylock(raw_rwlock_t *lock)
162{
163 atomic_t *count = (atomic_t *)lock;
164
165 if (atomic_sub_and_test(RW_LOCK_BIAS, count))
166 return 1;
167 atomic_add(RW_LOCK_BIAS, count);
168 return 0;
169}
170
171static inline void __raw_read_unlock(raw_rwlock_t *rw)
172{
173 asm volatile(LOCK_PREFIX "incl %0" :"+m" (rw->lock) : : "memory");
174}
175
176static inline void __raw_write_unlock(raw_rwlock_t *rw)
177{
178 asm volatile(LOCK_PREFIX "addl %1, %0"
179 : "+m" (rw->lock) : "i" (RW_LOCK_BIAS) : "memory");
180}
181
182#define _raw_spin_relax(lock) cpu_relax()
183#define _raw_read_relax(lock) cpu_relax()
184#define _raw_write_relax(lock) cpu_relax()
185
186#endif /* __ASM_SPINLOCK_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-11 13:17:38 -0500