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-rw-r--r--include/asm-x86/processor.h9
1 files changed, 2 insertions, 7 deletions
diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h
index 559105220a47..7f7382704592 100644
--- a/include/asm-x86/processor.h
+++ b/include/asm-x86/processor.h
@@ -153,7 +153,7 @@ static inline int hlt_works(int cpu)
153 153
154extern void cpu_detect(struct cpuinfo_x86 *c); 154extern void cpu_detect(struct cpuinfo_x86 *c);
155 155
156extern void identify_cpu(struct cpuinfo_x86 *); 156extern void early_cpu_init(void);
157extern void identify_boot_cpu(void); 157extern void identify_boot_cpu(void);
158extern void identify_secondary_cpu(struct cpuinfo_x86 *); 158extern void identify_secondary_cpu(struct cpuinfo_x86 *);
159extern void print_cpu_info(struct cpuinfo_x86 *); 159extern void print_cpu_info(struct cpuinfo_x86 *);
@@ -263,15 +263,11 @@ struct tss_struct {
263 struct thread_struct *io_bitmap_owner; 263 struct thread_struct *io_bitmap_owner;
264 264
265 /* 265 /*
266 * Pad the TSS to be cacheline-aligned (size is 0x100):
267 */
268 unsigned long __cacheline_filler[35];
269 /*
270 * .. and then another 0x100 bytes for the emergency kernel stack: 266 * .. and then another 0x100 bytes for the emergency kernel stack:
271 */ 267 */
272 unsigned long stack[64]; 268 unsigned long stack[64];
273 269
274} __attribute__((packed)); 270} ____cacheline_aligned;
275 271
276DECLARE_PER_CPU(struct tss_struct, init_tss); 272DECLARE_PER_CPU(struct tss_struct, init_tss);
277 273
@@ -535,7 +531,6 @@ static inline void load_sp0(struct tss_struct *tss,
535} 531}
536 532
537#define set_iopl_mask native_set_iopl_mask 533#define set_iopl_mask native_set_iopl_mask
538#define SWAPGS swapgs
539#endif /* CONFIG_PARAVIRT */ 534#endif /* CONFIG_PARAVIRT */
540 535
541/* 536/*