diff options
Diffstat (limited to 'include/asm-x86/pgtable-3level.h')
-rw-r--r-- | include/asm-x86/pgtable-3level.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/include/asm-x86/pgtable-3level.h b/include/asm-x86/pgtable-3level.h index ad71960bca3a..1d763eec740f 100644 --- a/include/asm-x86/pgtable-3level.h +++ b/include/asm-x86/pgtable-3level.h | |||
@@ -98,8 +98,10 @@ static inline void pud_clear(pud_t *pudp) | |||
98 | set_pud(pudp, __pud(0)); | 98 | set_pud(pudp, __pud(0)); |
99 | 99 | ||
100 | /* | 100 | /* |
101 | * Pentium-II erratum A13: in PAE mode we explicitly have to flush | 101 | * According to Intel App note "TLBs, Paging-Structure Caches, |
102 | * the TLB via cr3 if the top-level pgd is changed... | 102 | * and Their Invalidation", April 2007, document 317080-001, |
103 | * section 8.1: in PAE mode we explicitly have to flush the | ||
104 | * TLB via cr3 if the top-level pgd is changed... | ||
103 | * | 105 | * |
104 | * Make sure the pud entry we're updating is within the | 106 | * Make sure the pud entry we're updating is within the |
105 | * current pgd to avoid unnecessary TLB flushes. | 107 | * current pgd to avoid unnecessary TLB flushes. |