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-rw-r--r--include/asm-x86/pgalloc_32.h6
1 files changed, 4 insertions, 2 deletions
diff --git a/include/asm-x86/pgalloc_32.h b/include/asm-x86/pgalloc_32.h
index 7641e7b5d931..6c21ef951dab 100644
--- a/include/asm-x86/pgalloc_32.h
+++ b/include/asm-x86/pgalloc_32.h
@@ -80,8 +80,10 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd)
80 set_pud(pudp, __pud(__pa(pmd) | _PAGE_PRESENT)); 80 set_pud(pudp, __pud(__pa(pmd) | _PAGE_PRESENT));
81 81
82 /* 82 /*
83 * Pentium-II erratum A13: in PAE mode we explicitly have to flush 83 * According to Intel App note "TLBs, Paging-Structure Caches,
84 * the TLB via cr3 if the top-level pgd is changed... 84 * and Their Invalidation", April 2007, document 317080-001,
85 * section 8.1: in PAE mode we explicitly have to flush the
86 * TLB via cr3 if the top-level pgd is changed...
85 */ 87 */
86 if (mm == current->active_mm) 88 if (mm == current->active_mm)
87 write_cr3(read_cr3()); 89 write_cr3(read_cr3());