diff options
Diffstat (limited to 'include/asm-x86/mach-visws')
-rw-r--r-- | include/asm-x86/mach-visws/cobalt.h | 125 | ||||
-rw-r--r-- | include/asm-x86/mach-visws/entry_arch.h | 23 | ||||
-rw-r--r-- | include/asm-x86/mach-visws/irq_vectors.h | 62 | ||||
-rw-r--r-- | include/asm-x86/mach-visws/lithium.h | 53 | ||||
-rw-r--r-- | include/asm-x86/mach-visws/mach_apic.h | 103 | ||||
-rw-r--r-- | include/asm-x86/mach-visws/mach_apicdef.h | 12 | ||||
-rw-r--r-- | include/asm-x86/mach-visws/piix4.h | 107 | ||||
-rw-r--r-- | include/asm-x86/mach-visws/setup_arch.h | 8 | ||||
-rw-r--r-- | include/asm-x86/mach-visws/smpboot_hooks.h | 24 |
9 files changed, 517 insertions, 0 deletions
diff --git a/include/asm-x86/mach-visws/cobalt.h b/include/asm-x86/mach-visws/cobalt.h new file mode 100644 index 000000000000..33c36225a042 --- /dev/null +++ b/include/asm-x86/mach-visws/cobalt.h | |||
@@ -0,0 +1,125 @@ | |||
1 | #ifndef __I386_SGI_COBALT_H | ||
2 | #define __I386_SGI_COBALT_H | ||
3 | |||
4 | #include <asm/fixmap.h> | ||
5 | |||
6 | /* | ||
7 | * Cobalt SGI Visual Workstation system ASIC | ||
8 | */ | ||
9 | |||
10 | #define CO_CPU_NUM_PHYS 0x1e00 | ||
11 | #define CO_CPU_TAB_PHYS (CO_CPU_NUM_PHYS + 2) | ||
12 | |||
13 | #define CO_CPU_MAX 4 | ||
14 | |||
15 | #define CO_CPU_PHYS 0xc2000000 | ||
16 | #define CO_APIC_PHYS 0xc4000000 | ||
17 | |||
18 | /* see set_fixmap() and asm/fixmap.h */ | ||
19 | #define CO_CPU_VADDR (fix_to_virt(FIX_CO_CPU)) | ||
20 | #define CO_APIC_VADDR (fix_to_virt(FIX_CO_APIC)) | ||
21 | |||
22 | /* Cobalt CPU registers -- relative to CO_CPU_VADDR, use co_cpu_*() */ | ||
23 | #define CO_CPU_REV 0x08 | ||
24 | #define CO_CPU_CTRL 0x10 | ||
25 | #define CO_CPU_STAT 0x20 | ||
26 | #define CO_CPU_TIMEVAL 0x30 | ||
27 | |||
28 | /* CO_CPU_CTRL bits */ | ||
29 | #define CO_CTRL_TIMERUN 0x04 /* 0 == disabled */ | ||
30 | #define CO_CTRL_TIMEMASK 0x08 /* 0 == unmasked */ | ||
31 | |||
32 | /* CO_CPU_STATUS bits */ | ||
33 | #define CO_STAT_TIMEINTR 0x02 /* (r) 1 == int pend, (w) 0 == clear */ | ||
34 | |||
35 | /* CO_CPU_TIMEVAL value */ | ||
36 | #define CO_TIME_HZ 100000000 /* Cobalt core rate */ | ||
37 | |||
38 | /* Cobalt APIC registers -- relative to CO_APIC_VADDR, use co_apic_*() */ | ||
39 | #define CO_APIC_HI(n) (((n) * 0x10) + 4) | ||
40 | #define CO_APIC_LO(n) ((n) * 0x10) | ||
41 | #define CO_APIC_ID 0x0ffc | ||
42 | |||
43 | /* CO_APIC_ID bits */ | ||
44 | #define CO_APIC_ENABLE 0x00000100 | ||
45 | |||
46 | /* CO_APIC_LO bits */ | ||
47 | #define CO_APIC_MASK 0x00010000 /* 0 = enabled */ | ||
48 | #define CO_APIC_LEVEL 0x00008000 /* 0 = edge */ | ||
49 | |||
50 | /* | ||
51 | * Where things are physically wired to Cobalt | ||
52 | * #defines with no board _<type>_<rev>_ are common to all (thus far) | ||
53 | */ | ||
54 | #define CO_APIC_IDE0 4 | ||
55 | #define CO_APIC_IDE1 2 /* Only on 320 */ | ||
56 | |||
57 | #define CO_APIC_8259 12 /* serial, floppy, par-l-l */ | ||
58 | |||
59 | /* Lithium PCI Bridge A -- "the one with 82557 Ethernet" */ | ||
60 | #define CO_APIC_PCIA_BASE0 0 /* and 1 */ /* slot 0, line 0 */ | ||
61 | #define CO_APIC_PCIA_BASE123 5 /* and 6 */ /* slot 0, line 1 */ | ||
62 | |||
63 | #define CO_APIC_PIIX4_USB 7 /* this one is weird */ | ||
64 | |||
65 | /* Lithium PCI Bridge B -- "the one with PIIX4" */ | ||
66 | #define CO_APIC_PCIB_BASE0 8 /* and 9-12 *//* slot 0, line 0 */ | ||
67 | #define CO_APIC_PCIB_BASE123 13 /* 14.15 */ /* slot 0, line 1 */ | ||
68 | |||
69 | #define CO_APIC_VIDOUT0 16 | ||
70 | #define CO_APIC_VIDOUT1 17 | ||
71 | #define CO_APIC_VIDIN0 18 | ||
72 | #define CO_APIC_VIDIN1 19 | ||
73 | |||
74 | #define CO_APIC_LI_AUDIO 22 | ||
75 | |||
76 | #define CO_APIC_AS 24 | ||
77 | #define CO_APIC_RE 25 | ||
78 | |||
79 | #define CO_APIC_CPU 28 /* Timer and Cache interrupt */ | ||
80 | #define CO_APIC_NMI 29 | ||
81 | #define CO_APIC_LAST CO_APIC_NMI | ||
82 | |||
83 | /* | ||
84 | * This is how irqs are assigned on the Visual Workstation. | ||
85 | * Legacy devices get irq's 1-15 (system clock is 0 and is CO_APIC_CPU). | ||
86 | * All other devices (including PCI) go to Cobalt and are irq's 16 on up. | ||
87 | */ | ||
88 | #define CO_IRQ_APIC0 16 /* irq of apic entry 0 */ | ||
89 | #define IS_CO_APIC(irq) ((irq) >= CO_IRQ_APIC0) | ||
90 | #define CO_IRQ(apic) (CO_IRQ_APIC0 + (apic)) /* apic ent to irq */ | ||
91 | #define CO_APIC(irq) ((irq) - CO_IRQ_APIC0) /* irq to apic ent */ | ||
92 | #define CO_IRQ_IDE0 14 /* knowledge of... */ | ||
93 | #define CO_IRQ_IDE1 15 /* ... ide driver defaults! */ | ||
94 | #define CO_IRQ_8259 CO_IRQ(CO_APIC_8259) | ||
95 | |||
96 | #ifdef CONFIG_X86_VISWS_APIC | ||
97 | extern __inline void co_cpu_write(unsigned long reg, unsigned long v) | ||
98 | { | ||
99 | *((volatile unsigned long *)(CO_CPU_VADDR+reg))=v; | ||
100 | } | ||
101 | |||
102 | extern __inline unsigned long co_cpu_read(unsigned long reg) | ||
103 | { | ||
104 | return *((volatile unsigned long *)(CO_CPU_VADDR+reg)); | ||
105 | } | ||
106 | |||
107 | extern __inline void co_apic_write(unsigned long reg, unsigned long v) | ||
108 | { | ||
109 | *((volatile unsigned long *)(CO_APIC_VADDR+reg))=v; | ||
110 | } | ||
111 | |||
112 | extern __inline unsigned long co_apic_read(unsigned long reg) | ||
113 | { | ||
114 | return *((volatile unsigned long *)(CO_APIC_VADDR+reg)); | ||
115 | } | ||
116 | #endif | ||
117 | |||
118 | extern char visws_board_type; | ||
119 | |||
120 | #define VISWS_320 0 | ||
121 | #define VISWS_540 1 | ||
122 | |||
123 | extern char visws_board_rev; | ||
124 | |||
125 | #endif /* __I386_SGI_COBALT_H */ | ||
diff --git a/include/asm-x86/mach-visws/entry_arch.h b/include/asm-x86/mach-visws/entry_arch.h new file mode 100644 index 000000000000..b183fa6d83d9 --- /dev/null +++ b/include/asm-x86/mach-visws/entry_arch.h | |||
@@ -0,0 +1,23 @@ | |||
1 | /* | ||
2 | * The following vectors are part of the Linux architecture, there | ||
3 | * is no hardware IRQ pin equivalent for them, they are triggered | ||
4 | * through the ICC by us (IPIs) | ||
5 | */ | ||
6 | #ifdef CONFIG_X86_SMP | ||
7 | BUILD_INTERRUPT(reschedule_interrupt,RESCHEDULE_VECTOR) | ||
8 | BUILD_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR) | ||
9 | BUILD_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR) | ||
10 | #endif | ||
11 | |||
12 | /* | ||
13 | * every pentium local APIC has two 'local interrupts', with a | ||
14 | * soft-definable vector attached to both interrupts, one of | ||
15 | * which is a timer interrupt, the other one is error counter | ||
16 | * overflow. Linux uses the local APIC timer interrupt to get | ||
17 | * a much simpler SMP time architecture: | ||
18 | */ | ||
19 | #ifdef CONFIG_X86_LOCAL_APIC | ||
20 | BUILD_INTERRUPT(apic_timer_interrupt,LOCAL_TIMER_VECTOR) | ||
21 | BUILD_INTERRUPT(error_interrupt,ERROR_APIC_VECTOR) | ||
22 | BUILD_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR) | ||
23 | #endif | ||
diff --git a/include/asm-x86/mach-visws/irq_vectors.h b/include/asm-x86/mach-visws/irq_vectors.h new file mode 100644 index 000000000000..cb572d8db505 --- /dev/null +++ b/include/asm-x86/mach-visws/irq_vectors.h | |||
@@ -0,0 +1,62 @@ | |||
1 | #ifndef _ASM_IRQ_VECTORS_H | ||
2 | #define _ASM_IRQ_VECTORS_H | ||
3 | |||
4 | /* | ||
5 | * IDT vectors usable for external interrupt sources start | ||
6 | * at 0x20: | ||
7 | */ | ||
8 | #define FIRST_EXTERNAL_VECTOR 0x20 | ||
9 | |||
10 | #define SYSCALL_VECTOR 0x80 | ||
11 | |||
12 | /* | ||
13 | * Vectors 0x20-0x2f are used for ISA interrupts. | ||
14 | */ | ||
15 | |||
16 | /* | ||
17 | * Special IRQ vectors used by the SMP architecture, 0xf0-0xff | ||
18 | * | ||
19 | * some of the following vectors are 'rare', they are merged | ||
20 | * into a single vector (CALL_FUNCTION_VECTOR) to save vector space. | ||
21 | * TLB, reschedule and local APIC vectors are performance-critical. | ||
22 | * | ||
23 | * Vectors 0xf0-0xfa are free (reserved for future Linux use). | ||
24 | */ | ||
25 | #define SPURIOUS_APIC_VECTOR 0xff | ||
26 | #define ERROR_APIC_VECTOR 0xfe | ||
27 | #define INVALIDATE_TLB_VECTOR 0xfd | ||
28 | #define RESCHEDULE_VECTOR 0xfc | ||
29 | #define CALL_FUNCTION_VECTOR 0xfb | ||
30 | |||
31 | #define THERMAL_APIC_VECTOR 0xf0 | ||
32 | /* | ||
33 | * Local APIC timer IRQ vector is on a different priority level, | ||
34 | * to work around the 'lost local interrupt if more than 2 IRQ | ||
35 | * sources per level' errata. | ||
36 | */ | ||
37 | #define LOCAL_TIMER_VECTOR 0xef | ||
38 | |||
39 | /* | ||
40 | * First APIC vector available to drivers: (vectors 0x30-0xee) | ||
41 | * we start at 0x31 to spread out vectors evenly between priority | ||
42 | * levels. (0x80 is the syscall vector) | ||
43 | */ | ||
44 | #define FIRST_DEVICE_VECTOR 0x31 | ||
45 | #define FIRST_SYSTEM_VECTOR 0xef | ||
46 | |||
47 | #define TIMER_IRQ 0 | ||
48 | |||
49 | /* | ||
50 | * IRQ definitions | ||
51 | */ | ||
52 | #define NR_VECTORS 256 | ||
53 | #define NR_IRQS 224 | ||
54 | #define NR_IRQ_VECTORS NR_IRQS | ||
55 | |||
56 | #define FPU_IRQ 13 | ||
57 | |||
58 | #define FIRST_VM86_IRQ 3 | ||
59 | #define LAST_VM86_IRQ 15 | ||
60 | #define invalid_vm86_irq(irq) ((irq) < 3 || (irq) > 15) | ||
61 | |||
62 | #endif /* _ASM_IRQ_VECTORS_H */ | ||
diff --git a/include/asm-x86/mach-visws/lithium.h b/include/asm-x86/mach-visws/lithium.h new file mode 100644 index 000000000000..d443e68d0066 --- /dev/null +++ b/include/asm-x86/mach-visws/lithium.h | |||
@@ -0,0 +1,53 @@ | |||
1 | #ifndef __I386_SGI_LITHIUM_H | ||
2 | #define __I386_SGI_LITHIUM_H | ||
3 | |||
4 | #include <asm/fixmap.h> | ||
5 | |||
6 | /* | ||
7 | * Lithium is the SGI Visual Workstation I/O ASIC | ||
8 | */ | ||
9 | |||
10 | #define LI_PCI_A_PHYS 0xfc000000 /* Enet is dev 3 */ | ||
11 | #define LI_PCI_B_PHYS 0xfd000000 /* PIIX4 is here */ | ||
12 | |||
13 | /* see set_fixmap() and asm/fixmap.h */ | ||
14 | #define LI_PCIA_VADDR (fix_to_virt(FIX_LI_PCIA)) | ||
15 | #define LI_PCIB_VADDR (fix_to_virt(FIX_LI_PCIB)) | ||
16 | |||
17 | /* Not a standard PCI? (not in linux/pci.h) */ | ||
18 | #define LI_PCI_BUSNUM 0x44 /* lo8: primary, hi8: sub */ | ||
19 | #define LI_PCI_INTEN 0x46 | ||
20 | |||
21 | /* LI_PCI_INTENT bits */ | ||
22 | #define LI_INTA_0 0x0001 | ||
23 | #define LI_INTA_1 0x0002 | ||
24 | #define LI_INTA_2 0x0004 | ||
25 | #define LI_INTA_3 0x0008 | ||
26 | #define LI_INTA_4 0x0010 | ||
27 | #define LI_INTB 0x0020 | ||
28 | #define LI_INTC 0x0040 | ||
29 | #define LI_INTD 0x0080 | ||
30 | |||
31 | /* More special purpose macros... */ | ||
32 | extern __inline void li_pcia_write16(unsigned long reg, unsigned short v) | ||
33 | { | ||
34 | *((volatile unsigned short *)(LI_PCIA_VADDR+reg))=v; | ||
35 | } | ||
36 | |||
37 | extern __inline unsigned short li_pcia_read16(unsigned long reg) | ||
38 | { | ||
39 | return *((volatile unsigned short *)(LI_PCIA_VADDR+reg)); | ||
40 | } | ||
41 | |||
42 | extern __inline void li_pcib_write16(unsigned long reg, unsigned short v) | ||
43 | { | ||
44 | *((volatile unsigned short *)(LI_PCIB_VADDR+reg))=v; | ||
45 | } | ||
46 | |||
47 | extern __inline unsigned short li_pcib_read16(unsigned long reg) | ||
48 | { | ||
49 | return *((volatile unsigned short *)(LI_PCIB_VADDR+reg)); | ||
50 | } | ||
51 | |||
52 | #endif | ||
53 | |||
diff --git a/include/asm-x86/mach-visws/mach_apic.h b/include/asm-x86/mach-visws/mach_apic.h new file mode 100644 index 000000000000..efac6f0d139f --- /dev/null +++ b/include/asm-x86/mach-visws/mach_apic.h | |||
@@ -0,0 +1,103 @@ | |||
1 | #ifndef __ASM_MACH_APIC_H | ||
2 | #define __ASM_MACH_APIC_H | ||
3 | |||
4 | #include <mach_apicdef.h> | ||
5 | #include <asm/smp.h> | ||
6 | |||
7 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) | ||
8 | |||
9 | #define no_balance_irq (0) | ||
10 | #define esr_disable (0) | ||
11 | |||
12 | #define INT_DELIVERY_MODE dest_LowestPrio | ||
13 | #define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */ | ||
14 | |||
15 | #ifdef CONFIG_SMP | ||
16 | #define TARGET_CPUS cpu_online_map | ||
17 | #else | ||
18 | #define TARGET_CPUS cpumask_of_cpu(0) | ||
19 | #endif | ||
20 | |||
21 | #define check_apicid_used(bitmap, apicid) physid_isset(apicid, bitmap) | ||
22 | #define check_apicid_present(bit) physid_isset(bit, phys_cpu_present_map) | ||
23 | |||
24 | static inline int apic_id_registered(void) | ||
25 | { | ||
26 | return physid_isset(GET_APIC_ID(apic_read(APIC_ID)), phys_cpu_present_map); | ||
27 | } | ||
28 | |||
29 | /* | ||
30 | * Set up the logical destination ID. | ||
31 | * | ||
32 | * Intel recommends to set DFR, LDR and TPR before enabling | ||
33 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | ||
34 | * document number 292116). So here it goes... | ||
35 | */ | ||
36 | static inline void init_apic_ldr(void) | ||
37 | { | ||
38 | unsigned long val; | ||
39 | |||
40 | apic_write_around(APIC_DFR, APIC_DFR_VALUE); | ||
41 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | ||
42 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); | ||
43 | apic_write_around(APIC_LDR, val); | ||
44 | } | ||
45 | |||
46 | static inline void summit_check(char *oem, char *productid) | ||
47 | { | ||
48 | } | ||
49 | |||
50 | static inline void setup_apic_routing(void) | ||
51 | { | ||
52 | } | ||
53 | |||
54 | static inline int apicid_to_node(int logical_apicid) | ||
55 | { | ||
56 | return 0; | ||
57 | } | ||
58 | |||
59 | /* Mapping from cpu number to logical apicid */ | ||
60 | static inline int cpu_to_logical_apicid(int cpu) | ||
61 | { | ||
62 | return 1 << cpu; | ||
63 | } | ||
64 | |||
65 | static inline int cpu_present_to_apicid(int mps_cpu) | ||
66 | { | ||
67 | if (mps_cpu < get_physical_broadcast()) | ||
68 | return mps_cpu; | ||
69 | else | ||
70 | return BAD_APICID; | ||
71 | } | ||
72 | |||
73 | static inline physid_mask_t apicid_to_cpu_present(int apicid) | ||
74 | { | ||
75 | return physid_mask_of_physid(apicid); | ||
76 | } | ||
77 | |||
78 | #define WAKE_SECONDARY_VIA_INIT | ||
79 | |||
80 | static inline void setup_portio_remap(void) | ||
81 | { | ||
82 | } | ||
83 | |||
84 | static inline void enable_apic_mode(void) | ||
85 | { | ||
86 | } | ||
87 | |||
88 | static inline int check_phys_apicid_present(int boot_cpu_physical_apicid) | ||
89 | { | ||
90 | return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map); | ||
91 | } | ||
92 | |||
93 | static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask) | ||
94 | { | ||
95 | return cpus_addr(cpumask)[0]; | ||
96 | } | ||
97 | |||
98 | static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb) | ||
99 | { | ||
100 | return cpuid_apic >> index_msb; | ||
101 | } | ||
102 | |||
103 | #endif /* __ASM_MACH_APIC_H */ | ||
diff --git a/include/asm-x86/mach-visws/mach_apicdef.h b/include/asm-x86/mach-visws/mach_apicdef.h new file mode 100644 index 000000000000..826cfa97d778 --- /dev/null +++ b/include/asm-x86/mach-visws/mach_apicdef.h | |||
@@ -0,0 +1,12 @@ | |||
1 | #ifndef __ASM_MACH_APICDEF_H | ||
2 | #define __ASM_MACH_APICDEF_H | ||
3 | |||
4 | #define APIC_ID_MASK (0xF<<24) | ||
5 | |||
6 | static inline unsigned get_apic_id(unsigned long x) | ||
7 | { | ||
8 | return (((x)>>24)&0xF); | ||
9 | } | ||
10 | #define GET_APIC_ID(x) get_apic_id(x) | ||
11 | |||
12 | #endif | ||
diff --git a/include/asm-x86/mach-visws/piix4.h b/include/asm-x86/mach-visws/piix4.h new file mode 100644 index 000000000000..83ea4f46e419 --- /dev/null +++ b/include/asm-x86/mach-visws/piix4.h | |||
@@ -0,0 +1,107 @@ | |||
1 | #ifndef __I386_SGI_PIIX_H | ||
2 | #define __I386_SGI_PIIX_H | ||
3 | |||
4 | /* | ||
5 | * PIIX4 as used on SGI Visual Workstations | ||
6 | */ | ||
7 | |||
8 | #define PIIX_PM_START 0x0F80 | ||
9 | |||
10 | #define SIO_GPIO_START 0x0FC0 | ||
11 | |||
12 | #define SIO_PM_START 0x0FC8 | ||
13 | |||
14 | #define PMBASE PIIX_PM_START | ||
15 | #define GPIREG0 (PMBASE+0x30) | ||
16 | #define GPIREG(x) (GPIREG0+((x)/8)) | ||
17 | #define GPIBIT(x) (1 << ((x)%8)) | ||
18 | |||
19 | #define PIIX_GPI_BD_ID1 18 | ||
20 | #define PIIX_GPI_BD_ID2 19 | ||
21 | #define PIIX_GPI_BD_ID3 20 | ||
22 | #define PIIX_GPI_BD_ID4 21 | ||
23 | #define PIIX_GPI_BD_REG GPIREG(PIIX_GPI_BD_ID1) | ||
24 | #define PIIX_GPI_BD_MASK (GPIBIT(PIIX_GPI_BD_ID1) | \ | ||
25 | GPIBIT(PIIX_GPI_BD_ID2) | \ | ||
26 | GPIBIT(PIIX_GPI_BD_ID3) | \ | ||
27 | GPIBIT(PIIX_GPI_BD_ID4) ) | ||
28 | |||
29 | #define PIIX_GPI_BD_SHIFT (PIIX_GPI_BD_ID1 % 8) | ||
30 | |||
31 | #define SIO_INDEX 0x2e | ||
32 | #define SIO_DATA 0x2f | ||
33 | |||
34 | #define SIO_DEV_SEL 0x7 | ||
35 | #define SIO_DEV_ENB 0x30 | ||
36 | #define SIO_DEV_MSB 0x60 | ||
37 | #define SIO_DEV_LSB 0x61 | ||
38 | |||
39 | #define SIO_GP_DEV 0x7 | ||
40 | |||
41 | #define SIO_GP_BASE SIO_GPIO_START | ||
42 | #define SIO_GP_MSB (SIO_GP_BASE>>8) | ||
43 | #define SIO_GP_LSB (SIO_GP_BASE&0xff) | ||
44 | |||
45 | #define SIO_GP_DATA1 (SIO_GP_BASE+0) | ||
46 | |||
47 | #define SIO_PM_DEV 0x8 | ||
48 | |||
49 | #define SIO_PM_BASE SIO_PM_START | ||
50 | #define SIO_PM_MSB (SIO_PM_BASE>>8) | ||
51 | #define SIO_PM_LSB (SIO_PM_BASE&0xff) | ||
52 | #define SIO_PM_INDEX (SIO_PM_BASE+0) | ||
53 | #define SIO_PM_DATA (SIO_PM_BASE+1) | ||
54 | |||
55 | #define SIO_PM_FER2 0x1 | ||
56 | |||
57 | #define SIO_PM_GP_EN 0x80 | ||
58 | |||
59 | |||
60 | |||
61 | /* | ||
62 | * This is the dev/reg where generating a config cycle will | ||
63 | * result in a PCI special cycle. | ||
64 | */ | ||
65 | #define SPECIAL_DEV 0xff | ||
66 | #define SPECIAL_REG 0x00 | ||
67 | |||
68 | /* | ||
69 | * PIIX4 needs to see a special cycle with the following data | ||
70 | * to be convinced the processor has gone into the stop grant | ||
71 | * state. PIIX4 insists on seeing this before it will power | ||
72 | * down a system. | ||
73 | */ | ||
74 | #define PIIX_SPECIAL_STOP 0x00120002 | ||
75 | |||
76 | #define PIIX4_RESET_PORT 0xcf9 | ||
77 | #define PIIX4_RESET_VAL 0x6 | ||
78 | |||
79 | #define PMSTS_PORT 0xf80 // 2 bytes PM Status | ||
80 | #define PMEN_PORT 0xf82 // 2 bytes PM Enable | ||
81 | #define PMCNTRL_PORT 0xf84 // 2 bytes PM Control | ||
82 | |||
83 | #define PM_SUSPEND_ENABLE 0x2000 // start sequence to suspend state | ||
84 | |||
85 | /* | ||
86 | * PMSTS and PMEN I/O bit definitions. | ||
87 | * (Bits are the same in both registers) | ||
88 | */ | ||
89 | #define PM_STS_RSM (1<<15) // Resume Status | ||
90 | #define PM_STS_PWRBTNOR (1<<11) // Power Button Override | ||
91 | #define PM_STS_RTC (1<<10) // RTC status | ||
92 | #define PM_STS_PWRBTN (1<<8) // Power Button Pressed? | ||
93 | #define PM_STS_GBL (1<<5) // Global Status | ||
94 | #define PM_STS_BM (1<<4) // Bus Master Status | ||
95 | #define PM_STS_TMROF (1<<0) // Timer Overflow Status. | ||
96 | |||
97 | /* | ||
98 | * Stop clock GPI register | ||
99 | */ | ||
100 | #define PIIX_GPIREG0 (0xf80 + 0x30) | ||
101 | |||
102 | /* | ||
103 | * Stop clock GPI bit in GPIREG0 | ||
104 | */ | ||
105 | #define PIIX_GPI_STPCLK 0x4 // STPCLK signal routed back in | ||
106 | |||
107 | #endif | ||
diff --git a/include/asm-x86/mach-visws/setup_arch.h b/include/asm-x86/mach-visws/setup_arch.h new file mode 100644 index 000000000000..33f700ef6831 --- /dev/null +++ b/include/asm-x86/mach-visws/setup_arch.h | |||
@@ -0,0 +1,8 @@ | |||
1 | /* Hook to call BIOS initialisation function */ | ||
2 | |||
3 | extern unsigned long sgivwfb_mem_phys; | ||
4 | extern unsigned long sgivwfb_mem_size; | ||
5 | |||
6 | /* no action for visws */ | ||
7 | |||
8 | #define ARCH_SETUP | ||
diff --git a/include/asm-x86/mach-visws/smpboot_hooks.h b/include/asm-x86/mach-visws/smpboot_hooks.h new file mode 100644 index 000000000000..d926471fa359 --- /dev/null +++ b/include/asm-x86/mach-visws/smpboot_hooks.h | |||
@@ -0,0 +1,24 @@ | |||
1 | static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) | ||
2 | { | ||
3 | CMOS_WRITE(0xa, 0xf); | ||
4 | local_flush_tlb(); | ||
5 | Dprintk("1.\n"); | ||
6 | *((volatile unsigned short *) TRAMPOLINE_HIGH) = start_eip >> 4; | ||
7 | Dprintk("2.\n"); | ||
8 | *((volatile unsigned short *) TRAMPOLINE_LOW) = start_eip & 0xf; | ||
9 | Dprintk("3.\n"); | ||
10 | } | ||
11 | |||
12 | /* for visws do nothing for any of these */ | ||
13 | |||
14 | static inline void smpboot_clear_io_apic_irqs(void) | ||
15 | { | ||
16 | } | ||
17 | |||
18 | static inline void smpboot_restore_warm_reset_vector(void) | ||
19 | { | ||
20 | } | ||
21 | |||
22 | static inline void smpboot_setup_io_apic(void) | ||
23 | { | ||
24 | } | ||