aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-x86/mach-es7000/mach_apic.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-x86/mach-es7000/mach_apic.h')
-rw-r--r--include/asm-x86/mach-es7000/mach_apic.h194
1 files changed, 0 insertions, 194 deletions
diff --git a/include/asm-x86/mach-es7000/mach_apic.h b/include/asm-x86/mach-es7000/mach_apic.h
deleted file mode 100644
index 0a3fdf930672..000000000000
--- a/include/asm-x86/mach-es7000/mach_apic.h
+++ /dev/null
@@ -1,194 +0,0 @@
1#ifndef __ASM_MACH_APIC_H
2#define __ASM_MACH_APIC_H
3
4#define xapic_phys_to_log_apicid(cpu) per_cpu(x86_bios_cpu_apicid, cpu)
5#define esr_disable (1)
6
7static inline int apic_id_registered(void)
8{
9 return (1);
10}
11
12static inline cpumask_t target_cpus(void)
13{
14#if defined CONFIG_ES7000_CLUSTERED_APIC
15 return CPU_MASK_ALL;
16#else
17 return cpumask_of_cpu(smp_processor_id());
18#endif
19}
20#define TARGET_CPUS (target_cpus())
21
22#if defined CONFIG_ES7000_CLUSTERED_APIC
23#define APIC_DFR_VALUE (APIC_DFR_CLUSTER)
24#define INT_DELIVERY_MODE (dest_LowestPrio)
25#define INT_DEST_MODE (1) /* logical delivery broadcast to all procs */
26#define NO_BALANCE_IRQ (1)
27#undef WAKE_SECONDARY_VIA_INIT
28#define WAKE_SECONDARY_VIA_MIP
29#else
30#define APIC_DFR_VALUE (APIC_DFR_FLAT)
31#define INT_DELIVERY_MODE (dest_Fixed)
32#define INT_DEST_MODE (0) /* phys delivery to target procs */
33#define NO_BALANCE_IRQ (0)
34#undef APIC_DEST_LOGICAL
35#define APIC_DEST_LOGICAL 0x0
36#define WAKE_SECONDARY_VIA_INIT
37#endif
38
39static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
40{
41 return 0;
42}
43static inline unsigned long check_apicid_present(int bit)
44{
45 return physid_isset(bit, phys_cpu_present_map);
46}
47
48#define apicid_cluster(apicid) (apicid & 0xF0)
49
50static inline unsigned long calculate_ldr(int cpu)
51{
52 unsigned long id;
53 id = xapic_phys_to_log_apicid(cpu);
54 return (SET_APIC_LOGICAL_ID(id));
55}
56
57/*
58 * Set up the logical destination ID.
59 *
60 * Intel recommends to set DFR, LdR and TPR before enabling
61 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
62 * document number 292116). So here it goes...
63 */
64static inline void init_apic_ldr(void)
65{
66 unsigned long val;
67 int cpu = smp_processor_id();
68
69 apic_write(APIC_DFR, APIC_DFR_VALUE);
70 val = calculate_ldr(cpu);
71 apic_write(APIC_LDR, val);
72}
73
74#ifndef CONFIG_X86_GENERICARCH
75extern void enable_apic_mode(void);
76#endif
77
78extern int apic_version [MAX_APICS];
79static inline void setup_apic_routing(void)
80{
81 int apic = per_cpu(x86_bios_cpu_apicid, smp_processor_id());
82 printk("Enabling APIC mode: %s. Using %d I/O APICs, target cpus %lx\n",
83 (apic_version[apic] == 0x14) ?
84 "Physical Cluster" : "Logical Cluster", nr_ioapics, cpus_addr(TARGET_CPUS)[0]);
85}
86
87static inline int multi_timer_check(int apic, int irq)
88{
89 return 0;
90}
91
92static inline int apicid_to_node(int logical_apicid)
93{
94 return 0;
95}
96
97
98static inline int cpu_present_to_apicid(int mps_cpu)
99{
100 if (!mps_cpu)
101 return boot_cpu_physical_apicid;
102 else if (mps_cpu < NR_CPUS)
103 return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu);
104 else
105 return BAD_APICID;
106}
107
108static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
109{
110 static int id = 0;
111 physid_mask_t mask;
112 mask = physid_mask_of_physid(id);
113 ++id;
114 return mask;
115}
116
117extern u8 cpu_2_logical_apicid[];
118/* Mapping from cpu number to logical apicid */
119static inline int cpu_to_logical_apicid(int cpu)
120{
121#ifdef CONFIG_SMP
122 if (cpu >= NR_CPUS)
123 return BAD_APICID;
124 return (int)cpu_2_logical_apicid[cpu];
125#else
126 return logical_smp_processor_id();
127#endif
128}
129
130static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
131{
132 /* For clustered we don't have a good way to do this yet - hack */
133 return physids_promote(0xff);
134}
135
136
137static inline void setup_portio_remap(void)
138{
139}
140
141extern unsigned int boot_cpu_physical_apicid;
142static inline int check_phys_apicid_present(int cpu_physical_apicid)
143{
144 boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
145 return (1);
146}
147
148static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
149{
150 int num_bits_set;
151 int cpus_found = 0;
152 int cpu;
153 int apicid;
154
155 num_bits_set = cpus_weight(cpumask);
156 /* Return id to all */
157 if (num_bits_set == NR_CPUS)
158#if defined CONFIG_ES7000_CLUSTERED_APIC
159 return 0xFF;
160#else
161 return cpu_to_logical_apicid(0);
162#endif
163 /*
164 * The cpus in the mask must all be on the apic cluster. If are not
165 * on the same apicid cluster return default value of TARGET_CPUS.
166 */
167 cpu = first_cpu(cpumask);
168 apicid = cpu_to_logical_apicid(cpu);
169 while (cpus_found < num_bits_set) {
170 if (cpu_isset(cpu, cpumask)) {
171 int new_apicid = cpu_to_logical_apicid(cpu);
172 if (apicid_cluster(apicid) !=
173 apicid_cluster(new_apicid)){
174 printk ("%s: Not a valid mask!\n",__FUNCTION__);
175#if defined CONFIG_ES7000_CLUSTERED_APIC
176 return 0xFF;
177#else
178 return cpu_to_logical_apicid(0);
179#endif
180 }
181 apicid = new_apicid;
182 cpus_found++;
183 }
184 cpu++;
185 }
186 return apicid;
187}
188
189static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
190{
191 return cpuid_apic >> index_msb;
192}
193
194#endif /* __ASM_MACH_APIC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 06:19:04 -0500