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-rw-r--r--include/asm-x86/es7000/apic.h193
1 files changed, 0 insertions, 193 deletions
diff --git a/include/asm-x86/es7000/apic.h b/include/asm-x86/es7000/apic.h
deleted file mode 100644
index 380f0b4f17ed..000000000000
--- a/include/asm-x86/es7000/apic.h
+++ /dev/null
@@ -1,193 +0,0 @@
1#ifndef __ASM_ES7000_APIC_H
2#define __ASM_ES7000_APIC_H
3
4#define xapic_phys_to_log_apicid(cpu) per_cpu(x86_bios_cpu_apicid, cpu)
5#define esr_disable (1)
6
7static inline int apic_id_registered(void)
8{
9 return (1);
10}
11
12static inline cpumask_t target_cpus(void)
13{
14#if defined CONFIG_ES7000_CLUSTERED_APIC
15 return CPU_MASK_ALL;
16#else
17 return cpumask_of_cpu(smp_processor_id());
18#endif
19}
20
21#if defined CONFIG_ES7000_CLUSTERED_APIC
22#define APIC_DFR_VALUE (APIC_DFR_CLUSTER)
23#define INT_DELIVERY_MODE (dest_LowestPrio)
24#define INT_DEST_MODE (1) /* logical delivery broadcast to all procs */
25#define NO_BALANCE_IRQ (1)
26#undef WAKE_SECONDARY_VIA_INIT
27#define WAKE_SECONDARY_VIA_MIP
28#else
29#define APIC_DFR_VALUE (APIC_DFR_FLAT)
30#define INT_DELIVERY_MODE (dest_Fixed)
31#define INT_DEST_MODE (0) /* phys delivery to target procs */
32#define NO_BALANCE_IRQ (0)
33#undef APIC_DEST_LOGICAL
34#define APIC_DEST_LOGICAL 0x0
35#define WAKE_SECONDARY_VIA_INIT
36#endif
37
38static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
39{
40 return 0;
41}
42static inline unsigned long check_apicid_present(int bit)
43{
44 return physid_isset(bit, phys_cpu_present_map);
45}
46
47#define apicid_cluster(apicid) (apicid & 0xF0)
48
49static inline unsigned long calculate_ldr(int cpu)
50{
51 unsigned long id;
52 id = xapic_phys_to_log_apicid(cpu);
53 return (SET_APIC_LOGICAL_ID(id));
54}
55
56/*
57 * Set up the logical destination ID.
58 *
59 * Intel recommends to set DFR, LdR and TPR before enabling
60 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
61 * document number 292116). So here it goes...
62 */
63static inline void init_apic_ldr(void)
64{
65 unsigned long val;
66 int cpu = smp_processor_id();
67
68 apic_write(APIC_DFR, APIC_DFR_VALUE);
69 val = calculate_ldr(cpu);
70 apic_write(APIC_LDR, val);
71}
72
73#ifndef CONFIG_X86_GENERICARCH
74extern void enable_apic_mode(void);
75#endif
76
77extern int apic_version [MAX_APICS];
78static inline void setup_apic_routing(void)
79{
80 int apic = per_cpu(x86_bios_cpu_apicid, smp_processor_id());
81 printk("Enabling APIC mode: %s. Using %d I/O APICs, target cpus %lx\n",
82 (apic_version[apic] == 0x14) ?
83 "Physical Cluster" : "Logical Cluster", nr_ioapics, cpus_addr(target_cpus())[0]);
84}
85
86static inline int multi_timer_check(int apic, int irq)
87{
88 return 0;
89}
90
91static inline int apicid_to_node(int logical_apicid)
92{
93 return 0;
94}
95
96
97static inline int cpu_present_to_apicid(int mps_cpu)
98{
99 if (!mps_cpu)
100 return boot_cpu_physical_apicid;
101 else if (mps_cpu < NR_CPUS)
102 return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu);
103 else
104 return BAD_APICID;
105}
106
107static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
108{
109 static int id = 0;
110 physid_mask_t mask;
111 mask = physid_mask_of_physid(id);
112 ++id;
113 return mask;
114}
115
116extern u8 cpu_2_logical_apicid[];
117/* Mapping from cpu number to logical apicid */
118static inline int cpu_to_logical_apicid(int cpu)
119{
120#ifdef CONFIG_SMP
121 if (cpu >= NR_CPUS)
122 return BAD_APICID;
123 return (int)cpu_2_logical_apicid[cpu];
124#else
125 return logical_smp_processor_id();
126#endif
127}
128
129static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
130{
131 /* For clustered we don't have a good way to do this yet - hack */
132 return physids_promote(0xff);
133}
134
135
136static inline void setup_portio_remap(void)
137{
138}
139
140extern unsigned int boot_cpu_physical_apicid;
141static inline int check_phys_apicid_present(int cpu_physical_apicid)
142{
143 boot_cpu_physical_apicid = read_apic_id();
144 return (1);
145}
146
147static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
148{
149 int num_bits_set;
150 int cpus_found = 0;
151 int cpu;
152 int apicid;
153
154 num_bits_set = cpus_weight(cpumask);
155 /* Return id to all */
156 if (num_bits_set == NR_CPUS)
157#if defined CONFIG_ES7000_CLUSTERED_APIC
158 return 0xFF;
159#else
160 return cpu_to_logical_apicid(0);
161#endif
162 /*
163 * The cpus in the mask must all be on the apic cluster. If are not
164 * on the same apicid cluster return default value of TARGET_CPUS.
165 */
166 cpu = first_cpu(cpumask);
167 apicid = cpu_to_logical_apicid(cpu);
168 while (cpus_found < num_bits_set) {
169 if (cpu_isset(cpu, cpumask)) {
170 int new_apicid = cpu_to_logical_apicid(cpu);
171 if (apicid_cluster(apicid) !=
172 apicid_cluster(new_apicid)){
173 printk ("%s: Not a valid mask!\n", __func__);
174#if defined CONFIG_ES7000_CLUSTERED_APIC
175 return 0xFF;
176#else
177 return cpu_to_logical_apicid(0);
178#endif
179 }
180 apicid = new_apicid;
181 cpus_found++;
182 }
183 cpu++;
184 }
185 return apicid;
186}
187
188static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
189{
190 return cpuid_apic >> index_msb;
191}
192
193#endif /* __ASM_ES7000_APIC_H */
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