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-rw-r--r--include/asm-x86/cpufeature.h20
1 files changed, 12 insertions, 8 deletions
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 2f5a792b0acc..250fa0cb144b 100644
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -1,8 +1,8 @@
1/* 1/*
2 * Defines x86 CPU feature bits 2 * Defines x86 CPU feature bits
3 */ 3 */
4#ifndef _ASM_X86_CPUFEATURE_H 4#ifndef ASM_X86__CPUFEATURE_H
5#define _ASM_X86_CPUFEATURE_H 5#define ASM_X86__CPUFEATURE_H
6 6
7#include <asm/required-features.h> 7#include <asm/required-features.h>
8 8
@@ -72,14 +72,16 @@
72#define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */ 72#define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */
73#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */ 73#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */
74#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ 74#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
75#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ 75#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
76#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ 76#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
77#define X86_FEATURE_SYSCALL32 (3*32+14) /* syscall in ia32 userspace */ 77#define X86_FEATURE_SYSCALL32 (3*32+14) /* syscall in ia32 userspace */
78#define X86_FEATURE_SYSENTER32 (3*32+15) /* sysenter in ia32 userspace */ 78#define X86_FEATURE_SYSENTER32 (3*32+15) /* sysenter in ia32 userspace */
79#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ 79#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */
80#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */ 80#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
81#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */ 81#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */
82#define X86_FEATURE_11AP (3*32+19) /* Bad local APIC aka 11AP */ 82#define X86_FEATURE_11AP (3*32+19) /* Bad local APIC aka 11AP */
83#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */
84#define X86_FEATURE_AMDC1E (3*32+21) /* AMD C1E detected */
83 85
84/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ 86/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
85#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ 87#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
@@ -91,6 +93,7 @@
91#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ 93#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
92#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ 94#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
93#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */ 95#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
96#define X86_FEATURE_XMM4_2 (4*32+20) /* Streaming SIMD Extensions-4.2 */
94 97
95/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ 98/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
96#define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */ 99#define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */
@@ -189,6 +192,7 @@ extern const char * const x86_power_flags[32];
189#define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES) 192#define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES)
190#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) 193#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
191#define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) 194#define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
195#define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2)
192 196
193#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64) 197#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
194# define cpu_has_invlpg 1 198# define cpu_has_invlpg 1
@@ -220,4 +224,4 @@ extern const char * const x86_power_flags[32];
220 224
221#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */ 225#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */
222 226
223#endif /* _ASM_X86_CPUFEATURE_H */ 227#endif /* ASM_X86__CPUFEATURE_H */