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-rw-r--r--include/asm-x86/cpufeature.h119
1 files changed, 78 insertions, 41 deletions
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 762f6a6bc707..7ac4d93d20ed 100644
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -1,20 +1,26 @@
1/* 1/*
2 * Defines x86 CPU feature bits 2 * Defines x86 CPU feature bits
3 */ 3 */
4#ifndef _ASM_X86_CPUFEATURE_H 4#ifndef ASM_X86__CPUFEATURE_H
5#define _ASM_X86_CPUFEATURE_H 5#define ASM_X86__CPUFEATURE_H
6 6
7#include <asm/required-features.h> 7#include <asm/required-features.h>
8 8
9#define NCAPINTS 8 /* N 32-bit words worth of info */ 9#define NCAPINTS 8 /* N 32-bit words worth of info */
10 10
11/*
12 * Note: If the comment begins with a quoted string, that string is used
13 * in /proc/cpuinfo instead of the macro name. If the string is "",
14 * this feature bit is not displayed in /proc/cpuinfo at all.
15 */
16
11/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ 17/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
12#define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ 18#define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */
13#define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */ 19#define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */
14#define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */ 20#define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */
15#define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */ 21#define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */
16#define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */ 22#define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */
17#define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */ 23#define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers */
18#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */ 24#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */
19#define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */ 25#define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */
20#define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */ 26#define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
@@ -23,22 +29,23 @@
23#define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */ 29#define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */
24#define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */ 30#define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */
25#define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */ 31#define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */
26#define X86_FEATURE_CMOV (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */ 32#define X86_FEATURE_CMOV (0*32+15) /* CMOV instructions */
33 /* (plus FCMOVcc, FCOMI with FPU) */
27#define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */ 34#define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */
28#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */ 35#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
29#define X86_FEATURE_PN (0*32+18) /* Processor serial number */ 36#define X86_FEATURE_PN (0*32+18) /* Processor serial number */
30#define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */ 37#define X86_FEATURE_CLFLSH (0*32+19) /* "clflush" CLFLUSH instruction */
31#define X86_FEATURE_DS (0*32+21) /* Debug Store */ 38#define X86_FEATURE_DS (0*32+21) /* "dts" Debug Store */
32#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */ 39#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */
33#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ 40#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
34#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */ 41#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
35 /* of FPU context), and CR4.OSFXSR available */ 42#define X86_FEATURE_XMM (0*32+25) /* "sse" */
36#define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */ 43#define X86_FEATURE_XMM2 (0*32+26) /* "sse2" */
37#define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */ 44#define X86_FEATURE_SELFSNOOP (0*32+27) /* "ss" CPU self snoop */
38#define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */
39#define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */ 45#define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */
40#define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */ 46#define X86_FEATURE_ACC (0*32+29) /* "tm" Automatic clock control */
41#define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */ 47#define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */
48#define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */
42 49
43/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ 50/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
44/* Don't duplicate feature flags which are redundant with Intel! */ 51/* Don't duplicate feature flags which are redundant with Intel! */
@@ -46,7 +53,8 @@
46#define X86_FEATURE_MP (1*32+19) /* MP Capable. */ 53#define X86_FEATURE_MP (1*32+19) /* MP Capable. */
47#define X86_FEATURE_NX (1*32+20) /* Execute Disable */ 54#define X86_FEATURE_NX (1*32+20) /* Execute Disable */
48#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */ 55#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
49#define X86_FEATURE_GBPAGES (1*32+26) /* GB pages */ 56#define X86_FEATURE_FXSR_OPT (1*32+25) /* FXSAVE/FXRSTOR optimizations */
57#define X86_FEATURE_GBPAGES (1*32+26) /* "pdpe1gb" GB pages */
50#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */ 58#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */
51#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */ 59#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
52#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */ 60#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
@@ -64,51 +72,77 @@
64#define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */ 72#define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
65#define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */ 73#define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
66/* cpu types for specific tunings: */ 74/* cpu types for specific tunings: */
67#define X86_FEATURE_K8 (3*32+ 4) /* Opteron, Athlon64 */ 75#define X86_FEATURE_K8 (3*32+ 4) /* "" Opteron, Athlon64 */
68#define X86_FEATURE_K7 (3*32+ 5) /* Athlon */ 76#define X86_FEATURE_K7 (3*32+ 5) /* "" Athlon */
69#define X86_FEATURE_P3 (3*32+ 6) /* P3 */ 77#define X86_FEATURE_P3 (3*32+ 6) /* "" P3 */
70#define X86_FEATURE_P4 (3*32+ 7) /* P4 */ 78#define X86_FEATURE_P4 (3*32+ 7) /* "" P4 */
71#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */ 79#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
72#define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */ 80#define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */
73#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */ 81#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */
74#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ 82#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
75#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ 83#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
76#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ 84#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
77#define X86_FEATURE_SYSCALL32 (3*32+14) /* syscall in ia32 userspace */ 85#define X86_FEATURE_SYSCALL32 (3*32+14) /* "" syscall in ia32 userspace */
78#define X86_FEATURE_SYSENTER32 (3*32+15) /* sysenter in ia32 userspace */ 86#define X86_FEATURE_SYSENTER32 (3*32+15) /* "" sysenter in ia32 userspace */
79#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ 87#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well */
80#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */ 88#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */
81#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */ 89#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */
82#define X86_FEATURE_11AP (3*32+19) /* Bad local APIC aka 11AP */ 90#define X86_FEATURE_11AP (3*32+19) /* "" Bad local APIC aka 11AP */
91#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */
92#define X86_FEATURE_XTOPOLOGY (3*32+21) /* cpu topology enum extensions */
83 93
84/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ 94/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
85#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ 95#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */
86#define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */ 96#define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* PCLMULQDQ instruction */
87#define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */ 97#define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */
98#define X86_FEATURE_MWAIT (4*32+ 3) /* "monitor" Monitor/Mwait support */
99#define X86_FEATURE_DSCPL (4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
100#define X86_FEATURE_VMX (4*32+ 5) /* Hardware virtualization */
101#define X86_FEATURE_SMX (4*32+ 6) /* Safer mode */
88#define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */ 102#define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */
89#define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */ 103#define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
104#define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */
90#define X86_FEATURE_CID (4*32+10) /* Context ID */ 105#define X86_FEATURE_CID (4*32+10) /* Context ID */
106#define X86_FEATURE_FMA (4*32+12) /* Fused multiply-add */
91#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ 107#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
92#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ 108#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
109#define X86_FEATURE_PDCM (4*32+15) /* Performance Capabilities */
93#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */ 110#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
94#define X86_FEATURE_XMM4_2 (4*32+20) /* Streaming SIMD Extensions-4.2 */ 111#define X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */
112#define X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */
113#define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */
114#define X86_FEATURE_AES (4*32+25) /* AES instructions */
115#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
116#define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */
117#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
95 118
96/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ 119/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
97#define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */ 120#define X86_FEATURE_XSTORE (5*32+ 2) /* "rng" RNG present (xstore) */
98#define X86_FEATURE_XSTORE_EN (5*32+ 3) /* on-CPU RNG enabled */ 121#define X86_FEATURE_XSTORE_EN (5*32+ 3) /* "rng_en" RNG enabled */
99#define X86_FEATURE_XCRYPT (5*32+ 6) /* on-CPU crypto (xcrypt insn) */ 122#define X86_FEATURE_XCRYPT (5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
100#define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* on-CPU crypto enabled */ 123#define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* "ace_en" on-CPU crypto enabled */
101#define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */ 124#define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */
102#define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */ 125#define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */
103#define X86_FEATURE_PHE (5*32+ 10) /* PadLock Hash Engine */ 126#define X86_FEATURE_PHE (5*32+10) /* PadLock Hash Engine */
104#define X86_FEATURE_PHE_EN (5*32+ 11) /* PHE enabled */ 127#define X86_FEATURE_PHE_EN (5*32+11) /* PHE enabled */
105#define X86_FEATURE_PMM (5*32+ 12) /* PadLock Montgomery Multiplier */ 128#define X86_FEATURE_PMM (5*32+12) /* PadLock Montgomery Multiplier */
106#define X86_FEATURE_PMM_EN (5*32+ 13) /* PMM enabled */ 129#define X86_FEATURE_PMM_EN (5*32+13) /* PMM enabled */
107 130
108/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ 131/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
109#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ 132#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */
110#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ 133#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */
111#define X86_FEATURE_IBS (6*32+ 10) /* Instruction Based Sampling */ 134#define X86_FEATURE_SVM (6*32+ 2) /* Secure virtual machine */
135#define X86_FEATURE_EXTAPIC (6*32+ 3) /* Extended APIC space */
136#define X86_FEATURE_CR8_LEGACY (6*32+ 4) /* CR8 in 32-bit mode */
137#define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */
138#define X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */
139#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */
140#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
141#define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */
142#define X86_FEATURE_IBS (6*32+10) /* Instruction Based Sampling */
143#define X86_FEATURE_SSE5 (6*32+11) /* SSE-5 */
144#define X86_FEATURE_SKINIT (6*32+12) /* SKINIT/STGI instructions */
145#define X86_FEATURE_WDT (6*32+13) /* Watchdog timer */
112 146
113/* 147/*
114 * Auxiliary flags: Linux defined - For features scattered in various 148 * Auxiliary flags: Linux defined - For features scattered in various
@@ -149,7 +183,7 @@ extern const char * const x86_power_flags[32];
149} while (0) 183} while (0)
150#define setup_force_cpu_cap(bit) do { \ 184#define setup_force_cpu_cap(bit) do { \
151 set_cpu_cap(&boot_cpu_data, bit); \ 185 set_cpu_cap(&boot_cpu_data, bit); \
152 clear_bit(bit, (unsigned long *)cleared_cpu_caps); \ 186 clear_bit(bit, (unsigned long *)cleared_cpu_caps); \
153} while (0) 187} while (0)
154 188
155#define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) 189#define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU)
@@ -190,7 +224,10 @@ extern const char * const x86_power_flags[32];
190#define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES) 224#define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES)
191#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) 225#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
192#define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) 226#define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
227#define cpu_has_xmm4_1 boot_cpu_has(X86_FEATURE_XMM4_1)
193#define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2) 228#define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2)
229#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC)
230#define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE)
194 231
195#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64) 232#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
196# define cpu_has_invlpg 1 233# define cpu_has_invlpg 1
@@ -222,4 +259,4 @@ extern const char * const x86_power_flags[32];
222 259
223#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */ 260#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */
224 261
225#endif /* _ASM_X86_CPUFEATURE_H */ 262#endif /* ASM_X86__CPUFEATURE_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 02:43:59 -0500