diff options
Diffstat (limited to 'include/asm-x86/cpufeature.h')
-rw-r--r-- | include/asm-x86/cpufeature.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h index 0d609c837a41..2f5a792b0acc 100644 --- a/include/asm-x86/cpufeature.h +++ b/include/asm-x86/cpufeature.h | |||
@@ -74,11 +74,12 @@ | |||
74 | #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ | 74 | #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ |
75 | #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ | 75 | #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ |
76 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ | 76 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ |
77 | /* 14 free */ | 77 | #define X86_FEATURE_SYSCALL32 (3*32+14) /* syscall in ia32 userspace */ |
78 | /* 15 free */ | 78 | #define X86_FEATURE_SYSENTER32 (3*32+15) /* sysenter in ia32 userspace */ |
79 | #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ | 79 | #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ |
80 | #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */ | 80 | #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */ |
81 | #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */ | 81 | #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */ |
82 | #define X86_FEATURE_11AP (3*32+19) /* Bad local APIC aka 11AP */ | ||
82 | 83 | ||
83 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | 84 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ |
84 | #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ | 85 | #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ |
@@ -106,6 +107,7 @@ | |||
106 | /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ | 107 | /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ |
107 | #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ | 108 | #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ |
108 | #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ | 109 | #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ |
110 | #define X86_FEATURE_IBS (6*32+ 10) /* Instruction Based Sampling */ | ||
109 | 111 | ||
110 | /* | 112 | /* |
111 | * Auxiliary flags: Linux defined - For features scattered in various | 113 | * Auxiliary flags: Linux defined - For features scattered in various |
@@ -142,11 +144,11 @@ extern const char * const x86_power_flags[32]; | |||
142 | #define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability)) | 144 | #define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability)) |
143 | #define setup_clear_cpu_cap(bit) do { \ | 145 | #define setup_clear_cpu_cap(bit) do { \ |
144 | clear_cpu_cap(&boot_cpu_data, bit); \ | 146 | clear_cpu_cap(&boot_cpu_data, bit); \ |
145 | set_bit(bit, cleared_cpu_caps); \ | 147 | set_bit(bit, (unsigned long *)cleared_cpu_caps); \ |
146 | } while (0) | 148 | } while (0) |
147 | #define setup_force_cpu_cap(bit) do { \ | 149 | #define setup_force_cpu_cap(bit) do { \ |
148 | set_cpu_cap(&boot_cpu_data, bit); \ | 150 | set_cpu_cap(&boot_cpu_data, bit); \ |
149 | clear_bit(bit, cleared_cpu_caps); \ | 151 | clear_bit(bit, (unsigned long *)cleared_cpu_caps); \ |
150 | } while (0) | 152 | } while (0) |
151 | 153 | ||
152 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) | 154 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) |