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Diffstat (limited to 'include/asm-v850/v850e_cache.h')
| -rw-r--r-- | include/asm-v850/v850e_cache.h | 48 |
1 files changed, 0 insertions, 48 deletions
diff --git a/include/asm-v850/v850e_cache.h b/include/asm-v850/v850e_cache.h deleted file mode 100644 index aa7d7eb9da50..000000000000 --- a/include/asm-v850/v850e_cache.h +++ /dev/null | |||
| @@ -1,48 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-v850/v850e_cache.h -- Cache control for V850E cache memories | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001,03 NEC Electronics Corporation | ||
| 5 | * Copyright (C) 2001,03 Miles Bader <miles@gnu.org> | ||
| 6 | * | ||
| 7 | * This file is subject to the terms and conditions of the GNU General | ||
| 8 | * Public License. See the file COPYING in the main directory of this | ||
| 9 | * archive for more details. | ||
| 10 | * | ||
| 11 | * Written by Miles Bader <miles@gnu.org> | ||
| 12 | */ | ||
| 13 | |||
| 14 | /* This file implements cache control for the rather simple cache used on | ||
| 15 | some V850E CPUs, specifically the NB85E/TEG CPU-core and the V850E/ME2 | ||
| 16 | CPU. V850E2 processors have their own (better) cache | ||
| 17 | implementation. */ | ||
| 18 | |||
| 19 | #ifndef __V850_V850E_CACHE_H__ | ||
| 20 | #define __V850_V850E_CACHE_H__ | ||
| 21 | |||
| 22 | #include <asm/types.h> | ||
| 23 | |||
| 24 | |||
| 25 | /* Cache control registers. */ | ||
| 26 | #define V850E_CACHE_BHC_ADDR 0xFFFFF06A | ||
| 27 | #define V850E_CACHE_BHC (*(volatile u16 *)V850E_CACHE_BHC_ADDR) | ||
| 28 | #define V850E_CACHE_ICC_ADDR 0xFFFFF070 | ||
| 29 | #define V850E_CACHE_ICC (*(volatile u16 *)V850E_CACHE_ICC_ADDR) | ||
| 30 | #define V850E_CACHE_ISI_ADDR 0xFFFFF072 | ||
| 31 | #define V850E_CACHE_ISI (*(volatile u16 *)V850E_CACHE_ISI_ADDR) | ||
| 32 | #define V850E_CACHE_DCC_ADDR 0xFFFFF078 | ||
| 33 | #define V850E_CACHE_DCC (*(volatile u16 *)V850E_CACHE_DCC_ADDR) | ||
| 34 | |||
| 35 | /* Size of a cache line in bytes. */ | ||
| 36 | #define V850E_CACHE_LINE_SIZE 16 | ||
| 37 | |||
| 38 | /* For <asm/cache.h> */ | ||
| 39 | #define L1_CACHE_BYTES V850E_CACHE_LINE_SIZE | ||
| 40 | |||
| 41 | |||
| 42 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) | ||
| 43 | /* Set caching params via the BHC, ICC, and DCC registers. */ | ||
| 44 | void v850e_cache_enable (u16 bhc, u16 icc, u16 dcc); | ||
| 45 | #endif /* __KERNEL__ && !__ASSEMBLY__ */ | ||
| 46 | |||
| 47 | |||
| 48 | #endif /* __V850_V850E_CACHE_H__ */ | ||