aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-v850/anna.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-v850/anna.h')
-rw-r--r--include/asm-v850/anna.h137
1 files changed, 0 insertions, 137 deletions
diff --git a/include/asm-v850/anna.h b/include/asm-v850/anna.h
deleted file mode 100644
index cd5eaee103b0..000000000000
--- a/include/asm-v850/anna.h
+++ /dev/null
@@ -1,137 +0,0 @@
1/*
2 * include/asm-v850/anna.h -- Anna V850E2 evaluation cpu chip/board
3 *
4 * Copyright (C) 2001,02,03 NEC Electronics Corporation
5 * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
6 *
7 * This file is subject to the terms and conditions of the GNU General
8 * Public License. See the file COPYING in the main directory of this
9 * archive for more details.
10 *
11 * Written by Miles Bader <miles@gnu.org>
12 */
13
14#ifndef __V850_ANNA_H__
15#define __V850_ANNA_H__
16
17#include <asm/v850e2.h> /* Based on V850E2 core. */
18
19
20#define CPU_MODEL "v850e2/anna"
21#define CPU_MODEL_LONG "NEC V850E2/Anna"
22#define PLATFORM "anna"
23#define PLATFORM_LONG "NEC/Midas lab V850E2/Anna evaluation board"
24
25#define CPU_CLOCK_FREQ 200000000 /* 200MHz */
26#define SYS_CLOCK_FREQ 33300000 /* 33.3MHz */
27
28
29/* 1MB of static RAM. This memory is mirrored 64 times. */
30#define SRAM_ADDR 0x04000000
31#define SRAM_SIZE 0x00100000 /* 1MB */
32/* 64MB of DRAM. */
33#define SDRAM_ADDR 0x08000000
34#define SDRAM_SIZE 0x04000000 /* 64MB */
35
36
37/* For <asm/page.h> */
38#define PAGE_OFFSET SRAM_ADDR
39
40/* We use on-chip RAM, for a few miscellaneous variables that must be
41 accessible using a load instruction relative to R0. The Anna chip has
42 128K of `dLB' ram nominally located at 0xFFF00000, but it's mirrored
43 every 128K, so we can use the `last mirror' (except for the portion at
44 the top which is overridden by I/O space). In addition, the early
45 sample chip we're using has lots of memory errors in the dLB ram, so we
46 use a specially chosen location that has at least 20 bytes of contiguous
47 valid memory (xxxF0020 - xxxF003F). */
48#define R0_RAM_ADDR 0xFFFF8020
49
50
51/* Anna specific control registers. */
52#define ANNA_ILBEN_ADDR 0xFFFFF7F2
53#define ANNA_ILBEN (*(volatile u16 *)ANNA_ILBEN_ADDR)
54
55
56/* I/O port P0-P3. */
57/* Direct I/O. Bits 0-7 are pins Pn0-Pn7. */
58#define ANNA_PORT_IO_ADDR(n) (0xFFFFF400 + (n) * 2)
59#define ANNA_PORT_IO(n) (*(volatile u8 *)ANNA_PORT_IO_ADDR(n))
60/* Port mode (for direct I/O, 0 = output, 1 = input). */
61#define ANNA_PORT_PM_ADDR(n) (0xFFFFF410 + (n) * 2)
62#define ANNA_PORT_PM(n) (*(volatile u8 *)ANNA_PORT_PM_ADDR(n))
63
64
65/* Hardware-specific interrupt numbers (in the kernel IRQ namespace). */
66#define IRQ_INTP(n) (n) /* Pnnn (pin) interrupts 0-15 */
67#define IRQ_INTP_NUM 16
68#define IRQ_INTOV(n) (0x10 + (n)) /* 0-2 */
69#define IRQ_INTOV_NUM 2
70#define IRQ_INTCCC(n) (0x12 + (n))
71#define IRQ_INTCCC_NUM 4
72#define IRQ_INTCMD(n) (0x16 + (n)) /* interval timer interrupts 0-5 */
73#define IRQ_INTCMD_NUM 6
74#define IRQ_INTDMA(n) (0x1C + (n)) /* DMA interrupts 0-3 */
75#define IRQ_INTDMA_NUM 4
76#define IRQ_INTDMXER 0x20
77#define IRQ_INTSRE(n) (0x21 + (n)*3) /* UART 0-1 reception error */
78#define IRQ_INTSRE_NUM 2
79#define IRQ_INTSR(n) (0x22 + (n)*3) /* UART 0-1 reception completion */
80#define IRQ_INTSR_NUM 2
81#define IRQ_INTST(n) (0x23 + (n)*3) /* UART 0-1 transmission completion */
82#define IRQ_INTST_NUM 2
83
84#define NUM_CPU_IRQS 64
85
86#ifndef __ASSEMBLY__
87/* Initialize chip interrupts. */
88extern void anna_init_irqs (void);
89#endif
90
91
92/* Anna UART details (basically the same as the V850E/MA1, but 2 channels). */
93#define V850E_UART_NUM_CHANNELS 2
94#define V850E_UART_BASE_FREQ (SYS_CLOCK_FREQ / 2)
95#define V850E_UART_CHIP_NAME "V850E2/NA85E2A"
96
97/* This is the UART channel that's actually connected on the board. */
98#define V850E_UART_CONSOLE_CHANNEL 1
99
100/* This is a function that gets called before configuring the UART. */
101#define V850E_UART_PRE_CONFIGURE anna_uart_pre_configure
102#ifndef __ASSEMBLY__
103extern void anna_uart_pre_configure (unsigned chan,
104 unsigned cflags, unsigned baud);
105#endif
106
107/* This board supports RTS/CTS for the on-chip UART, but only for channel 1. */
108
109/* CTS for UART channel 1 is pin P37 (bit 7 of port 3). */
110#define V850E_UART_CTS(chan) ((chan) == 1 ? !(ANNA_PORT_IO(3) & 0x80) : 1)
111/* RTS for UART channel 1 is pin P07 (bit 7 of port 0). */
112#define V850E_UART_SET_RTS(chan, val) \
113 do { \
114 if (chan == 1) { \
115 unsigned old = ANNA_PORT_IO(0); \
116 if (val) \
117 ANNA_PORT_IO(0) = old & ~0x80; \
118 else \
119 ANNA_PORT_IO(0) = old | 0x80; \
120 } \
121 } while (0)
122
123
124/* Timer C details. */
125#define V850E_TIMER_C_BASE_ADDR 0xFFFFF600
126
127/* Timer D details (the Anna actually has 5 of these; should change later). */
128#define V850E_TIMER_D_BASE_ADDR 0xFFFFF540
129#define V850E_TIMER_D_TMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x0)
130#define V850E_TIMER_D_CMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x2)
131#define V850E_TIMER_D_TMCD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x4)
132
133#define V850E_TIMER_D_BASE_FREQ SYS_CLOCK_FREQ
134#define V850E_TIMER_D_TMCD_CS_MIN 1 /* min 2^1 divider */
135
136
137#endif /* __V850_ANNA_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 22:54:57 -0500