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-rw-r--r--include/asm-sparc64/atomic.h8
-rw-r--r--include/asm-sparc64/bitops.h4
-rw-r--r--include/asm-sparc64/processor.h1
-rw-r--r--include/asm-sparc64/segment.h6
-rw-r--r--include/asm-sparc64/sfafsr.h82
-rw-r--r--include/asm-sparc64/socket.h2
-rw-r--r--include/asm-sparc64/spinlock.h42
-rw-r--r--include/asm-sparc64/system.h17
8 files changed, 125 insertions, 37 deletions
diff --git a/include/asm-sparc64/atomic.h b/include/asm-sparc64/atomic.h
index d80f3379669b..e175afcf2cde 100644
--- a/include/asm-sparc64/atomic.h
+++ b/include/asm-sparc64/atomic.h
@@ -72,10 +72,10 @@ extern int atomic64_sub_ret(int, atomic64_t *);
72 72
73/* Atomic operations are already serializing */ 73/* Atomic operations are already serializing */
74#ifdef CONFIG_SMP 74#ifdef CONFIG_SMP
75#define smp_mb__before_atomic_dec() membar("#StoreLoad | #LoadLoad") 75#define smp_mb__before_atomic_dec() membar_storeload_loadload();
76#define smp_mb__after_atomic_dec() membar("#StoreLoad | #StoreStore") 76#define smp_mb__after_atomic_dec() membar_storeload_storestore();
77#define smp_mb__before_atomic_inc() membar("#StoreLoad | #LoadLoad") 77#define smp_mb__before_atomic_inc() membar_storeload_loadload();
78#define smp_mb__after_atomic_inc() membar("#StoreLoad | #StoreStore") 78#define smp_mb__after_atomic_inc() membar_storeload_storestore();
79#else 79#else
80#define smp_mb__before_atomic_dec() barrier() 80#define smp_mb__before_atomic_dec() barrier()
81#define smp_mb__after_atomic_dec() barrier() 81#define smp_mb__after_atomic_dec() barrier()
diff --git a/include/asm-sparc64/bitops.h b/include/asm-sparc64/bitops.h
index 9c5e71970287..6388b8376c50 100644
--- a/include/asm-sparc64/bitops.h
+++ b/include/asm-sparc64/bitops.h
@@ -72,8 +72,8 @@ static inline int __test_and_change_bit(int nr, volatile unsigned long *addr)
72} 72}
73 73
74#ifdef CONFIG_SMP 74#ifdef CONFIG_SMP
75#define smp_mb__before_clear_bit() membar("#StoreLoad | #LoadLoad") 75#define smp_mb__before_clear_bit() membar_storeload_loadload()
76#define smp_mb__after_clear_bit() membar("#StoreLoad | #StoreStore") 76#define smp_mb__after_clear_bit() membar_storeload_storestore()
77#else 77#else
78#define smp_mb__before_clear_bit() barrier() 78#define smp_mb__before_clear_bit() barrier()
79#define smp_mb__after_clear_bit() barrier() 79#define smp_mb__after_clear_bit() barrier()
diff --git a/include/asm-sparc64/processor.h b/include/asm-sparc64/processor.h
index d0bee2413560..3169f3e2237e 100644
--- a/include/asm-sparc64/processor.h
+++ b/include/asm-sparc64/processor.h
@@ -18,7 +18,6 @@
18#include <asm/a.out.h> 18#include <asm/a.out.h>
19#include <asm/pstate.h> 19#include <asm/pstate.h>
20#include <asm/ptrace.h> 20#include <asm/ptrace.h>
21#include <asm/segment.h>
22#include <asm/page.h> 21#include <asm/page.h>
23 22
24/* The sparc has no problems with write protection */ 23/* The sparc has no problems with write protection */
diff --git a/include/asm-sparc64/segment.h b/include/asm-sparc64/segment.h
deleted file mode 100644
index b03e709fc945..000000000000
--- a/include/asm-sparc64/segment.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __SPARC64_SEGMENT_H
2#define __SPARC64_SEGMENT_H
3
4/* Only here because we have some old header files that expect it.. */
5
6#endif
diff --git a/include/asm-sparc64/sfafsr.h b/include/asm-sparc64/sfafsr.h
new file mode 100644
index 000000000000..2f792c20b53c
--- /dev/null
+++ b/include/asm-sparc64/sfafsr.h
@@ -0,0 +1,82 @@
1#ifndef _SPARC64_SFAFSR_H
2#define _SPARC64_SFAFSR_H
3
4#include <asm/const.h>
5
6/* Spitfire Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */
7
8#define SFAFSR_ME (_AC(1,UL) << SFAFSR_ME_SHIFT)
9#define SFAFSR_ME_SHIFT 32
10#define SFAFSR_PRIV (_AC(1,UL) << SFAFSR_PRIV_SHIFT)
11#define SFAFSR_PRIV_SHIFT 31
12#define SFAFSR_ISAP (_AC(1,UL) << SFAFSR_ISAP_SHIFT)
13#define SFAFSR_ISAP_SHIFT 30
14#define SFAFSR_ETP (_AC(1,UL) << SFAFSR_ETP_SHIFT)
15#define SFAFSR_ETP_SHIFT 29
16#define SFAFSR_IVUE (_AC(1,UL) << SFAFSR_IVUE_SHIFT)
17#define SFAFSR_IVUE_SHIFT 28
18#define SFAFSR_TO (_AC(1,UL) << SFAFSR_TO_SHIFT)
19#define SFAFSR_TO_SHIFT 27
20#define SFAFSR_BERR (_AC(1,UL) << SFAFSR_BERR_SHIFT)
21#define SFAFSR_BERR_SHIFT 26
22#define SFAFSR_LDP (_AC(1,UL) << SFAFSR_LDP_SHIFT)
23#define SFAFSR_LDP_SHIFT 25
24#define SFAFSR_CP (_AC(1,UL) << SFAFSR_CP_SHIFT)
25#define SFAFSR_CP_SHIFT 24
26#define SFAFSR_WP (_AC(1,UL) << SFAFSR_WP_SHIFT)
27#define SFAFSR_WP_SHIFT 23
28#define SFAFSR_EDP (_AC(1,UL) << SFAFSR_EDP_SHIFT)
29#define SFAFSR_EDP_SHIFT 22
30#define SFAFSR_UE (_AC(1,UL) << SFAFSR_UE_SHIFT)
31#define SFAFSR_UE_SHIFT 21
32#define SFAFSR_CE (_AC(1,UL) << SFAFSR_CE_SHIFT)
33#define SFAFSR_CE_SHIFT 20
34#define SFAFSR_ETS (_AC(0xf,UL) << SFAFSR_ETS_SHIFT)
35#define SFAFSR_ETS_SHIFT 16
36#define SFAFSR_PSYND (_AC(0xffff,UL) << SFAFSR_PSYND_SHIFT)
37#define SFAFSR_PSYND_SHIFT 0
38
39/* UDB Error Register, ASI=0x7f VA<63:0>=0x0(High),0x18(Low) for read
40 * ASI=0x77 VA<63:0>=0x0(High),0x18(Low) for write
41 */
42
43#define UDBE_UE (_AC(1,UL) << 9)
44#define UDBE_CE (_AC(1,UL) << 8)
45#define UDBE_E_SYNDR (_AC(0xff,UL) << 0)
46
47/* The trap handlers for asynchronous errors encode the AFSR and
48 * other pieces of information into a 64-bit argument for C code
49 * encoded as follows:
50 *
51 * -----------------------------------------------
52 * | UDB_H | UDB_L | TL>1 | TT | AFSR |
53 * -----------------------------------------------
54 * 63 54 53 44 42 41 33 32 0
55 *
56 * The AFAR is passed in unchanged.
57 */
58#define SFSTAT_UDBH_MASK (_AC(0x3ff,UL) << SFSTAT_UDBH_SHIFT)
59#define SFSTAT_UDBH_SHIFT 54
60#define SFSTAT_UDBL_MASK (_AC(0x3ff,UL) << SFSTAT_UDBH_SHIFT)
61#define SFSTAT_UDBL_SHIFT 44
62#define SFSTAT_TL_GT_ONE (_AC(1,UL) << SFSTAT_TL_GT_ONE_SHIFT)
63#define SFSTAT_TL_GT_ONE_SHIFT 42
64#define SFSTAT_TRAP_TYPE (_AC(0x1FF,UL) << SFSTAT_TRAP_TYPE_SHIFT)
65#define SFSTAT_TRAP_TYPE_SHIFT 33
66#define SFSTAT_AFSR_MASK (_AC(0x1ffffffff,UL) << SFSTAT_AFSR_SHIFT)
67#define SFSTAT_AFSR_SHIFT 0
68
69/* ESTATE Error Enable Register, ASI=0x4b VA<63:0>=0x0 */
70#define ESTATE_ERR_CE 0x1 /* Correctable errors */
71#define ESTATE_ERR_NCE 0x2 /* TO, BERR, LDP, ETP, EDP, WP, UE, IVUE */
72#define ESTATE_ERR_ISAP 0x4 /* System address parity error */
73#define ESTATE_ERR_ALL (ESTATE_ERR_CE | \
74 ESTATE_ERR_NCE | \
75 ESTATE_ERR_ISAP)
76
77/* The various trap types that report using the above state. */
78#define TRAP_TYPE_IAE 0x09 /* Instruction Access Error */
79#define TRAP_TYPE_DAE 0x32 /* Data Access Error */
80#define TRAP_TYPE_CEE 0x63 /* Correctable ECC Error */
81
82#endif /* _SPARC64_SFAFSR_H */
diff --git a/include/asm-sparc64/socket.h b/include/asm-sparc64/socket.h
index 865547a23908..59987dad3359 100644
--- a/include/asm-sparc64/socket.h
+++ b/include/asm-sparc64/socket.h
@@ -29,6 +29,8 @@
29 29
30#define SO_SNDBUF 0x1001 30#define SO_SNDBUF 0x1001
31#define SO_RCVBUF 0x1002 31#define SO_RCVBUF 0x1002
32#define SO_SNDBUFFORCE 0x100a
33#define SO_RCVBUFFORCE 0x100b
32#define SO_ERROR 0x1007 34#define SO_ERROR 0x1007
33#define SO_TYPE 0x1008 35#define SO_TYPE 0x1008
34 36
diff --git a/include/asm-sparc64/spinlock.h b/include/asm-sparc64/spinlock.h
index 9cb93a5c2b4f..a02c4370eb42 100644
--- a/include/asm-sparc64/spinlock.h
+++ b/include/asm-sparc64/spinlock.h
@@ -43,7 +43,7 @@ typedef struct {
43#define spin_is_locked(lp) ((lp)->lock != 0) 43#define spin_is_locked(lp) ((lp)->lock != 0)
44 44
45#define spin_unlock_wait(lp) \ 45#define spin_unlock_wait(lp) \
46do { membar("#LoadLoad"); \ 46do { rmb(); \
47} while((lp)->lock) 47} while((lp)->lock)
48 48
49static inline void _raw_spin_lock(spinlock_t *lock) 49static inline void _raw_spin_lock(spinlock_t *lock)
@@ -129,15 +129,18 @@ typedef struct {
129#define spin_is_locked(__lock) ((__lock)->lock != 0) 129#define spin_is_locked(__lock) ((__lock)->lock != 0)
130#define spin_unlock_wait(__lock) \ 130#define spin_unlock_wait(__lock) \
131do { \ 131do { \
132 membar("#LoadLoad"); \ 132 rmb(); \
133} while((__lock)->lock) 133} while((__lock)->lock)
134 134
135extern void _do_spin_lock (spinlock_t *lock, char *str); 135extern void _do_spin_lock(spinlock_t *lock, char *str, unsigned long caller);
136extern void _do_spin_unlock (spinlock_t *lock); 136extern void _do_spin_unlock(spinlock_t *lock);
137extern int _do_spin_trylock (spinlock_t *lock); 137extern int _do_spin_trylock(spinlock_t *lock, unsigned long caller);
138 138
139#define _raw_spin_trylock(lp) _do_spin_trylock(lp) 139#define _raw_spin_trylock(lp) \
140#define _raw_spin_lock(lock) _do_spin_lock(lock, "spin_lock") 140 _do_spin_trylock(lp, (unsigned long) __builtin_return_address(0))
141#define _raw_spin_lock(lock) \
142 _do_spin_lock(lock, "spin_lock", \
143 (unsigned long) __builtin_return_address(0))
141#define _raw_spin_unlock(lock) _do_spin_unlock(lock) 144#define _raw_spin_unlock(lock) _do_spin_unlock(lock)
142#define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock) 145#define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
143 146
@@ -279,37 +282,41 @@ typedef struct {
279#define RW_LOCK_UNLOCKED (rwlock_t) { 0, 0, 0xff, { } } 282#define RW_LOCK_UNLOCKED (rwlock_t) { 0, 0, 0xff, { } }
280#define rwlock_init(lp) do { *(lp) = RW_LOCK_UNLOCKED; } while(0) 283#define rwlock_init(lp) do { *(lp) = RW_LOCK_UNLOCKED; } while(0)
281 284
282extern void _do_read_lock(rwlock_t *rw, char *str); 285extern void _do_read_lock(rwlock_t *rw, char *str, unsigned long caller);
283extern void _do_read_unlock(rwlock_t *rw, char *str); 286extern void _do_read_unlock(rwlock_t *rw, char *str, unsigned long caller);
284extern void _do_write_lock(rwlock_t *rw, char *str); 287extern void _do_write_lock(rwlock_t *rw, char *str, unsigned long caller);
285extern void _do_write_unlock(rwlock_t *rw); 288extern void _do_write_unlock(rwlock_t *rw, unsigned long caller);
286extern int _do_write_trylock(rwlock_t *rw, char *str); 289extern int _do_write_trylock(rwlock_t *rw, char *str, unsigned long caller);
287 290
288#define _raw_read_lock(lock) \ 291#define _raw_read_lock(lock) \
289do { unsigned long flags; \ 292do { unsigned long flags; \
290 local_irq_save(flags); \ 293 local_irq_save(flags); \
291 _do_read_lock(lock, "read_lock"); \ 294 _do_read_lock(lock, "read_lock", \
295 (unsigned long) __builtin_return_address(0)); \
292 local_irq_restore(flags); \ 296 local_irq_restore(flags); \
293} while(0) 297} while(0)
294 298
295#define _raw_read_unlock(lock) \ 299#define _raw_read_unlock(lock) \
296do { unsigned long flags; \ 300do { unsigned long flags; \
297 local_irq_save(flags); \ 301 local_irq_save(flags); \
298 _do_read_unlock(lock, "read_unlock"); \ 302 _do_read_unlock(lock, "read_unlock", \
303 (unsigned long) __builtin_return_address(0)); \
299 local_irq_restore(flags); \ 304 local_irq_restore(flags); \
300} while(0) 305} while(0)
301 306
302#define _raw_write_lock(lock) \ 307#define _raw_write_lock(lock) \
303do { unsigned long flags; \ 308do { unsigned long flags; \
304 local_irq_save(flags); \ 309 local_irq_save(flags); \
305 _do_write_lock(lock, "write_lock"); \ 310 _do_write_lock(lock, "write_lock", \
311 (unsigned long) __builtin_return_address(0)); \
306 local_irq_restore(flags); \ 312 local_irq_restore(flags); \
307} while(0) 313} while(0)
308 314
309#define _raw_write_unlock(lock) \ 315#define _raw_write_unlock(lock) \
310do { unsigned long flags; \ 316do { unsigned long flags; \
311 local_irq_save(flags); \ 317 local_irq_save(flags); \
312 _do_write_unlock(lock); \ 318 _do_write_unlock(lock, \
319 (unsigned long) __builtin_return_address(0)); \
313 local_irq_restore(flags); \ 320 local_irq_restore(flags); \
314} while(0) 321} while(0)
315 322
@@ -317,7 +324,8 @@ do { unsigned long flags; \
317({ unsigned long flags; \ 324({ unsigned long flags; \
318 int val; \ 325 int val; \
319 local_irq_save(flags); \ 326 local_irq_save(flags); \
320 val = _do_write_trylock(lock, "write_trylock"); \ 327 val = _do_write_trylock(lock, "write_trylock", \
328 (unsigned long) __builtin_return_address(0)); \
321 local_irq_restore(flags); \ 329 local_irq_restore(flags); \
322 val; \ 330 val; \
323}) 331})
diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h
index ee4bdfc6b88f..5e94c05dc2fc 100644
--- a/include/asm-sparc64/system.h
+++ b/include/asm-sparc64/system.h
@@ -28,6 +28,14 @@ enum sparc_cpu {
28#define ARCH_SUN4C_SUN4 0 28#define ARCH_SUN4C_SUN4 0
29#define ARCH_SUN4 0 29#define ARCH_SUN4 0
30 30
31extern void mb(void);
32extern void rmb(void);
33extern void wmb(void);
34extern void membar_storeload(void);
35extern void membar_storeload_storestore(void);
36extern void membar_storeload_loadload(void);
37extern void membar_storestore_loadstore(void);
38
31#endif 39#endif
32 40
33#define setipl(__new_ipl) \ 41#define setipl(__new_ipl) \
@@ -78,16 +86,11 @@ enum sparc_cpu {
78 86
79#define nop() __asm__ __volatile__ ("nop") 87#define nop() __asm__ __volatile__ ("nop")
80 88
81#define membar(type) __asm__ __volatile__ ("membar " type : : : "memory")
82#define mb() \
83 membar("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
84#define rmb() membar("#LoadLoad")
85#define wmb() membar("#StoreStore")
86#define read_barrier_depends() do { } while(0) 89#define read_barrier_depends() do { } while(0)
87#define set_mb(__var, __value) \ 90#define set_mb(__var, __value) \
88 do { __var = __value; membar("#StoreLoad | #StoreStore"); } while(0) 91 do { __var = __value; membar_storeload_storestore(); } while(0)
89#define set_wmb(__var, __value) \ 92#define set_wmb(__var, __value) \
90 do { __var = __value; membar("#StoreStore"); } while(0) 93 do { __var = __value; wmb(); } while(0)
91 94
92#ifdef CONFIG_SMP 95#ifdef CONFIG_SMP
93#define smp_mb() mb() 96#define smp_mb() mb()
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