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-rw-r--r--include/asm-sparc64/cpudata.h8
-rw-r--r--include/asm-sparc64/tsb.h11
2 files changed, 17 insertions, 2 deletions
diff --git a/include/asm-sparc64/cpudata.h b/include/asm-sparc64/cpudata.h
index 998145b92653..a3dc4afc4b21 100644
--- a/include/asm-sparc64/cpudata.h
+++ b/include/asm-sparc64/cpudata.h
@@ -6,6 +6,8 @@
6#ifndef _SPARC64_CPUDATA_H 6#ifndef _SPARC64_CPUDATA_H
7#define _SPARC64_CPUDATA_H 7#define _SPARC64_CPUDATA_H
8 8
9#include <asm/hypervisor.h>
10
9#ifndef __ASSEMBLY__ 11#ifndef __ASSEMBLY__
10 12
11#include <linux/percpu.h> 13#include <linux/percpu.h>
@@ -57,6 +59,9 @@ struct trap_per_cpu {
57 59
58/* D-cache line 2 */ 60/* D-cache line 2 */
59 unsigned long __pad2[4]; 61 unsigned long __pad2[4];
62
63/* Dcache lines 3 and 4 */
64 struct hv_fault_status fault_info;
60} __attribute__((aligned(64))); 65} __attribute__((aligned(64)));
61extern struct trap_per_cpu trap_block[NR_CPUS]; 66extern struct trap_per_cpu trap_block[NR_CPUS];
62extern void init_cur_cpu_trap(void); 67extern void init_cur_cpu_trap(void);
@@ -88,8 +93,9 @@ extern struct gl_2insn_patch_entry __gl_2insn_patch, __gl_2insn_patch_end;
88 93
89#define TRAP_PER_CPU_THREAD 0x00 94#define TRAP_PER_CPU_THREAD 0x00
90#define TRAP_PER_CPU_PGD_PADDR 0x08 95#define TRAP_PER_CPU_PGD_PADDR 0x08
96#define TRAP_PER_CPU_FAULT_INFO 0x20
91 97
92#define TRAP_BLOCK_SZ_SHIFT 6 98#define TRAP_BLOCK_SZ_SHIFT 7
93 99
94#include <asm/scratchpad.h> 100#include <asm/scratchpad.h>
95 101
diff --git a/include/asm-sparc64/tsb.h b/include/asm-sparc64/tsb.h
index 44709cde5617..7f3abc32c4dd 100644
--- a/include/asm-sparc64/tsb.h
+++ b/include/asm-sparc64/tsb.h
@@ -53,6 +53,14 @@
53 * kernel image, so we don't play these games for swapper_tsb access. 53 * kernel image, so we don't play these games for swapper_tsb access.
54 */ 54 */
55#ifndef __ASSEMBLY__ 55#ifndef __ASSEMBLY__
56struct tsb_ldquad_phys_patch_entry {
57 unsigned int addr;
58 unsigned int sun4u_insn;
59 unsigned int sun4v_insn;
60};
61extern struct tsb_ldquad_phys_patch_entry __tsb_ldquad_phys_patch,
62 __tsb_ldquad_phys_patch_end;
63
56struct tsb_phys_patch_entry { 64struct tsb_phys_patch_entry {
57 unsigned int addr; 65 unsigned int addr;
58 unsigned int insn; 66 unsigned int insn;
@@ -61,9 +69,10 @@ extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
61#endif 69#endif
62#define TSB_LOAD_QUAD(TSB, REG) \ 70#define TSB_LOAD_QUAD(TSB, REG) \
63661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \ 71661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
64 .section .tsb_phys_patch, "ax"; \ 72 .section .tsb_ldquad_phys_patch, "ax"; \
65 .word 661b; \ 73 .word 661b; \
66 ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \ 74 ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
75 ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
67 .previous 76 .previous
68 77
69#define TSB_LOAD_TAG_HIGH(TSB, REG) \ 78#define TSB_LOAD_TAG_HIGH(TSB, REG) \