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Diffstat (limited to 'include/asm-sparc64/spitfire.h')
-rw-r--r--include/asm-sparc64/spitfire.h53
1 files changed, 26 insertions, 27 deletions
diff --git a/include/asm-sparc64/spitfire.h b/include/asm-sparc64/spitfire.h
index cf7807813e85..63b7040e8134 100644
--- a/include/asm-sparc64/spitfire.h
+++ b/include/asm-sparc64/spitfire.h
@@ -1,7 +1,6 @@
1/* $Id: spitfire.h,v 1.18 2001/11/29 16:42:10 kanoj Exp $ 1/* spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
2 * spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
3 * 2 *
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) 3 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
5 */ 4 */
6 5
7#ifndef _SPARC64_SPITFIRE_H 6#ifndef _SPARC64_SPITFIRE_H
@@ -67,7 +66,7 @@ extern void cheetah_enable_pcache(void);
67/* The data cache is write through, so this just invalidates the 66/* The data cache is write through, so this just invalidates the
68 * specified line. 67 * specified line.
69 */ 68 */
70static __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag) 69static inline void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
71{ 70{
72 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 71 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
73 "membar #Sync" 72 "membar #Sync"
@@ -81,7 +80,7 @@ static __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long
81 * a flush instruction (to any address) is sufficient to handle 80 * a flush instruction (to any address) is sufficient to handle
82 * this issue after the line is invalidated. 81 * this issue after the line is invalidated.
83 */ 82 */
84static __inline__ void spitfire_put_icache_tag(unsigned long addr, unsigned long tag) 83static inline void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
85{ 84{
86 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 85 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
87 "membar #Sync" 86 "membar #Sync"
@@ -89,7 +88,7 @@ static __inline__ void spitfire_put_icache_tag(unsigned long addr, unsigned long
89 : "r" (tag), "r" (addr), "i" (ASI_IC_TAG)); 88 : "r" (tag), "r" (addr), "i" (ASI_IC_TAG));
90} 89}
91 90
92static __inline__ unsigned long spitfire_get_dtlb_data(int entry) 91static inline unsigned long spitfire_get_dtlb_data(int entry)
93{ 92{
94 unsigned long data; 93 unsigned long data;
95 94
@@ -103,7 +102,7 @@ static __inline__ unsigned long spitfire_get_dtlb_data(int entry)
103 return data; 102 return data;
104} 103}
105 104
106static __inline__ unsigned long spitfire_get_dtlb_tag(int entry) 105static inline unsigned long spitfire_get_dtlb_tag(int entry)
107{ 106{
108 unsigned long tag; 107 unsigned long tag;
109 108
@@ -113,7 +112,7 @@ static __inline__ unsigned long spitfire_get_dtlb_tag(int entry)
113 return tag; 112 return tag;
114} 113}
115 114
116static __inline__ void spitfire_put_dtlb_data(int entry, unsigned long data) 115static inline void spitfire_put_dtlb_data(int entry, unsigned long data)
117{ 116{
118 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 117 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
119 "membar #Sync" 118 "membar #Sync"
@@ -122,7 +121,7 @@ static __inline__ void spitfire_put_dtlb_data(int entry, unsigned long data)
122 "i" (ASI_DTLB_DATA_ACCESS)); 121 "i" (ASI_DTLB_DATA_ACCESS));
123} 122}
124 123
125static __inline__ unsigned long spitfire_get_itlb_data(int entry) 124static inline unsigned long spitfire_get_itlb_data(int entry)
126{ 125{
127 unsigned long data; 126 unsigned long data;
128 127
@@ -136,7 +135,7 @@ static __inline__ unsigned long spitfire_get_itlb_data(int entry)
136 return data; 135 return data;
137} 136}
138 137
139static __inline__ unsigned long spitfire_get_itlb_tag(int entry) 138static inline unsigned long spitfire_get_itlb_tag(int entry)
140{ 139{
141 unsigned long tag; 140 unsigned long tag;
142 141
@@ -146,7 +145,7 @@ static __inline__ unsigned long spitfire_get_itlb_tag(int entry)
146 return tag; 145 return tag;
147} 146}
148 147
149static __inline__ void spitfire_put_itlb_data(int entry, unsigned long data) 148static inline void spitfire_put_itlb_data(int entry, unsigned long data)
150{ 149{
151 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 150 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
152 "membar #Sync" 151 "membar #Sync"
@@ -155,7 +154,7 @@ static __inline__ void spitfire_put_itlb_data(int entry, unsigned long data)
155 "i" (ASI_ITLB_DATA_ACCESS)); 154 "i" (ASI_ITLB_DATA_ACCESS));
156} 155}
157 156
158static __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page) 157static inline void spitfire_flush_dtlb_nucleus_page(unsigned long page)
159{ 158{
160 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 159 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
161 "membar #Sync" 160 "membar #Sync"
@@ -163,7 +162,7 @@ static __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page)
163 : "r" (page | 0x20), "i" (ASI_DMMU_DEMAP)); 162 : "r" (page | 0x20), "i" (ASI_DMMU_DEMAP));
164} 163}
165 164
166static __inline__ void spitfire_flush_itlb_nucleus_page(unsigned long page) 165static inline void spitfire_flush_itlb_nucleus_page(unsigned long page)
167{ 166{
168 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 167 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
169 "membar #Sync" 168 "membar #Sync"
@@ -172,7 +171,7 @@ static __inline__ void spitfire_flush_itlb_nucleus_page(unsigned long page)
172} 171}
173 172
174/* Cheetah has "all non-locked" tlb flushes. */ 173/* Cheetah has "all non-locked" tlb flushes. */
175static __inline__ void cheetah_flush_dtlb_all(void) 174static inline void cheetah_flush_dtlb_all(void)
176{ 175{
177 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 176 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
178 "membar #Sync" 177 "membar #Sync"
@@ -180,7 +179,7 @@ static __inline__ void cheetah_flush_dtlb_all(void)
180 : "r" (0x80), "i" (ASI_DMMU_DEMAP)); 179 : "r" (0x80), "i" (ASI_DMMU_DEMAP));
181} 180}
182 181
183static __inline__ void cheetah_flush_itlb_all(void) 182static inline void cheetah_flush_itlb_all(void)
184{ 183{
185 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 184 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
186 "membar #Sync" 185 "membar #Sync"
@@ -202,7 +201,7 @@ static __inline__ void cheetah_flush_itlb_all(void)
202 * ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes 201 * ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes
203 * the problem for me. -DaveM 202 * the problem for me. -DaveM
204 */ 203 */
205static __inline__ unsigned long cheetah_get_ldtlb_data(int entry) 204static inline unsigned long cheetah_get_ldtlb_data(int entry)
206{ 205{
207 unsigned long data; 206 unsigned long data;
208 207
@@ -215,7 +214,7 @@ static __inline__ unsigned long cheetah_get_ldtlb_data(int entry)
215 return data; 214 return data;
216} 215}
217 216
218static __inline__ unsigned long cheetah_get_litlb_data(int entry) 217static inline unsigned long cheetah_get_litlb_data(int entry)
219{ 218{
220 unsigned long data; 219 unsigned long data;
221 220
@@ -228,7 +227,7 @@ static __inline__ unsigned long cheetah_get_litlb_data(int entry)
228 return data; 227 return data;
229} 228}
230 229
231static __inline__ unsigned long cheetah_get_ldtlb_tag(int entry) 230static inline unsigned long cheetah_get_ldtlb_tag(int entry)
232{ 231{
233 unsigned long tag; 232 unsigned long tag;
234 233
@@ -240,7 +239,7 @@ static __inline__ unsigned long cheetah_get_ldtlb_tag(int entry)
240 return tag; 239 return tag;
241} 240}
242 241
243static __inline__ unsigned long cheetah_get_litlb_tag(int entry) 242static inline unsigned long cheetah_get_litlb_tag(int entry)
244{ 243{
245 unsigned long tag; 244 unsigned long tag;
246 245
@@ -252,7 +251,7 @@ static __inline__ unsigned long cheetah_get_litlb_tag(int entry)
252 return tag; 251 return tag;
253} 252}
254 253
255static __inline__ void cheetah_put_ldtlb_data(int entry, unsigned long data) 254static inline void cheetah_put_ldtlb_data(int entry, unsigned long data)
256{ 255{
257 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 256 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
258 "membar #Sync" 257 "membar #Sync"
@@ -262,7 +261,7 @@ static __inline__ void cheetah_put_ldtlb_data(int entry, unsigned long data)
262 "i" (ASI_DTLB_DATA_ACCESS)); 261 "i" (ASI_DTLB_DATA_ACCESS));
263} 262}
264 263
265static __inline__ void cheetah_put_litlb_data(int entry, unsigned long data) 264static inline void cheetah_put_litlb_data(int entry, unsigned long data)
266{ 265{
267 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 266 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
268 "membar #Sync" 267 "membar #Sync"
@@ -272,7 +271,7 @@ static __inline__ void cheetah_put_litlb_data(int entry, unsigned long data)
272 "i" (ASI_ITLB_DATA_ACCESS)); 271 "i" (ASI_ITLB_DATA_ACCESS));
273} 272}
274 273
275static __inline__ unsigned long cheetah_get_dtlb_data(int entry, int tlb) 274static inline unsigned long cheetah_get_dtlb_data(int entry, int tlb)
276{ 275{
277 unsigned long data; 276 unsigned long data;
278 277
@@ -284,7 +283,7 @@ static __inline__ unsigned long cheetah_get_dtlb_data(int entry, int tlb)
284 return data; 283 return data;
285} 284}
286 285
287static __inline__ unsigned long cheetah_get_dtlb_tag(int entry, int tlb) 286static inline unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
288{ 287{
289 unsigned long tag; 288 unsigned long tag;
290 289
@@ -294,7 +293,7 @@ static __inline__ unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
294 return tag; 293 return tag;
295} 294}
296 295
297static __inline__ void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb) 296static inline void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb)
298{ 297{
299 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 298 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
300 "membar #Sync" 299 "membar #Sync"
@@ -304,7 +303,7 @@ static __inline__ void cheetah_put_dtlb_data(int entry, unsigned long data, int
304 "i" (ASI_DTLB_DATA_ACCESS)); 303 "i" (ASI_DTLB_DATA_ACCESS));
305} 304}
306 305
307static __inline__ unsigned long cheetah_get_itlb_data(int entry) 306static inline unsigned long cheetah_get_itlb_data(int entry)
308{ 307{
309 unsigned long data; 308 unsigned long data;
310 309
@@ -317,7 +316,7 @@ static __inline__ unsigned long cheetah_get_itlb_data(int entry)
317 return data; 316 return data;
318} 317}
319 318
320static __inline__ unsigned long cheetah_get_itlb_tag(int entry) 319static inline unsigned long cheetah_get_itlb_tag(int entry)
321{ 320{
322 unsigned long tag; 321 unsigned long tag;
323 322
@@ -327,7 +326,7 @@ static __inline__ unsigned long cheetah_get_itlb_tag(int entry)
327 return tag; 326 return tag;
328} 327}
329 328
330static __inline__ void cheetah_put_itlb_data(int entry, unsigned long data) 329static inline void cheetah_put_itlb_data(int entry, unsigned long data)
331{ 330{
332 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 331 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
333 "membar #Sync" 332 "membar #Sync"
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 21:09:53 -0500