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-rw-r--r--include/asm-sparc64/pgtable.h704
1 files changed, 516 insertions, 188 deletions
diff --git a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h
index f0a9b44d3eb5..ed4124edf837 100644
--- a/include/asm-sparc64/pgtable.h
+++ b/include/asm-sparc64/pgtable.h
@@ -25,7 +25,8 @@
25#include <asm/const.h> 25#include <asm/const.h>
26 26
27/* The kernel image occupies 0x4000000 to 0x1000000 (4MB --> 32MB). 27/* The kernel image occupies 0x4000000 to 0x1000000 (4MB --> 32MB).
28 * The page copy blockops can use 0x2000000 to 0x10000000. 28 * The page copy blockops can use 0x2000000 to 0x4000000.
29 * The TSB is mapped in the 0x4000000 to 0x6000000 range.
29 * The PROM resides in an area spanning 0xf0000000 to 0x100000000. 30 * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
30 * The vmalloc area spans 0x100000000 to 0x200000000. 31 * The vmalloc area spans 0x100000000 to 0x200000000.
31 * Since modules need to be in the lowest 32-bits of the address space, 32 * Since modules need to be in the lowest 32-bits of the address space,
@@ -34,6 +35,7 @@
34 * 0x400000000. 35 * 0x400000000.
35 */ 36 */
36#define TLBTEMP_BASE _AC(0x0000000002000000,UL) 37#define TLBTEMP_BASE _AC(0x0000000002000000,UL)
38#define TSBMAP_BASE _AC(0x0000000004000000,UL)
37#define MODULES_VADDR _AC(0x0000000010000000,UL) 39#define MODULES_VADDR _AC(0x0000000010000000,UL)
38#define MODULES_LEN _AC(0x00000000e0000000,UL) 40#define MODULES_LEN _AC(0x00000000e0000000,UL)
39#define MODULES_END _AC(0x00000000f0000000,UL) 41#define MODULES_END _AC(0x00000000f0000000,UL)
@@ -88,162 +90,538 @@
88 90
89#endif /* !(__ASSEMBLY__) */ 91#endif /* !(__ASSEMBLY__) */
90 92
91/* Spitfire/Cheetah TTE bits. */ 93/* PTE bits which are the same in SUN4U and SUN4V format. */
92#define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */ 94#define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */
93#define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit up to date*/ 95#define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/
94#define _PAGE_SZ4MB _AC(0x6000000000000000,UL) /* 4MB Page */ 96
95#define _PAGE_SZ512K _AC(0x4000000000000000,UL) /* 512K Page */ 97/* SUN4U pte bits... */
96#define _PAGE_SZ64K _AC(0x2000000000000000,UL) /* 64K Page */ 98#define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */
97#define _PAGE_SZ8K _AC(0x0000000000000000,UL) /* 8K Page */ 99#define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */
98#define _PAGE_NFO _AC(0x1000000000000000,UL) /* No Fault Only */ 100#define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */
99#define _PAGE_IE _AC(0x0800000000000000,UL) /* Invert Endianness */ 101#define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */
100#define _PAGE_SOFT2 _AC(0x07FC000000000000,UL) /* Software bits, set 2 */ 102#define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */
101#define _PAGE_RES1 _AC(0x0002000000000000,UL) /* Reserved */ 103#define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */
102#define _PAGE_SZ32MB _AC(0x0001000000000000,UL) /* (Panther) 32MB page */ 104#define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
103#define _PAGE_SZ256MB _AC(0x2001000000000000,UL) /* (Panther) 256MB page */ 105#define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */
104#define _PAGE_SN _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */ 106#define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */
105#define _PAGE_RES2 _AC(0x0000780000000000,UL) /* Reserved */ 107#define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
106#define _PAGE_PADDR_SF _AC(0x000001FFFFFFE000,UL) /* (Spitfire) paddr[40:13]*/ 108#define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */
107#define _PAGE_PADDR _AC(0x000007FFFFFFE000,UL) /* (Cheetah) paddr[42:13] */ 109#define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */
108#define _PAGE_SOFT _AC(0x0000000000001F80,UL) /* Software bits */ 110#define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */
109#define _PAGE_L _AC(0x0000000000000040,UL) /* Locked TTE */ 111#define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */
110#define _PAGE_CP _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */ 112#define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */
111#define _PAGE_CV _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */ 113#define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */
112#define _PAGE_E _AC(0x0000000000000008,UL) /* side-Effect */ 114#define _PAGE_FILE_4U _AC(0x0000000000000800,UL) /* Pagecache page */
113#define _PAGE_P _AC(0x0000000000000004,UL) /* Privileged Page */ 115#define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */
114#define _PAGE_W _AC(0x0000000000000002,UL) /* Writable */ 116#define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */
115#define _PAGE_G _AC(0x0000000000000001,UL) /* Global */ 117#define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */
116 118#define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */
117/* Here are the SpitFire software bits we use in the TTE's. 119#define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */
118 * 120#define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
119 * WARNING: If you are going to try and start using some 121#define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
120 * of the soft2 bits, you will need to make 122#define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */
121 * modifications to the swap entry implementation. 123#define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */
122 * For example, one thing that could happen is that 124#define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */
123 * swp_entry_to_pte() would BUG_ON() if you tried 125
124 * to use one of the soft2 bits for _PAGE_FILE. 126/* SUN4V pte bits... */
125 * 127#define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */
126 * Like other architectures, I have aliased _PAGE_FILE with 128#define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */
127 * _PAGE_MODIFIED. This works because _PAGE_FILE is never 129#define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */
128 * interpreted that way unless _PAGE_PRESENT is clear. 130#define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */
129 */ 131#define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */
130#define _PAGE_EXEC _AC(0x0000000000001000,UL) /* Executable SW bit */ 132#define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */
131#define _PAGE_MODIFIED _AC(0x0000000000000800,UL) /* Modified (dirty) */ 133#define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */
132#define _PAGE_FILE _AC(0x0000000000000800,UL) /* Pagecache page */ 134#define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */
133#define _PAGE_ACCESSED _AC(0x0000000000000400,UL) /* Accessed (ref'd) */ 135#define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */
134#define _PAGE_READ _AC(0x0000000000000200,UL) /* Readable SW Bit */ 136#define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */
135#define _PAGE_WRITE _AC(0x0000000000000100,UL) /* Writable SW Bit */ 137#define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */
136#define _PAGE_PRESENT _AC(0x0000000000000080,UL) /* Present */ 138#define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */
139#define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */
140#define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */
141#define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */
142#define _PAGE_FILE_4V _AC(0x0000000000000020,UL) /* Pagecache page */
143#define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */
144#define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */
145#define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */
146#define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */
147#define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */
148#define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */
149#define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */
150#define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */
151#define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */
152#define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */
137 153
138#if PAGE_SHIFT == 13 154#if PAGE_SHIFT == 13
139#define _PAGE_SZBITS _PAGE_SZ8K 155#define _PAGE_SZBITS_4U _PAGE_SZ8K_4U
156#define _PAGE_SZBITS_4V _PAGE_SZ8K_4V
140#elif PAGE_SHIFT == 16 157#elif PAGE_SHIFT == 16
141#define _PAGE_SZBITS _PAGE_SZ64K 158#define _PAGE_SZBITS_4U _PAGE_SZ64K_4U
159#define _PAGE_SZBITS_4V _PAGE_SZ64K_4V
142#elif PAGE_SHIFT == 19 160#elif PAGE_SHIFT == 19
143#define _PAGE_SZBITS _PAGE_SZ512K 161#define _PAGE_SZBITS_4U _PAGE_SZ512K_4U
162#define _PAGE_SZBITS_4V _PAGE_SZ512K_4V
144#elif PAGE_SHIFT == 22 163#elif PAGE_SHIFT == 22
145#define _PAGE_SZBITS _PAGE_SZ4MB 164#define _PAGE_SZBITS_4U _PAGE_SZ4MB_4U
165#define _PAGE_SZBITS_4V _PAGE_SZ4MB_4V
146#else 166#else
147#error Wrong PAGE_SHIFT specified 167#error Wrong PAGE_SHIFT specified
148#endif 168#endif
149 169
150#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB) 170#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
151#define _PAGE_SZHUGE _PAGE_SZ4MB 171#define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U
172#define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V
152#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K) 173#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
153#define _PAGE_SZHUGE _PAGE_SZ512K 174#define _PAGE_SZHUGE_4U _PAGE_SZ512K_4U
175#define _PAGE_SZHUGE_4V _PAGE_SZ512K_4V
154#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K) 176#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
155#define _PAGE_SZHUGE _PAGE_SZ64K 177#define _PAGE_SZHUGE_4U _PAGE_SZ64K_4U
178#define _PAGE_SZHUGE_4V _PAGE_SZ64K_4V
156#endif 179#endif
157 180
158#define _PAGE_CACHE (_PAGE_CP | _PAGE_CV) 181/* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
182#define __P000 __pgprot(0)
183#define __P001 __pgprot(0)
184#define __P010 __pgprot(0)
185#define __P011 __pgprot(0)
186#define __P100 __pgprot(0)
187#define __P101 __pgprot(0)
188#define __P110 __pgprot(0)
189#define __P111 __pgprot(0)
190
191#define __S000 __pgprot(0)
192#define __S001 __pgprot(0)
193#define __S010 __pgprot(0)
194#define __S011 __pgprot(0)
195#define __S100 __pgprot(0)
196#define __S101 __pgprot(0)
197#define __S110 __pgprot(0)
198#define __S111 __pgprot(0)
159 199
160#define __DIRTY_BITS (_PAGE_MODIFIED | _PAGE_WRITE | _PAGE_W) 200#ifndef __ASSEMBLY__
161#define __ACCESS_BITS (_PAGE_ACCESSED | _PAGE_READ | _PAGE_R)
162#define __PRIV_BITS _PAGE_P
163 201
164#define PAGE_NONE __pgprot (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_CACHE) 202extern pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long);
165 203
166/* Don't set the TTE _PAGE_W bit here, else the dirty bit never gets set. */ 204extern unsigned long pte_sz_bits(unsigned long size);
167#define PAGE_SHARED __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
168 __ACCESS_BITS | _PAGE_WRITE | _PAGE_EXEC)
169 205
170#define PAGE_COPY __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \ 206extern pgprot_t PAGE_KERNEL;
171 __ACCESS_BITS | _PAGE_EXEC) 207extern pgprot_t PAGE_KERNEL_LOCKED;
208extern pgprot_t PAGE_COPY;
209extern pgprot_t PAGE_SHARED;
172 210
173#define PAGE_READONLY __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \ 211/* XXX This uglyness is for the atyfb driver's sparc mmap() support. XXX */
174 __ACCESS_BITS | _PAGE_EXEC) 212extern unsigned long _PAGE_IE;
213extern unsigned long _PAGE_E;
214extern unsigned long _PAGE_CACHE;
175 215
176#define PAGE_KERNEL __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \ 216extern unsigned long pg_iobits;
177 __PRIV_BITS | \ 217extern unsigned long _PAGE_ALL_SZ_BITS;
178 __ACCESS_BITS | __DIRTY_BITS | _PAGE_EXEC) 218extern unsigned long _PAGE_SZBITS;
179 219
180#define PAGE_SHARED_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \ 220extern struct page *mem_map_zero;
181 _PAGE_CACHE | \ 221#define ZERO_PAGE(vaddr) (mem_map_zero)
182 __ACCESS_BITS | _PAGE_WRITE)
183 222
184#define PAGE_COPY_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \ 223/* PFNs are real physical page numbers. However, mem_map only begins to record
185 _PAGE_CACHE | __ACCESS_BITS) 224 * per-page information starting at pfn_base. This is to handle systems where
225 * the first physical page in the machine is at some huge physical address,
226 * such as 4GB. This is common on a partitioned E10000, for example.
227 */
228static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
229{
230 unsigned long paddr = pfn << PAGE_SHIFT;
231 unsigned long sz_bits;
232
233 sz_bits = 0UL;
234 if (_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL) {
235 __asm__ __volatile__(
236 "\n661: sethi %uhi(%1), %0\n"
237 " sllx %0, 32, %0\n"
238 " .section .sun4v_2insn_patch, \"ax\"\n"
239 " .word 661b\n"
240 " mov %2, %0\n"
241 " nop\n"
242 " .previous\n"
243 : "=r" (sz_bits)
244 : "i" (_PAGE_SZBITS_4U), "i" (_PAGE_SZBITS_4V));
245 }
246 return __pte(paddr | sz_bits | pgprot_val(prot));
247}
248#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
186 249
187#define PAGE_READONLY_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \ 250/* This one can be done with two shifts. */
188 _PAGE_CACHE | __ACCESS_BITS) 251static inline unsigned long pte_pfn(pte_t pte)
252{
253 unsigned long ret;
254
255 __asm__ __volatile__(
256 "\n661: sllx %1, %2, %0\n"
257 " srlx %0, %3, %0\n"
258 " .section .sun4v_2insn_patch, \"ax\"\n"
259 " .word 661b\n"
260 " sllx %1, %4, %0\n"
261 " srlx %0, %5, %0\n"
262 " .previous\n"
263 : "=r" (ret)
264 : "r" (pte_val(pte)),
265 "i" (21), "i" (21 + PAGE_SHIFT),
266 "i" (8), "i" (8 + PAGE_SHIFT));
267
268 return ret;
269}
270#define pte_page(x) pfn_to_page(pte_pfn(x))
189 271
190#define _PFN_MASK _PAGE_PADDR 272static inline pte_t pte_modify(pte_t pte, pgprot_t prot)
273{
274 unsigned long mask, tmp;
275
276 /* SUN4U: 0x600307ffffffecb8 (negated == 0x9ffcf80000001347)
277 * SUN4V: 0x30ffffffffffee17 (negated == 0xcf000000000011e8)
278 *
279 * Even if we use negation tricks the result is still a 6
280 * instruction sequence, so don't try to play fancy and just
281 * do the most straightforward implementation.
282 *
283 * Note: We encode this into 3 sun4v 2-insn patch sequences.
284 */
191 285
192#define pg_iobits (_PAGE_VALID | _PAGE_PRESENT | __DIRTY_BITS | \ 286 __asm__ __volatile__(
193 __ACCESS_BITS | _PAGE_E) 287 "\n661: sethi %%uhi(%2), %1\n"
288 " sethi %%hi(%2), %0\n"
289 "\n662: or %1, %%ulo(%2), %1\n"
290 " or %0, %%lo(%2), %0\n"
291 "\n663: sllx %1, 32, %1\n"
292 " or %0, %1, %0\n"
293 " .section .sun4v_2insn_patch, \"ax\"\n"
294 " .word 661b\n"
295 " sethi %%uhi(%3), %1\n"
296 " sethi %%hi(%3), %0\n"
297 " .word 662b\n"
298 " or %1, %%ulo(%3), %1\n"
299 " or %0, %%lo(%3), %0\n"
300 " .word 663b\n"
301 " sllx %1, 32, %1\n"
302 " or %0, %1, %0\n"
303 " .previous\n"
304 : "=r" (mask), "=r" (tmp)
305 : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U |
306 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | _PAGE_PRESENT_4U |
307 _PAGE_SZBITS_4U),
308 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V |
309 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | _PAGE_PRESENT_4V |
310 _PAGE_SZBITS_4V));
311
312 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask));
313}
194 314
195#define __P000 PAGE_NONE 315static inline pte_t pgoff_to_pte(unsigned long off)
196#define __P001 PAGE_READONLY_NOEXEC 316{
197#define __P010 PAGE_COPY_NOEXEC 317 off <<= PAGE_SHIFT;
198#define __P011 PAGE_COPY_NOEXEC 318
199#define __P100 PAGE_READONLY 319 __asm__ __volatile__(
200#define __P101 PAGE_READONLY 320 "\n661: or %0, %2, %0\n"
201#define __P110 PAGE_COPY 321 " .section .sun4v_1insn_patch, \"ax\"\n"
202#define __P111 PAGE_COPY 322 " .word 661b\n"
323 " or %0, %3, %0\n"
324 " .previous\n"
325 : "=r" (off)
326 : "0" (off), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
327
328 return __pte(off);
329}
203 330
204#define __S000 PAGE_NONE 331static inline pgprot_t pgprot_noncached(pgprot_t prot)
205#define __S001 PAGE_READONLY_NOEXEC 332{
206#define __S010 PAGE_SHARED_NOEXEC 333 unsigned long val = pgprot_val(prot);
207#define __S011 PAGE_SHARED_NOEXEC 334
208#define __S100 PAGE_READONLY 335 __asm__ __volatile__(
209#define __S101 PAGE_READONLY 336 "\n661: andn %0, %2, %0\n"
210#define __S110 PAGE_SHARED 337 " or %0, %3, %0\n"
211#define __S111 PAGE_SHARED 338 " .section .sun4v_2insn_patch, \"ax\"\n"
339 " .word 661b\n"
340 " andn %0, %4, %0\n"
341 " or %0, %3, %0\n"
342 " .previous\n"
343 : "=r" (val)
344 : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U),
345 "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V));
346
347 return __pgprot(val);
348}
349/* Various pieces of code check for platform support by ifdef testing
350 * on "pgprot_noncached". That's broken and should be fixed, but for
351 * now...
352 */
353#define pgprot_noncached pgprot_noncached
212 354
213#ifndef __ASSEMBLY__ 355#ifdef CONFIG_HUGETLB_PAGE
356static inline pte_t pte_mkhuge(pte_t pte)
357{
358 unsigned long mask;
359
360 __asm__ __volatile__(
361 "\n661: sethi %%uhi(%1), %0\n"
362 " sllx %0, 32, %0\n"
363 " .section .sun4v_2insn_patch, \"ax\"\n"
364 " .word 661b\n"
365 " mov %2, %0\n"
366 " nop\n"
367 " .previous\n"
368 : "=r" (mask)
369 : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V));
370
371 return __pte(pte_val(pte) | mask);
372}
373#endif
214 374
215extern unsigned long phys_base; 375static inline pte_t pte_mkdirty(pte_t pte)
216extern unsigned long pfn_base; 376{
377 unsigned long val = pte_val(pte), tmp;
378
379 __asm__ __volatile__(
380 "\n661: or %0, %3, %0\n"
381 " nop\n"
382 "\n662: nop\n"
383 " nop\n"
384 " .section .sun4v_2insn_patch, \"ax\"\n"
385 " .word 661b\n"
386 " sethi %%uhi(%4), %1\n"
387 " sllx %1, 32, %1\n"
388 " .word 662b\n"
389 " or %1, %%lo(%4), %1\n"
390 " or %0, %1, %0\n"
391 " .previous\n"
392 : "=r" (val), "=r" (tmp)
393 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
394 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
395
396 return __pte(val);
397}
217 398
218extern struct page *mem_map_zero; 399static inline pte_t pte_mkclean(pte_t pte)
219#define ZERO_PAGE(vaddr) (mem_map_zero) 400{
401 unsigned long val = pte_val(pte), tmp;
402
403 __asm__ __volatile__(
404 "\n661: andn %0, %3, %0\n"
405 " nop\n"
406 "\n662: nop\n"
407 " nop\n"
408 " .section .sun4v_2insn_patch, \"ax\"\n"
409 " .word 661b\n"
410 " sethi %%uhi(%4), %1\n"
411 " sllx %1, 32, %1\n"
412 " .word 662b\n"
413 " or %1, %%lo(%4), %1\n"
414 " andn %0, %1, %0\n"
415 " .previous\n"
416 : "=r" (val), "=r" (tmp)
417 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
418 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
419
420 return __pte(val);
421}
220 422
221/* PFNs are real physical page numbers. However, mem_map only begins to record 423static inline pte_t pte_mkwrite(pte_t pte)
222 * per-page information starting at pfn_base. This is to handle systems where 424{
223 * the first physical page in the machine is at some huge physical address, 425 unsigned long val = pte_val(pte), mask;
224 * such as 4GB. This is common on a partitioned E10000, for example. 426
225 */ 427 __asm__ __volatile__(
428 "\n661: mov %1, %0\n"
429 " nop\n"
430 " .section .sun4v_2insn_patch, \"ax\"\n"
431 " .word 661b\n"
432 " sethi %%uhi(%2), %0\n"
433 " sllx %0, 32, %0\n"
434 " .previous\n"
435 : "=r" (mask)
436 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
437
438 return __pte(val | mask);
439}
226 440
227#define pfn_pte(pfn, prot) \ 441static inline pte_t pte_wrprotect(pte_t pte)
228 __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot) | _PAGE_SZBITS) 442{
229#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 443 unsigned long val = pte_val(pte), tmp;
444
445 __asm__ __volatile__(
446 "\n661: andn %0, %3, %0\n"
447 " nop\n"
448 "\n662: nop\n"
449 " nop\n"
450 " .section .sun4v_2insn_patch, \"ax\"\n"
451 " .word 661b\n"
452 " sethi %%uhi(%4), %1\n"
453 " sllx %1, 32, %1\n"
454 " .word 662b\n"
455 " or %1, %%lo(%4), %1\n"
456 " andn %0, %1, %0\n"
457 " .previous\n"
458 : "=r" (val), "=r" (tmp)
459 : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U),
460 "i" (_PAGE_WRITE_4V | _PAGE_W_4V));
461
462 return __pte(val);
463}
464
465static inline pte_t pte_mkold(pte_t pte)
466{
467 unsigned long mask;
468
469 __asm__ __volatile__(
470 "\n661: mov %1, %0\n"
471 " nop\n"
472 " .section .sun4v_2insn_patch, \"ax\"\n"
473 " .word 661b\n"
474 " sethi %%uhi(%2), %0\n"
475 " sllx %0, 32, %0\n"
476 " .previous\n"
477 : "=r" (mask)
478 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
479
480 mask |= _PAGE_R;
481
482 return __pte(pte_val(pte) & ~mask);
483}
484
485static inline pte_t pte_mkyoung(pte_t pte)
486{
487 unsigned long mask;
488
489 __asm__ __volatile__(
490 "\n661: mov %1, %0\n"
491 " nop\n"
492 " .section .sun4v_2insn_patch, \"ax\"\n"
493 " .word 661b\n"
494 " sethi %%uhi(%2), %0\n"
495 " sllx %0, 32, %0\n"
496 " .previous\n"
497 : "=r" (mask)
498 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
499
500 mask |= _PAGE_R;
501
502 return __pte(pte_val(pte) | mask);
503}
230 504
231#define pte_pfn(x) ((pte_val(x) & _PAGE_PADDR)>>PAGE_SHIFT) 505static inline unsigned long pte_young(pte_t pte)
232#define pte_page(x) pfn_to_page(pte_pfn(x)) 506{
507 unsigned long mask;
508
509 __asm__ __volatile__(
510 "\n661: mov %1, %0\n"
511 " nop\n"
512 " .section .sun4v_2insn_patch, \"ax\"\n"
513 " .word 661b\n"
514 " sethi %%uhi(%2), %0\n"
515 " sllx %0, 32, %0\n"
516 " .previous\n"
517 : "=r" (mask)
518 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
519
520 return (pte_val(pte) & mask);
521}
522
523static inline unsigned long pte_dirty(pte_t pte)
524{
525 unsigned long mask;
526
527 __asm__ __volatile__(
528 "\n661: mov %1, %0\n"
529 " nop\n"
530 " .section .sun4v_2insn_patch, \"ax\"\n"
531 " .word 661b\n"
532 " sethi %%uhi(%2), %0\n"
533 " sllx %0, 32, %0\n"
534 " .previous\n"
535 : "=r" (mask)
536 : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V));
537
538 return (pte_val(pte) & mask);
539}
233 540
234static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot) 541static inline unsigned long pte_write(pte_t pte)
235{ 542{
236 pte_t __pte; 543 unsigned long mask;
237 const unsigned long preserve_mask = (_PFN_MASK | 544
238 _PAGE_MODIFIED | _PAGE_ACCESSED | 545 __asm__ __volatile__(
239 _PAGE_CACHE | _PAGE_E | 546 "\n661: mov %1, %0\n"
240 _PAGE_PRESENT | _PAGE_SZBITS); 547 " nop\n"
548 " .section .sun4v_2insn_patch, \"ax\"\n"
549 " .word 661b\n"
550 " sethi %%uhi(%2), %0\n"
551 " sllx %0, 32, %0\n"
552 " .previous\n"
553 : "=r" (mask)
554 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
555
556 return (pte_val(pte) & mask);
557}
241 558
242 pte_val(__pte) = (pte_val(orig_pte) & preserve_mask) | 559static inline unsigned long pte_exec(pte_t pte)
243 (pgprot_val(new_prot) & ~preserve_mask); 560{
561 unsigned long mask;
562
563 __asm__ __volatile__(
564 "\n661: sethi %%hi(%1), %0\n"
565 " .section .sun4v_1insn_patch, \"ax\"\n"
566 " .word 661b\n"
567 " mov %2, %0\n"
568 " .previous\n"
569 : "=r" (mask)
570 : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V));
571
572 return (pte_val(pte) & mask);
573}
244 574
245 return __pte; 575static inline unsigned long pte_read(pte_t pte)
576{
577 unsigned long mask;
578
579 __asm__ __volatile__(
580 "\n661: mov %1, %0\n"
581 " nop\n"
582 " .section .sun4v_2insn_patch, \"ax\"\n"
583 " .word 661b\n"
584 " sethi %%uhi(%2), %0\n"
585 " sllx %0, 32, %0\n"
586 " .previous\n"
587 : "=r" (mask)
588 : "i" (_PAGE_READ_4U), "i" (_PAGE_READ_4V));
589
590 return (pte_val(pte) & mask);
246} 591}
592
593static inline unsigned long pte_file(pte_t pte)
594{
595 unsigned long val = pte_val(pte);
596
597 __asm__ __volatile__(
598 "\n661: and %0, %2, %0\n"
599 " .section .sun4v_1insn_patch, \"ax\"\n"
600 " .word 661b\n"
601 " and %0, %3, %0\n"
602 " .previous\n"
603 : "=r" (val)
604 : "0" (val), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
605
606 return val;
607}
608
609static inline unsigned long pte_present(pte_t pte)
610{
611 unsigned long val = pte_val(pte);
612
613 __asm__ __volatile__(
614 "\n661: and %0, %2, %0\n"
615 " .section .sun4v_1insn_patch, \"ax\"\n"
616 " .word 661b\n"
617 " and %0, %3, %0\n"
618 " .previous\n"
619 : "=r" (val)
620 : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V));
621
622 return val;
623}
624
247#define pmd_set(pmdp, ptep) \ 625#define pmd_set(pmdp, ptep) \
248 (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL)) 626 (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL))
249#define pud_set(pudp, pmdp) \ 627#define pud_set(pudp, pmdp) \
@@ -253,8 +631,6 @@ static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot)
253#define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) 631#define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
254#define pud_page(pud) \ 632#define pud_page(pud) \
255 ((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL))) 633 ((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL)))
256#define pte_none(pte) (!pte_val(pte))
257#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
258#define pmd_none(pmd) (!pmd_val(pmd)) 634#define pmd_none(pmd) (!pmd_val(pmd))
259#define pmd_bad(pmd) (0) 635#define pmd_bad(pmd) (0)
260#define pmd_present(pmd) (pmd_val(pmd) != 0U) 636#define pmd_present(pmd) (pmd_val(pmd) != 0U)
@@ -264,30 +640,8 @@ static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot)
264#define pud_present(pud) (pud_val(pud) != 0U) 640#define pud_present(pud) (pud_val(pud) != 0U)
265#define pud_clear(pudp) (pud_val(*(pudp)) = 0U) 641#define pud_clear(pudp) (pud_val(*(pudp)) = 0U)
266 642
267/* The following only work if pte_present() is true. 643/* Same in both SUN4V and SUN4U. */
268 * Undefined behaviour if not.. 644#define pte_none(pte) (!pte_val(pte))
269 */
270#define pte_read(pte) (pte_val(pte) & _PAGE_READ)
271#define pte_exec(pte) (pte_val(pte) & _PAGE_EXEC)
272#define pte_write(pte) (pte_val(pte) & _PAGE_WRITE)
273#define pte_dirty(pte) (pte_val(pte) & _PAGE_MODIFIED)
274#define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED)
275#define pte_wrprotect(pte) (__pte(pte_val(pte) & ~(_PAGE_WRITE|_PAGE_W)))
276#define pte_rdprotect(pte) \
277 (__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_READ))
278#define pte_mkclean(pte) \
279 (__pte(pte_val(pte) & ~(_PAGE_MODIFIED|_PAGE_W)))
280#define pte_mkold(pte) \
281 (__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_ACCESSED))
282
283/* Permanent address of a page. */
284#define __page_address(page) page_address(page)
285
286/* Be very careful when you change these three, they are delicate. */
287#define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_ACCESSED | _PAGE_R))
288#define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_WRITE))
289#define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_MODIFIED | _PAGE_W))
290#define pte_mkhuge(pte) (__pte(pte_val(pte) | _PAGE_SZHUGE))
291 645
292/* to find an entry in a page-table-directory. */ 646/* to find an entry in a page-table-directory. */
293#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 647#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
@@ -296,11 +650,6 @@ static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot)
296/* to find an entry in a kernel page-table-directory */ 650/* to find an entry in a kernel page-table-directory */
297#define pgd_offset_k(address) pgd_offset(&init_mm, address) 651#define pgd_offset_k(address) pgd_offset(&init_mm, address)
298 652
299/* extract the pgd cache used for optimizing the tlb miss
300 * slow path when executing 32-bit compat processes
301 */
302#define get_pgd_cache(pgd) ((unsigned long) pgd_val(*pgd) << 11)
303
304/* Find an entry in the second-level page table.. */ 653/* Find an entry in the second-level page table.. */
305#define pmd_offset(pudp, address) \ 654#define pmd_offset(pudp, address) \
306 ((pmd_t *) pud_page(*(pudp)) + \ 655 ((pmd_t *) pud_page(*(pudp)) + \
@@ -327,6 +676,9 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *p
327 676
328 /* It is more efficient to let flush_tlb_kernel_range() 677 /* It is more efficient to let flush_tlb_kernel_range()
329 * handle init_mm tlb flushes. 678 * handle init_mm tlb flushes.
679 *
680 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U
681 * and SUN4V pte layout, so this inline test is fine.
330 */ 682 */
331 if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID)) 683 if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID))
332 tlb_batch_add(mm, addr, ptep, orig); 684 tlb_batch_add(mm, addr, ptep, orig);
@@ -361,42 +713,23 @@ extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
361#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 713#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
362 714
363/* File offset in PTE support. */ 715/* File offset in PTE support. */
364#define pte_file(pte) (pte_val(pte) & _PAGE_FILE) 716extern unsigned long pte_file(pte_t);
365#define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT) 717#define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT)
366#define pgoff_to_pte(off) (__pte(((off) << PAGE_SHIFT) | _PAGE_FILE)) 718extern pte_t pgoff_to_pte(unsigned long);
367#define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL) 719#define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL)
368 720
369extern unsigned long prom_virt_to_phys(unsigned long, int *); 721extern unsigned long prom_virt_to_phys(unsigned long, int *);
370 722
371static __inline__ unsigned long 723extern unsigned long sun4u_get_pte(unsigned long);
372sun4u_get_pte (unsigned long addr)
373{
374 pgd_t *pgdp;
375 pud_t *pudp;
376 pmd_t *pmdp;
377 pte_t *ptep;
378
379 if (addr >= PAGE_OFFSET)
380 return addr & _PAGE_PADDR;
381 if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
382 return prom_virt_to_phys(addr, NULL);
383 pgdp = pgd_offset_k(addr);
384 pudp = pud_offset(pgdp, addr);
385 pmdp = pmd_offset(pudp, addr);
386 ptep = pte_offset_kernel(pmdp, addr);
387 return pte_val(*ptep) & _PAGE_PADDR;
388}
389 724
390static __inline__ unsigned long 725static inline unsigned long __get_phys(unsigned long addr)
391__get_phys (unsigned long addr)
392{ 726{
393 return sun4u_get_pte (addr); 727 return sun4u_get_pte(addr);
394} 728}
395 729
396static __inline__ int 730static inline int __get_iospace(unsigned long addr)
397__get_iospace (unsigned long addr)
398{ 731{
399 return ((sun4u_get_pte (addr) & 0xf0000000) >> 28); 732 return ((sun4u_get_pte(addr) & 0xf0000000) >> 28);
400} 733}
401 734
402extern unsigned long *sparc64_valid_addr_bitmap; 735extern unsigned long *sparc64_valid_addr_bitmap;
@@ -409,11 +742,6 @@ extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
409 unsigned long pfn, 742 unsigned long pfn,
410 unsigned long size, pgprot_t prot); 743 unsigned long size, pgprot_t prot);
411 744
412/* Clear virtual and physical cachability, set side-effect bit. */
413#define pgprot_noncached(prot) \
414 (__pgprot((pgprot_val(prot) & ~(_PAGE_CP | _PAGE_CV)) | \
415 _PAGE_E))
416
417/* 745/*
418 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in 746 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
419 * its high 4 bits. These macros/functions put it there or get it from there. 747 * its high 4 bits. These macros/functions put it there or get it from there.
@@ -424,8 +752,11 @@ extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
424 752
425#include <asm-generic/pgtable.h> 753#include <asm-generic/pgtable.h>
426 754
427/* We provide our own get_unmapped_area to cope with VA holes for userland */ 755/* We provide our own get_unmapped_area to cope with VA holes and
756 * SHM area cache aliasing for userland.
757 */
428#define HAVE_ARCH_UNMAPPED_AREA 758#define HAVE_ARCH_UNMAPPED_AREA
759#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
429 760
430/* We provide a special get_unmapped_area for framebuffer mmaps to try and use 761/* We provide a special get_unmapped_area for framebuffer mmaps to try and use
431 * the largest alignment possible such that larget PTEs can be used. 762 * the largest alignment possible such that larget PTEs can be used.
@@ -435,12 +766,9 @@ extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
435 unsigned long); 766 unsigned long);
436#define HAVE_ARCH_FB_UNMAPPED_AREA 767#define HAVE_ARCH_FB_UNMAPPED_AREA
437 768
438/* 769extern void pgtable_cache_init(void);
439 * No page table caches to initialise 770extern void sun4v_register_fault_status(void);
440 */ 771extern void sun4v_ktsb_register(void);
441#define pgtable_cache_init() do { } while (0)
442
443extern void check_pgt_cache(void);
444 772
445#endif /* !(__ASSEMBLY__) */ 773#endif /* !(__ASSEMBLY__) */
446 774
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 09:49:46 -0500