diff options
Diffstat (limited to 'include/asm-sparc64/pgtable.h')
-rw-r--r-- | include/asm-sparc64/pgtable.h | 706 |
1 files changed, 518 insertions, 188 deletions
diff --git a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h index f0a9b44d3eb5..c44e7466534e 100644 --- a/include/asm-sparc64/pgtable.h +++ b/include/asm-sparc64/pgtable.h | |||
@@ -25,7 +25,8 @@ | |||
25 | #include <asm/const.h> | 25 | #include <asm/const.h> |
26 | 26 | ||
27 | /* The kernel image occupies 0x4000000 to 0x1000000 (4MB --> 32MB). | 27 | /* The kernel image occupies 0x4000000 to 0x1000000 (4MB --> 32MB). |
28 | * The page copy blockops can use 0x2000000 to 0x10000000. | 28 | * The page copy blockops can use 0x2000000 to 0x4000000. |
29 | * The TSB is mapped in the 0x4000000 to 0x6000000 range. | ||
29 | * The PROM resides in an area spanning 0xf0000000 to 0x100000000. | 30 | * The PROM resides in an area spanning 0xf0000000 to 0x100000000. |
30 | * The vmalloc area spans 0x100000000 to 0x200000000. | 31 | * The vmalloc area spans 0x100000000 to 0x200000000. |
31 | * Since modules need to be in the lowest 32-bits of the address space, | 32 | * Since modules need to be in the lowest 32-bits of the address space, |
@@ -34,6 +35,7 @@ | |||
34 | * 0x400000000. | 35 | * 0x400000000. |
35 | */ | 36 | */ |
36 | #define TLBTEMP_BASE _AC(0x0000000002000000,UL) | 37 | #define TLBTEMP_BASE _AC(0x0000000002000000,UL) |
38 | #define TSBMAP_BASE _AC(0x0000000004000000,UL) | ||
37 | #define MODULES_VADDR _AC(0x0000000010000000,UL) | 39 | #define MODULES_VADDR _AC(0x0000000010000000,UL) |
38 | #define MODULES_LEN _AC(0x00000000e0000000,UL) | 40 | #define MODULES_LEN _AC(0x00000000e0000000,UL) |
39 | #define MODULES_END _AC(0x00000000f0000000,UL) | 41 | #define MODULES_END _AC(0x00000000f0000000,UL) |
@@ -88,162 +90,540 @@ | |||
88 | 90 | ||
89 | #endif /* !(__ASSEMBLY__) */ | 91 | #endif /* !(__ASSEMBLY__) */ |
90 | 92 | ||
91 | /* Spitfire/Cheetah TTE bits. */ | 93 | /* PTE bits which are the same in SUN4U and SUN4V format. */ |
92 | #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */ | 94 | #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */ |
93 | #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit up to date*/ | 95 | #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/ |
94 | #define _PAGE_SZ4MB _AC(0x6000000000000000,UL) /* 4MB Page */ | 96 | |
95 | #define _PAGE_SZ512K _AC(0x4000000000000000,UL) /* 512K Page */ | 97 | /* SUN4U pte bits... */ |
96 | #define _PAGE_SZ64K _AC(0x2000000000000000,UL) /* 64K Page */ | 98 | #define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */ |
97 | #define _PAGE_SZ8K _AC(0x0000000000000000,UL) /* 8K Page */ | 99 | #define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */ |
98 | #define _PAGE_NFO _AC(0x1000000000000000,UL) /* No Fault Only */ | 100 | #define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */ |
99 | #define _PAGE_IE _AC(0x0800000000000000,UL) /* Invert Endianness */ | 101 | #define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */ |
100 | #define _PAGE_SOFT2 _AC(0x07FC000000000000,UL) /* Software bits, set 2 */ | 102 | #define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */ |
101 | #define _PAGE_RES1 _AC(0x0002000000000000,UL) /* Reserved */ | 103 | #define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */ |
102 | #define _PAGE_SZ32MB _AC(0x0001000000000000,UL) /* (Panther) 32MB page */ | 104 | #define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */ |
103 | #define _PAGE_SZ256MB _AC(0x2001000000000000,UL) /* (Panther) 256MB page */ | 105 | #define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */ |
104 | #define _PAGE_SN _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */ | 106 | #define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */ |
105 | #define _PAGE_RES2 _AC(0x0000780000000000,UL) /* Reserved */ | 107 | #define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */ |
106 | #define _PAGE_PADDR_SF _AC(0x000001FFFFFFE000,UL) /* (Spitfire) paddr[40:13]*/ | 108 | #define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */ |
107 | #define _PAGE_PADDR _AC(0x000007FFFFFFE000,UL) /* (Cheetah) paddr[42:13] */ | 109 | #define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */ |
108 | #define _PAGE_SOFT _AC(0x0000000000001F80,UL) /* Software bits */ | 110 | #define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */ |
109 | #define _PAGE_L _AC(0x0000000000000040,UL) /* Locked TTE */ | 111 | #define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */ |
110 | #define _PAGE_CP _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */ | 112 | #define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */ |
111 | #define _PAGE_CV _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */ | 113 | #define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */ |
112 | #define _PAGE_E _AC(0x0000000000000008,UL) /* side-Effect */ | 114 | #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */ |
113 | #define _PAGE_P _AC(0x0000000000000004,UL) /* Privileged Page */ | 115 | #define _PAGE_FILE_4U _AC(0x0000000000000800,UL) /* Pagecache page */ |
114 | #define _PAGE_W _AC(0x0000000000000002,UL) /* Writable */ | 116 | #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */ |
115 | #define _PAGE_G _AC(0x0000000000000001,UL) /* Global */ | 117 | #define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */ |
116 | 118 | #define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */ | |
117 | /* Here are the SpitFire software bits we use in the TTE's. | 119 | #define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */ |
118 | * | 120 | #define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */ |
119 | * WARNING: If you are going to try and start using some | 121 | #define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */ |
120 | * of the soft2 bits, you will need to make | 122 | #define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */ |
121 | * modifications to the swap entry implementation. | 123 | #define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */ |
122 | * For example, one thing that could happen is that | 124 | #define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */ |
123 | * swp_entry_to_pte() would BUG_ON() if you tried | 125 | #define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */ |
124 | * to use one of the soft2 bits for _PAGE_FILE. | 126 | |
125 | * | 127 | /* SUN4V pte bits... */ |
126 | * Like other architectures, I have aliased _PAGE_FILE with | 128 | #define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */ |
127 | * _PAGE_MODIFIED. This works because _PAGE_FILE is never | 129 | #define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */ |
128 | * interpreted that way unless _PAGE_PRESENT is clear. | 130 | #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */ |
129 | */ | 131 | #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */ |
130 | #define _PAGE_EXEC _AC(0x0000000000001000,UL) /* Executable SW bit */ | 132 | #define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */ |
131 | #define _PAGE_MODIFIED _AC(0x0000000000000800,UL) /* Modified (dirty) */ | 133 | #define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */ |
132 | #define _PAGE_FILE _AC(0x0000000000000800,UL) /* Pagecache page */ | 134 | #define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */ |
133 | #define _PAGE_ACCESSED _AC(0x0000000000000400,UL) /* Accessed (ref'd) */ | 135 | #define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */ |
134 | #define _PAGE_READ _AC(0x0000000000000200,UL) /* Readable SW Bit */ | 136 | #define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */ |
135 | #define _PAGE_WRITE _AC(0x0000000000000100,UL) /* Writable SW Bit */ | 137 | #define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */ |
136 | #define _PAGE_PRESENT _AC(0x0000000000000080,UL) /* Present */ | 138 | #define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */ |
139 | #define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */ | ||
140 | #define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */ | ||
141 | #define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */ | ||
142 | #define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */ | ||
143 | #define _PAGE_FILE_4V _AC(0x0000000000000020,UL) /* Pagecache page */ | ||
144 | #define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */ | ||
145 | #define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */ | ||
146 | #define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */ | ||
147 | #define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */ | ||
148 | #define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */ | ||
149 | #define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */ | ||
150 | #define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */ | ||
151 | #define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */ | ||
152 | #define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */ | ||
153 | #define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */ | ||
154 | #define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */ | ||
137 | 155 | ||
138 | #if PAGE_SHIFT == 13 | 156 | #if PAGE_SHIFT == 13 |
139 | #define _PAGE_SZBITS _PAGE_SZ8K | 157 | #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U |
158 | #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V | ||
140 | #elif PAGE_SHIFT == 16 | 159 | #elif PAGE_SHIFT == 16 |
141 | #define _PAGE_SZBITS _PAGE_SZ64K | 160 | #define _PAGE_SZBITS_4U _PAGE_SZ64K_4U |
161 | #define _PAGE_SZBITS_4V _PAGE_SZ64K_4V | ||
142 | #elif PAGE_SHIFT == 19 | 162 | #elif PAGE_SHIFT == 19 |
143 | #define _PAGE_SZBITS _PAGE_SZ512K | 163 | #define _PAGE_SZBITS_4U _PAGE_SZ512K_4U |
164 | #define _PAGE_SZBITS_4V _PAGE_SZ512K_4V | ||
144 | #elif PAGE_SHIFT == 22 | 165 | #elif PAGE_SHIFT == 22 |
145 | #define _PAGE_SZBITS _PAGE_SZ4MB | 166 | #define _PAGE_SZBITS_4U _PAGE_SZ4MB_4U |
167 | #define _PAGE_SZBITS_4V _PAGE_SZ4MB_4V | ||
146 | #else | 168 | #else |
147 | #error Wrong PAGE_SHIFT specified | 169 | #error Wrong PAGE_SHIFT specified |
148 | #endif | 170 | #endif |
149 | 171 | ||
150 | #if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB) | 172 | #if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB) |
151 | #define _PAGE_SZHUGE _PAGE_SZ4MB | 173 | #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U |
174 | #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V | ||
152 | #elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K) | 175 | #elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K) |
153 | #define _PAGE_SZHUGE _PAGE_SZ512K | 176 | #define _PAGE_SZHUGE_4U _PAGE_SZ512K_4U |
177 | #define _PAGE_SZHUGE_4V _PAGE_SZ512K_4V | ||
154 | #elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K) | 178 | #elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K) |
155 | #define _PAGE_SZHUGE _PAGE_SZ64K | 179 | #define _PAGE_SZHUGE_4U _PAGE_SZ64K_4U |
180 | #define _PAGE_SZHUGE_4V _PAGE_SZ64K_4V | ||
156 | #endif | 181 | #endif |
157 | 182 | ||
158 | #define _PAGE_CACHE (_PAGE_CP | _PAGE_CV) | 183 | /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */ |
184 | #define __P000 __pgprot(0) | ||
185 | #define __P001 __pgprot(0) | ||
186 | #define __P010 __pgprot(0) | ||
187 | #define __P011 __pgprot(0) | ||
188 | #define __P100 __pgprot(0) | ||
189 | #define __P101 __pgprot(0) | ||
190 | #define __P110 __pgprot(0) | ||
191 | #define __P111 __pgprot(0) | ||
192 | |||
193 | #define __S000 __pgprot(0) | ||
194 | #define __S001 __pgprot(0) | ||
195 | #define __S010 __pgprot(0) | ||
196 | #define __S011 __pgprot(0) | ||
197 | #define __S100 __pgprot(0) | ||
198 | #define __S101 __pgprot(0) | ||
199 | #define __S110 __pgprot(0) | ||
200 | #define __S111 __pgprot(0) | ||
159 | 201 | ||
160 | #define __DIRTY_BITS (_PAGE_MODIFIED | _PAGE_WRITE | _PAGE_W) | 202 | #ifndef __ASSEMBLY__ |
161 | #define __ACCESS_BITS (_PAGE_ACCESSED | _PAGE_READ | _PAGE_R) | ||
162 | #define __PRIV_BITS _PAGE_P | ||
163 | 203 | ||
164 | #define PAGE_NONE __pgprot (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_CACHE) | 204 | extern pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long); |
165 | 205 | ||
166 | /* Don't set the TTE _PAGE_W bit here, else the dirty bit never gets set. */ | 206 | extern unsigned long pte_sz_bits(unsigned long size); |
167 | #define PAGE_SHARED __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \ | ||
168 | __ACCESS_BITS | _PAGE_WRITE | _PAGE_EXEC) | ||
169 | 207 | ||
170 | #define PAGE_COPY __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \ | 208 | extern pgprot_t PAGE_KERNEL; |
171 | __ACCESS_BITS | _PAGE_EXEC) | 209 | extern pgprot_t PAGE_KERNEL_LOCKED; |
210 | extern pgprot_t PAGE_COPY; | ||
211 | extern pgprot_t PAGE_SHARED; | ||
172 | 212 | ||
173 | #define PAGE_READONLY __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \ | 213 | /* XXX This uglyness is for the atyfb driver's sparc mmap() support. XXX */ |
174 | __ACCESS_BITS | _PAGE_EXEC) | 214 | extern unsigned long _PAGE_IE; |
215 | extern unsigned long _PAGE_E; | ||
216 | extern unsigned long _PAGE_CACHE; | ||
175 | 217 | ||
176 | #define PAGE_KERNEL __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \ | 218 | extern unsigned long pg_iobits; |
177 | __PRIV_BITS | \ | 219 | extern unsigned long _PAGE_ALL_SZ_BITS; |
178 | __ACCESS_BITS | __DIRTY_BITS | _PAGE_EXEC) | 220 | extern unsigned long _PAGE_SZBITS; |
179 | 221 | ||
180 | #define PAGE_SHARED_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \ | 222 | extern struct page *mem_map_zero; |
181 | _PAGE_CACHE | \ | 223 | #define ZERO_PAGE(vaddr) (mem_map_zero) |
182 | __ACCESS_BITS | _PAGE_WRITE) | ||
183 | 224 | ||
184 | #define PAGE_COPY_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \ | 225 | /* PFNs are real physical page numbers. However, mem_map only begins to record |
185 | _PAGE_CACHE | __ACCESS_BITS) | 226 | * per-page information starting at pfn_base. This is to handle systems where |
227 | * the first physical page in the machine is at some huge physical address, | ||
228 | * such as 4GB. This is common on a partitioned E10000, for example. | ||
229 | */ | ||
230 | static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) | ||
231 | { | ||
232 | unsigned long paddr = pfn << PAGE_SHIFT; | ||
233 | unsigned long sz_bits; | ||
234 | |||
235 | sz_bits = 0UL; | ||
236 | if (_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL) { | ||
237 | __asm__ __volatile__( | ||
238 | "\n661: sethi %uhi(%1), %0\n" | ||
239 | " sllx %0, 32, %0\n" | ||
240 | " .section .sun4v_2insn_patch, \"ax\"\n" | ||
241 | " .word 661b\n" | ||
242 | " mov %2, %0\n" | ||
243 | " nop\n" | ||
244 | " .previous\n" | ||
245 | : "=r" (sz_bits) | ||
246 | : "i" (_PAGE_SZBITS_4U), "i" (_PAGE_SZBITS_4V)); | ||
247 | } | ||
248 | return __pte(paddr | sz_bits | pgprot_val(prot)); | ||
249 | } | ||
250 | #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) | ||
186 | 251 | ||
187 | #define PAGE_READONLY_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \ | 252 | /* This one can be done with two shifts. */ |
188 | _PAGE_CACHE | __ACCESS_BITS) | 253 | static inline unsigned long pte_pfn(pte_t pte) |
254 | { | ||
255 | unsigned long ret; | ||
256 | |||
257 | __asm__ __volatile__( | ||
258 | "\n661: sllx %1, %2, %0\n" | ||
259 | " srlx %0, %3, %0\n" | ||
260 | " .section .sun4v_2insn_patch, \"ax\"\n" | ||
261 | " .word 661b\n" | ||
262 | " sllx %1, %4, %0\n" | ||
263 | " srlx %0, %5, %0\n" | ||
264 | " .previous\n" | ||
265 | : "=r" (ret) | ||
266 | : "r" (pte_val(pte)), | ||
267 | "i" (21), "i" (21 + PAGE_SHIFT), | ||
268 | "i" (8), "i" (8 + PAGE_SHIFT)); | ||
269 | |||
270 | return ret; | ||
271 | } | ||
272 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | ||
189 | 273 | ||
190 | #define _PFN_MASK _PAGE_PADDR | 274 | static inline pte_t pte_modify(pte_t pte, pgprot_t prot) |
275 | { | ||
276 | unsigned long mask, tmp; | ||
277 | |||
278 | /* SUN4U: 0x600307ffffffecb8 (negated == 0x9ffcf80000001347) | ||
279 | * SUN4V: 0x30ffffffffffee17 (negated == 0xcf000000000011e8) | ||
280 | * | ||
281 | * Even if we use negation tricks the result is still a 6 | ||
282 | * instruction sequence, so don't try to play fancy and just | ||
283 | * do the most straightforward implementation. | ||
284 | * | ||
285 | * Note: We encode this into 3 sun4v 2-insn patch sequences. | ||
286 | */ | ||
191 | 287 | ||
192 | #define pg_iobits (_PAGE_VALID | _PAGE_PRESENT | __DIRTY_BITS | \ | 288 | __asm__ __volatile__( |
193 | __ACCESS_BITS | _PAGE_E) | 289 | "\n661: sethi %%uhi(%2), %1\n" |
290 | " sethi %%hi(%2), %0\n" | ||
291 | "\n662: or %1, %%ulo(%2), %1\n" | ||
292 | " or %0, %%lo(%2), %0\n" | ||
293 | "\n663: sllx %1, 32, %1\n" | ||
294 | " or %0, %1, %0\n" | ||
295 | " .section .sun4v_2insn_patch, \"ax\"\n" | ||
296 | " .word 661b\n" | ||
297 | " sethi %%uhi(%3), %1\n" | ||
298 | " sethi %%hi(%3), %0\n" | ||
299 | " .word 662b\n" | ||
300 | " or %1, %%ulo(%3), %1\n" | ||
301 | " or %0, %%lo(%3), %0\n" | ||
302 | " .word 663b\n" | ||
303 | " sllx %1, 32, %1\n" | ||
304 | " or %0, %1, %0\n" | ||
305 | " .previous\n" | ||
306 | : "=r" (mask), "=r" (tmp) | ||
307 | : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U | | ||
308 | _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | _PAGE_PRESENT_4U | | ||
309 | _PAGE_SZBITS_4U), | ||
310 | "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | | ||
311 | _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | _PAGE_PRESENT_4V | | ||
312 | _PAGE_SZBITS_4V)); | ||
313 | |||
314 | return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask)); | ||
315 | } | ||
194 | 316 | ||
195 | #define __P000 PAGE_NONE | 317 | static inline pte_t pgoff_to_pte(unsigned long off) |
196 | #define __P001 PAGE_READONLY_NOEXEC | 318 | { |
197 | #define __P010 PAGE_COPY_NOEXEC | 319 | off <<= PAGE_SHIFT; |
198 | #define __P011 PAGE_COPY_NOEXEC | 320 | |
199 | #define __P100 PAGE_READONLY | 321 | __asm__ __volatile__( |
200 | #define __P101 PAGE_READONLY | 322 | "\n661: or %0, %2, %0\n" |
201 | #define __P110 PAGE_COPY | 323 | " .section .sun4v_1insn_patch, \"ax\"\n" |
202 | #define __P111 PAGE_COPY | 324 | " .word 661b\n" |
325 | " or %0, %3, %0\n" | ||
326 | " .previous\n" | ||
327 | : "=r" (off) | ||
328 | : "0" (off), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V)); | ||
329 | |||
330 | return __pte(off); | ||
331 | } | ||
203 | 332 | ||
204 | #define __S000 PAGE_NONE | 333 | static inline pgprot_t pgprot_noncached(pgprot_t prot) |
205 | #define __S001 PAGE_READONLY_NOEXEC | 334 | { |
206 | #define __S010 PAGE_SHARED_NOEXEC | 335 | unsigned long val = pgprot_val(prot); |
207 | #define __S011 PAGE_SHARED_NOEXEC | 336 | |
208 | #define __S100 PAGE_READONLY | 337 | __asm__ __volatile__( |
209 | #define __S101 PAGE_READONLY | 338 | "\n661: andn %0, %2, %0\n" |
210 | #define __S110 PAGE_SHARED | 339 | " or %0, %3, %0\n" |
211 | #define __S111 PAGE_SHARED | 340 | " .section .sun4v_2insn_patch, \"ax\"\n" |
341 | " .word 661b\n" | ||
342 | " andn %0, %4, %0\n" | ||
343 | " or %0, %3, %0\n" | ||
344 | " .previous\n" | ||
345 | : "=r" (val) | ||
346 | : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U), | ||
347 | "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V)); | ||
348 | |||
349 | return __pgprot(val); | ||
350 | } | ||
351 | /* Various pieces of code check for platform support by ifdef testing | ||
352 | * on "pgprot_noncached". That's broken and should be fixed, but for | ||
353 | * now... | ||
354 | */ | ||
355 | #define pgprot_noncached pgprot_noncached | ||
212 | 356 | ||
213 | #ifndef __ASSEMBLY__ | 357 | #ifdef CONFIG_HUGETLB_PAGE |
358 | static inline pte_t pte_mkhuge(pte_t pte) | ||
359 | { | ||
360 | unsigned long mask; | ||
361 | |||
362 | __asm__ __volatile__( | ||
363 | "\n661: sethi %%uhi(%1), %0\n" | ||
364 | " sllx %0, 32, %0\n" | ||
365 | " .section .sun4v_2insn_patch, \"ax\"\n" | ||
366 | " .word 661b\n" | ||
367 | " mov %2, %0\n" | ||
368 | " nop\n" | ||
369 | " .previous\n" | ||
370 | : "=r" (mask) | ||
371 | : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V)); | ||
372 | |||
373 | return __pte(pte_val(pte) | mask); | ||
374 | } | ||
375 | #endif | ||
214 | 376 | ||
215 | extern unsigned long phys_base; | 377 | static inline pte_t pte_mkdirty(pte_t pte) |
216 | extern unsigned long pfn_base; | 378 | { |
379 | unsigned long val = pte_val(pte), tmp; | ||
380 | |||
381 | __asm__ __volatile__( | ||
382 | "\n661: or %0, %3, %0\n" | ||
383 | " nop\n" | ||
384 | "\n662: nop\n" | ||
385 | " nop\n" | ||
386 | " .section .sun4v_2insn_patch, \"ax\"\n" | ||
387 | " .word 661b\n" | ||
388 | " sethi %%uhi(%4), %1\n" | ||
389 | " sllx %1, 32, %1\n" | ||
390 | " .word 662b\n" | ||
391 | " or %1, %%lo(%4), %1\n" | ||
392 | " or %0, %1, %0\n" | ||
393 | " .previous\n" | ||
394 | : "=r" (val), "=r" (tmp) | ||
395 | : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), | ||
396 | "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); | ||
397 | |||
398 | return __pte(val); | ||
399 | } | ||
217 | 400 | ||
218 | extern struct page *mem_map_zero; | 401 | static inline pte_t pte_mkclean(pte_t pte) |
219 | #define ZERO_PAGE(vaddr) (mem_map_zero) | 402 | { |
403 | unsigned long val = pte_val(pte), tmp; | ||
404 | |||
405 | __asm__ __volatile__( | ||
406 | "\n661: andn %0, %3, %0\n" | ||
407 | " nop\n" | ||
408 | "\n662: nop\n" | ||
409 | " nop\n" | ||
410 | " .section .sun4v_2insn_patch, \"ax\"\n" | ||
411 | " .word 661b\n" | ||
412 | " sethi %%uhi(%4), %1\n" | ||
413 | " sllx %1, 32, %1\n" | ||
414 | " .word 662b\n" | ||
415 | " or %1, %%lo(%4), %1\n" | ||
416 | " andn %0, %1, %0\n" | ||
417 | " .previous\n" | ||
418 | : "=r" (val), "=r" (tmp) | ||
419 | : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), | ||
420 | "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); | ||
421 | |||
422 | return __pte(val); | ||
423 | } | ||
220 | 424 | ||
221 | /* PFNs are real physical page numbers. However, mem_map only begins to record | 425 | static inline pte_t pte_mkwrite(pte_t pte) |
222 | * per-page information starting at pfn_base. This is to handle systems where | 426 | { |
223 | * the first physical page in the machine is at some huge physical address, | 427 | unsigned long val = pte_val(pte), mask; |
224 | * such as 4GB. This is common on a partitioned E10000, for example. | 428 | |
225 | */ | 429 | __asm__ __volatile__( |
430 | "\n661: mov %1, %0\n" | ||
431 | " nop\n" | ||
432 | " .section .sun4v_2insn_patch, \"ax\"\n" | ||
433 | " .word 661b\n" | ||
434 | " sethi %%uhi(%2), %0\n" | ||
435 | " sllx %0, 32, %0\n" | ||
436 | " .previous\n" | ||
437 | : "=r" (mask) | ||
438 | : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); | ||
439 | |||
440 | return __pte(val | mask); | ||
441 | } | ||
226 | 442 | ||
227 | #define pfn_pte(pfn, prot) \ | 443 | static inline pte_t pte_wrprotect(pte_t pte) |
228 | __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot) | _PAGE_SZBITS) | 444 | { |
229 | #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) | 445 | unsigned long val = pte_val(pte), tmp; |
446 | |||
447 | __asm__ __volatile__( | ||
448 | "\n661: andn %0, %3, %0\n" | ||
449 | " nop\n" | ||
450 | "\n662: nop\n" | ||
451 | " nop\n" | ||
452 | " .section .sun4v_2insn_patch, \"ax\"\n" | ||
453 | " .word 661b\n" | ||
454 | " sethi %%uhi(%4), %1\n" | ||
455 | " sllx %1, 32, %1\n" | ||
456 | " .word 662b\n" | ||
457 | " or %1, %%lo(%4), %1\n" | ||
458 | " andn %0, %1, %0\n" | ||
459 | " .previous\n" | ||
460 | : "=r" (val), "=r" (tmp) | ||
461 | : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U), | ||
462 | "i" (_PAGE_WRITE_4V | _PAGE_W_4V)); | ||
463 | |||
464 | return __pte(val); | ||
465 | } | ||
466 | |||
467 | static inline pte_t pte_mkold(pte_t pte) | ||
468 | { | ||
469 | unsigned long mask; | ||
470 | |||
471 | __asm__ __volatile__( | ||
472 | "\n661: mov %1, %0\n" | ||
473 | " nop\n" | ||
474 | " .section .sun4v_2insn_patch, \"ax\"\n" | ||
475 | " .word 661b\n" | ||
476 | " sethi %%uhi(%2), %0\n" | ||
477 | " sllx %0, 32, %0\n" | ||
478 | " .previous\n" | ||
479 | : "=r" (mask) | ||
480 | : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); | ||
481 | |||
482 | mask |= _PAGE_R; | ||
483 | |||
484 | return __pte(pte_val(pte) & ~mask); | ||
485 | } | ||
486 | |||
487 | static inline pte_t pte_mkyoung(pte_t pte) | ||
488 | { | ||
489 | unsigned long mask; | ||
490 | |||
491 | __asm__ __volatile__( | ||
492 | "\n661: mov %1, %0\n" | ||
493 | " nop\n" | ||
494 | " .section .sun4v_2insn_patch, \"ax\"\n" | ||
495 | " .word 661b\n" | ||
496 | " sethi %%uhi(%2), %0\n" | ||
497 | " sllx %0, 32, %0\n" | ||
498 | " .previous\n" | ||
499 | : "=r" (mask) | ||
500 | : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); | ||
501 | |||
502 | mask |= _PAGE_R; | ||
503 | |||
504 | return __pte(pte_val(pte) | mask); | ||
505 | } | ||
230 | 506 | ||
231 | #define pte_pfn(x) ((pte_val(x) & _PAGE_PADDR)>>PAGE_SHIFT) | 507 | static inline unsigned long pte_young(pte_t pte) |
232 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | 508 | { |
509 | unsigned long mask; | ||
510 | |||
511 | __asm__ __volatile__( | ||
512 | "\n661: mov %1, %0\n" | ||
513 | " nop\n" | ||
514 | " .section .sun4v_2insn_patch, \"ax\"\n" | ||
515 | " .word 661b\n" | ||
516 | " sethi %%uhi(%2), %0\n" | ||
517 | " sllx %0, 32, %0\n" | ||
518 | " .previous\n" | ||
519 | : "=r" (mask) | ||
520 | : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); | ||
521 | |||
522 | return (pte_val(pte) & mask); | ||
523 | } | ||
524 | |||
525 | static inline unsigned long pte_dirty(pte_t pte) | ||
526 | { | ||
527 | unsigned long mask; | ||
528 | |||
529 | __asm__ __volatile__( | ||
530 | "\n661: mov %1, %0\n" | ||
531 | " nop\n" | ||
532 | " .section .sun4v_2insn_patch, \"ax\"\n" | ||
533 | " .word 661b\n" | ||
534 | " sethi %%uhi(%2), %0\n" | ||
535 | " sllx %0, 32, %0\n" | ||
536 | " .previous\n" | ||
537 | : "=r" (mask) | ||
538 | : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V)); | ||
539 | |||
540 | return (pte_val(pte) & mask); | ||
541 | } | ||
233 | 542 | ||
234 | static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot) | 543 | static inline unsigned long pte_write(pte_t pte) |
235 | { | 544 | { |
236 | pte_t __pte; | 545 | unsigned long mask; |
237 | const unsigned long preserve_mask = (_PFN_MASK | | 546 | |
238 | _PAGE_MODIFIED | _PAGE_ACCESSED | | 547 | __asm__ __volatile__( |
239 | _PAGE_CACHE | _PAGE_E | | 548 | "\n661: mov %1, %0\n" |
240 | _PAGE_PRESENT | _PAGE_SZBITS); | 549 | " nop\n" |
550 | " .section .sun4v_2insn_patch, \"ax\"\n" | ||
551 | " .word 661b\n" | ||
552 | " sethi %%uhi(%2), %0\n" | ||
553 | " sllx %0, 32, %0\n" | ||
554 | " .previous\n" | ||
555 | : "=r" (mask) | ||
556 | : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); | ||
557 | |||
558 | return (pte_val(pte) & mask); | ||
559 | } | ||
241 | 560 | ||
242 | pte_val(__pte) = (pte_val(orig_pte) & preserve_mask) | | 561 | static inline unsigned long pte_exec(pte_t pte) |
243 | (pgprot_val(new_prot) & ~preserve_mask); | 562 | { |
563 | unsigned long mask; | ||
564 | |||
565 | __asm__ __volatile__( | ||
566 | "\n661: sethi %%hi(%1), %0\n" | ||
567 | " .section .sun4v_1insn_patch, \"ax\"\n" | ||
568 | " .word 661b\n" | ||
569 | " mov %2, %0\n" | ||
570 | " .previous\n" | ||
571 | : "=r" (mask) | ||
572 | : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V)); | ||
573 | |||
574 | return (pte_val(pte) & mask); | ||
575 | } | ||
244 | 576 | ||
245 | return __pte; | 577 | static inline unsigned long pte_read(pte_t pte) |
578 | { | ||
579 | unsigned long mask; | ||
580 | |||
581 | __asm__ __volatile__( | ||
582 | "\n661: mov %1, %0\n" | ||
583 | " nop\n" | ||
584 | " .section .sun4v_2insn_patch, \"ax\"\n" | ||
585 | " .word 661b\n" | ||
586 | " sethi %%uhi(%2), %0\n" | ||
587 | " sllx %0, 32, %0\n" | ||
588 | " .previous\n" | ||
589 | : "=r" (mask) | ||
590 | : "i" (_PAGE_READ_4U), "i" (_PAGE_READ_4V)); | ||
591 | |||
592 | return (pte_val(pte) & mask); | ||
246 | } | 593 | } |
594 | |||
595 | static inline unsigned long pte_file(pte_t pte) | ||
596 | { | ||
597 | unsigned long val = pte_val(pte); | ||
598 | |||
599 | __asm__ __volatile__( | ||
600 | "\n661: and %0, %2, %0\n" | ||
601 | " .section .sun4v_1insn_patch, \"ax\"\n" | ||
602 | " .word 661b\n" | ||
603 | " and %0, %3, %0\n" | ||
604 | " .previous\n" | ||
605 | : "=r" (val) | ||
606 | : "0" (val), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V)); | ||
607 | |||
608 | return val; | ||
609 | } | ||
610 | |||
611 | static inline unsigned long pte_present(pte_t pte) | ||
612 | { | ||
613 | unsigned long val = pte_val(pte); | ||
614 | |||
615 | __asm__ __volatile__( | ||
616 | "\n661: and %0, %2, %0\n" | ||
617 | " .section .sun4v_1insn_patch, \"ax\"\n" | ||
618 | " .word 661b\n" | ||
619 | " and %0, %3, %0\n" | ||
620 | " .previous\n" | ||
621 | : "=r" (val) | ||
622 | : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V)); | ||
623 | |||
624 | return val; | ||
625 | } | ||
626 | |||
247 | #define pmd_set(pmdp, ptep) \ | 627 | #define pmd_set(pmdp, ptep) \ |
248 | (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL)) | 628 | (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL)) |
249 | #define pud_set(pudp, pmdp) \ | 629 | #define pud_set(pudp, pmdp) \ |
@@ -253,8 +633,6 @@ static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot) | |||
253 | #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) | 633 | #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) |
254 | #define pud_page(pud) \ | 634 | #define pud_page(pud) \ |
255 | ((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL))) | 635 | ((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL))) |
256 | #define pte_none(pte) (!pte_val(pte)) | ||
257 | #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) | ||
258 | #define pmd_none(pmd) (!pmd_val(pmd)) | 636 | #define pmd_none(pmd) (!pmd_val(pmd)) |
259 | #define pmd_bad(pmd) (0) | 637 | #define pmd_bad(pmd) (0) |
260 | #define pmd_present(pmd) (pmd_val(pmd) != 0U) | 638 | #define pmd_present(pmd) (pmd_val(pmd) != 0U) |
@@ -264,30 +642,8 @@ static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot) | |||
264 | #define pud_present(pud) (pud_val(pud) != 0U) | 642 | #define pud_present(pud) (pud_val(pud) != 0U) |
265 | #define pud_clear(pudp) (pud_val(*(pudp)) = 0U) | 643 | #define pud_clear(pudp) (pud_val(*(pudp)) = 0U) |
266 | 644 | ||
267 | /* The following only work if pte_present() is true. | 645 | /* Same in both SUN4V and SUN4U. */ |
268 | * Undefined behaviour if not.. | 646 | #define pte_none(pte) (!pte_val(pte)) |
269 | */ | ||
270 | #define pte_read(pte) (pte_val(pte) & _PAGE_READ) | ||
271 | #define pte_exec(pte) (pte_val(pte) & _PAGE_EXEC) | ||
272 | #define pte_write(pte) (pte_val(pte) & _PAGE_WRITE) | ||
273 | #define pte_dirty(pte) (pte_val(pte) & _PAGE_MODIFIED) | ||
274 | #define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED) | ||
275 | #define pte_wrprotect(pte) (__pte(pte_val(pte) & ~(_PAGE_WRITE|_PAGE_W))) | ||
276 | #define pte_rdprotect(pte) \ | ||
277 | (__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_READ)) | ||
278 | #define pte_mkclean(pte) \ | ||
279 | (__pte(pte_val(pte) & ~(_PAGE_MODIFIED|_PAGE_W))) | ||
280 | #define pte_mkold(pte) \ | ||
281 | (__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_ACCESSED)) | ||
282 | |||
283 | /* Permanent address of a page. */ | ||
284 | #define __page_address(page) page_address(page) | ||
285 | |||
286 | /* Be very careful when you change these three, they are delicate. */ | ||
287 | #define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_ACCESSED | _PAGE_R)) | ||
288 | #define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_WRITE)) | ||
289 | #define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_MODIFIED | _PAGE_W)) | ||
290 | #define pte_mkhuge(pte) (__pte(pte_val(pte) | _PAGE_SZHUGE)) | ||
291 | 647 | ||
292 | /* to find an entry in a page-table-directory. */ | 648 | /* to find an entry in a page-table-directory. */ |
293 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) | 649 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) |
@@ -296,11 +652,6 @@ static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot) | |||
296 | /* to find an entry in a kernel page-table-directory */ | 652 | /* to find an entry in a kernel page-table-directory */ |
297 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | 653 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) |
298 | 654 | ||
299 | /* extract the pgd cache used for optimizing the tlb miss | ||
300 | * slow path when executing 32-bit compat processes | ||
301 | */ | ||
302 | #define get_pgd_cache(pgd) ((unsigned long) pgd_val(*pgd) << 11) | ||
303 | |||
304 | /* Find an entry in the second-level page table.. */ | 655 | /* Find an entry in the second-level page table.. */ |
305 | #define pmd_offset(pudp, address) \ | 656 | #define pmd_offset(pudp, address) \ |
306 | ((pmd_t *) pud_page(*(pudp)) + \ | 657 | ((pmd_t *) pud_page(*(pudp)) + \ |
@@ -327,6 +678,9 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *p | |||
327 | 678 | ||
328 | /* It is more efficient to let flush_tlb_kernel_range() | 679 | /* It is more efficient to let flush_tlb_kernel_range() |
329 | * handle init_mm tlb flushes. | 680 | * handle init_mm tlb flushes. |
681 | * | ||
682 | * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U | ||
683 | * and SUN4V pte layout, so this inline test is fine. | ||
330 | */ | 684 | */ |
331 | if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID)) | 685 | if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID)) |
332 | tlb_batch_add(mm, addr, ptep, orig); | 686 | tlb_batch_add(mm, addr, ptep, orig); |
@@ -361,42 +715,23 @@ extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); | |||
361 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | 715 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) |
362 | 716 | ||
363 | /* File offset in PTE support. */ | 717 | /* File offset in PTE support. */ |
364 | #define pte_file(pte) (pte_val(pte) & _PAGE_FILE) | 718 | extern unsigned long pte_file(pte_t); |
365 | #define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT) | 719 | #define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT) |
366 | #define pgoff_to_pte(off) (__pte(((off) << PAGE_SHIFT) | _PAGE_FILE)) | 720 | extern pte_t pgoff_to_pte(unsigned long); |
367 | #define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL) | 721 | #define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL) |
368 | 722 | ||
369 | extern unsigned long prom_virt_to_phys(unsigned long, int *); | 723 | extern unsigned long prom_virt_to_phys(unsigned long, int *); |
370 | 724 | ||
371 | static __inline__ unsigned long | 725 | extern unsigned long sun4u_get_pte(unsigned long); |
372 | sun4u_get_pte (unsigned long addr) | ||
373 | { | ||
374 | pgd_t *pgdp; | ||
375 | pud_t *pudp; | ||
376 | pmd_t *pmdp; | ||
377 | pte_t *ptep; | ||
378 | |||
379 | if (addr >= PAGE_OFFSET) | ||
380 | return addr & _PAGE_PADDR; | ||
381 | if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS)) | ||
382 | return prom_virt_to_phys(addr, NULL); | ||
383 | pgdp = pgd_offset_k(addr); | ||
384 | pudp = pud_offset(pgdp, addr); | ||
385 | pmdp = pmd_offset(pudp, addr); | ||
386 | ptep = pte_offset_kernel(pmdp, addr); | ||
387 | return pte_val(*ptep) & _PAGE_PADDR; | ||
388 | } | ||
389 | 726 | ||
390 | static __inline__ unsigned long | 727 | static inline unsigned long __get_phys(unsigned long addr) |
391 | __get_phys (unsigned long addr) | ||
392 | { | 728 | { |
393 | return sun4u_get_pte (addr); | 729 | return sun4u_get_pte(addr); |
394 | } | 730 | } |
395 | 731 | ||
396 | static __inline__ int | 732 | static inline int __get_iospace(unsigned long addr) |
397 | __get_iospace (unsigned long addr) | ||
398 | { | 733 | { |
399 | return ((sun4u_get_pte (addr) & 0xf0000000) >> 28); | 734 | return ((sun4u_get_pte(addr) & 0xf0000000) >> 28); |
400 | } | 735 | } |
401 | 736 | ||
402 | extern unsigned long *sparc64_valid_addr_bitmap; | 737 | extern unsigned long *sparc64_valid_addr_bitmap; |
@@ -409,11 +744,6 @@ extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from, | |||
409 | unsigned long pfn, | 744 | unsigned long pfn, |
410 | unsigned long size, pgprot_t prot); | 745 | unsigned long size, pgprot_t prot); |
411 | 746 | ||
412 | /* Clear virtual and physical cachability, set side-effect bit. */ | ||
413 | #define pgprot_noncached(prot) \ | ||
414 | (__pgprot((pgprot_val(prot) & ~(_PAGE_CP | _PAGE_CV)) | \ | ||
415 | _PAGE_E)) | ||
416 | |||
417 | /* | 747 | /* |
418 | * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in | 748 | * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in |
419 | * its high 4 bits. These macros/functions put it there or get it from there. | 749 | * its high 4 bits. These macros/functions put it there or get it from there. |
@@ -424,8 +754,11 @@ extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from, | |||
424 | 754 | ||
425 | #include <asm-generic/pgtable.h> | 755 | #include <asm-generic/pgtable.h> |
426 | 756 | ||
427 | /* We provide our own get_unmapped_area to cope with VA holes for userland */ | 757 | /* We provide our own get_unmapped_area to cope with VA holes and |
758 | * SHM area cache aliasing for userland. | ||
759 | */ | ||
428 | #define HAVE_ARCH_UNMAPPED_AREA | 760 | #define HAVE_ARCH_UNMAPPED_AREA |
761 | #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN | ||
429 | 762 | ||
430 | /* We provide a special get_unmapped_area for framebuffer mmaps to try and use | 763 | /* We provide a special get_unmapped_area for framebuffer mmaps to try and use |
431 | * the largest alignment possible such that larget PTEs can be used. | 764 | * the largest alignment possible such that larget PTEs can be used. |
@@ -435,12 +768,9 @@ extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, | |||
435 | unsigned long); | 768 | unsigned long); |
436 | #define HAVE_ARCH_FB_UNMAPPED_AREA | 769 | #define HAVE_ARCH_FB_UNMAPPED_AREA |
437 | 770 | ||
438 | /* | 771 | extern void pgtable_cache_init(void); |
439 | * No page table caches to initialise | 772 | extern void sun4v_register_fault_status(void); |
440 | */ | 773 | extern void sun4v_ktsb_register(void); |
441 | #define pgtable_cache_init() do { } while (0) | ||
442 | |||
443 | extern void check_pgt_cache(void); | ||
444 | 774 | ||
445 | #endif /* !(__ASSEMBLY__) */ | 775 | #endif /* !(__ASSEMBLY__) */ |
446 | 776 | ||