1 files changed, 0 insertions, 132 deletions
diff --git a/include/asm-sparc64/pbm.h b/include/asm-sparc64/pbm.h
deleted file mode 100644
index d99e0468c7e4..000000000000
--- a/include/asm-sparc64/pbm.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* pbm.h: UltraSparc PCI controller software state.
- *
- * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
- */
-#ifndef __SPARC64_PBM_H
-#define __SPARC64_PBM_H
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/ioport.h>
-#include <linux/spinlock.h>
-#include <linux/msi.h>
-#include <asm/io.h>
-#include <asm/page.h>
-#include <asm/oplib.h>
-#include <asm/prom.h>
-#include <asm/of_device.h>
-#include <asm/iommu.h>
-/* The abstraction used here is that there are PCI controllers,
- * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
- * underneath.  Each PCI bus module uses an IOMMU (shared by both
- * PBMs of a controller, or per-PBM), and if a streaming buffer
- * is present, each PCI bus module has it's own. (ie. the IOMMU
- * might be shared between PBMs, the STC is never shared)
- * Furthermore, each PCI bus module controls it's own autonomous
- * PCI bus.
- */
-extern void pci_iommu_table_init(struct iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask);
-#define PCI_STC_FLUSHFLAG_INIT(STC) \
-        (*((STC)->strbuf_flushflag) = 0UL)
-#define PCI_STC_FLUSHFLAG_SET(STC) \
-        (*((STC)->strbuf_flushflag) != 0UL)
-struct pci_controller_info;
-struct pci_pbm_info {
-        struct pci_pbm_info             *next;
-        int                             index;
-        /* PCI controller we sit under. */
-        struct pci_controller_info      *parent;
-        /* Physical address base of controller registers. */
-        unsigned long                   controller_regs;
-        /* Physical address base of PBM registers. */
-        unsigned long                   pbm_regs;
-        /* Physical address of DMA sync register, if any.  */
-        unsigned long                   sync_reg;
-        /* Opaque 32-bit system bus Port ID. */
-        u32                             portid;
-        /* Opaque 32-bit handle used for hypervisor calls.  */
-        u32                             devhandle;
-        /* Chipset version information. */
-        int                             chip_type;
-#define PBM_CHIP_TYPE_SABRE             1
-#define PBM_CHIP_TYPE_PSYCHO            2
-#define PBM_CHIP_TYPE_SCHIZO            3
-#define PBM_CHIP_TYPE_SCHIZO_PLUS       4
-#define PBM_CHIP_TYPE_TOMATILLO         5
-        int                             chip_version;
-        int                             chip_revision;
-        /* Name used for top-level resources. */
-        char                            *name;
-        /* OBP specific information. */
-        struct device_node              *prom_node;
-        u64                             ino_bitmap;
-        /* PBM I/O and Memory space resources. */
-        struct resource                 io_space;
-        struct resource                 mem_space;
-        /* Base of PCI Config space, can be per-PBM or shared. */
-        unsigned long                   config_space;
-        /* State of 66MHz capabilities on this PBM. */
-        int                             is_66mhz_capable;
-        int                             all_devs_66mhz;
-#ifdef CONFIG_PCI_MSI
-        /* MSI info.  */
-        u32                             msiq_num;
-        u32                             msiq_ent_count;
-        u32                             msiq_first;
-        u32                             msiq_first_devino;
-        u32                             msi_num;
-        u32                             msi_first;
-        u32                             msi_data_mask;
-        u32                             msix_data_width;
-        u64                             msi32_start;
-        u64                             msi64_start;
-        u32                             msi32_len;
-        u32                             msi64_len;
-        void                            *msi_queues;
-        unsigned long                   *msi_bitmap;
-        int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev,
-                             struct msi_desc *entry);
-        void (*teardown_msi_irq)(unsigned int virt_irq, struct pci_dev *pdev);
-#endif /* !(CONFIG_PCI_MSI) */
-        /* This PBM's streaming buffer. */
-        struct strbuf                   stc;
-        /* IOMMU state, potentially shared by both PBM segments. */
-        struct iommu                    *iommu;
-        /* Now things for the actual PCI bus probes. */
-        unsigned int                    pci_first_busno;
-        unsigned int                    pci_last_busno;
-        struct pci_bus                  *pci_bus;
-        void (*scan_bus)(struct pci_pbm_info *);
-        struct pci_ops                  *pci_ops;
-};
-struct pci_controller_info {
-        /* The PCI bus modules controlled by us. */
-        struct pci_pbm_info             pbm_A;
-        struct pci_pbm_info             pbm_B;
-};
-#endif /* !(__SPARC64_PBM_H) */

diff --git a/include/asm-sparc64/pbm.h b/include/asm-sparc64/pbm.h deleted file mode 100644 index d99e0468c7e4..000000000000 --- a/include/asm-sparc64/pbm.h +++ /dev/null
@@ -1,132 +0,0 @@
1	/* pbm.h: UltraSparc PCI controller software state.
2	*
3	* Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
4	*/
5
6	#ifndef __SPARC64_PBM_H
7	#define __SPARC64_PBM_H
8
9	#include <linux/types.h>
10	#include <linux/pci.h>
11	#include <linux/ioport.h>
12	#include <linux/spinlock.h>
13	#include <linux/msi.h>
14
15	#include <asm/io.h>
16	#include <asm/page.h>
17	#include <asm/oplib.h>
18	#include <asm/prom.h>
19	#include <asm/of_device.h>
20	#include <asm/iommu.h>
21
22	/* The abstraction used here is that there are PCI controllers,
23	* each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
24	* underneath. Each PCI bus module uses an IOMMU (shared by both
25	* PBMs of a controller, or per-PBM), and if a streaming buffer
26	* is present, each PCI bus module has it's own. (ie. the IOMMU
27	* might be shared between PBMs, the STC is never shared)
28	* Furthermore, each PCI bus module controls it's own autonomous
29	* PCI bus.
30	*/
31
32	extern void pci_iommu_table_init(struct iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask);
33
34	#define PCI_STC_FLUSHFLAG_INIT(STC) \
35	(*((STC)->strbuf_flushflag) = 0UL)
36	#define PCI_STC_FLUSHFLAG_SET(STC) \
37	(*((STC)->strbuf_flushflag) != 0UL)
38
39	struct pci_controller_info;
40
41	struct pci_pbm_info {
42	struct pci_pbm_info *next;
43	int index;
44
45	/* PCI controller we sit under. */
46	struct pci_controller_info *parent;
47
48	/* Physical address base of controller registers. */
49	unsigned long controller_regs;
50
51	/* Physical address base of PBM registers. */
52	unsigned long pbm_regs;
53
54	/* Physical address of DMA sync register, if any. */
55	unsigned long sync_reg;
56
57	/* Opaque 32-bit system bus Port ID. */
58	u32 portid;
59
60	/* Opaque 32-bit handle used for hypervisor calls. */
61	u32 devhandle;
62
63	/* Chipset version information. */
64	int chip_type;
65	#define PBM_CHIP_TYPE_SABRE 1
66	#define PBM_CHIP_TYPE_PSYCHO 2
67	#define PBM_CHIP_TYPE_SCHIZO 3
68	#define PBM_CHIP_TYPE_SCHIZO_PLUS 4
69	#define PBM_CHIP_TYPE_TOMATILLO 5
70	int chip_version;
71	int chip_revision;
72
73	/* Name used for top-level resources. */
74	char *name;
75
76	/* OBP specific information. */
77	struct device_node *prom_node;
78	u64 ino_bitmap;
79
80	/* PBM I/O and Memory space resources. */
81	struct resource io_space;
82	struct resource mem_space;
83
84	/* Base of PCI Config space, can be per-PBM or shared. */
85	unsigned long config_space;
86
87	/* State of 66MHz capabilities on this PBM. */
88	int is_66mhz_capable;
89	int all_devs_66mhz;
90
91	#ifdef CONFIG_PCI_MSI
92	/* MSI info. */
93	u32 msiq_num;
94	u32 msiq_ent_count;
95	u32 msiq_first;
96	u32 msiq_first_devino;
97	u32 msi_num;
98	u32 msi_first;
99	u32 msi_data_mask;
100	u32 msix_data_width;
101	u64 msi32_start;
102	u64 msi64_start;
103	u32 msi32_len;
104	u32 msi64_len;
105	void *msi_queues;
106	unsigned long *msi_bitmap;
107	int (setup_msi_irq)(unsigned int virt_irq_p, struct pci_dev *pdev,
108	struct msi_desc *entry);
109	void (teardown_msi_irq)(unsigned int virt_irq, struct pci_dev pdev);
110	#endif /* !(CONFIG_PCI_MSI) */
111
112	/* This PBM's streaming buffer. */
113	struct strbuf stc;
114
115	/* IOMMU state, potentially shared by both PBM segments. */
116	struct iommu *iommu;
117
118	/* Now things for the actual PCI bus probes. */
119	unsigned int pci_first_busno;
120	unsigned int pci_last_busno;
121	struct pci_bus *pci_bus;
122	void (scan_bus)(struct pci_pbm_info );
123	struct pci_ops *pci_ops;
124	};
125
126	struct pci_controller_info {
127	/* The PCI bus modules controlled by us. */
128	struct pci_pbm_info pbm_A;
129	struct pci_pbm_info pbm_B;
130	};
131
132	#endif /* !(__SPARC64_PBM_H) */