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Diffstat (limited to 'include/asm-sparc64/mmu_context.h')
-rw-r--r--include/asm-sparc64/mmu_context.h162
1 files changed, 81 insertions, 81 deletions
diff --git a/include/asm-sparc64/mmu_context.h b/include/asm-sparc64/mmu_context.h
index 57ee7b306189..e7974321d052 100644
--- a/include/asm-sparc64/mmu_context.h
+++ b/include/asm-sparc64/mmu_context.h
@@ -19,96 +19,98 @@ extern unsigned long tlb_context_cache;
19extern unsigned long mmu_context_bmap[]; 19extern unsigned long mmu_context_bmap[];
20 20
21extern void get_new_mmu_context(struct mm_struct *mm); 21extern void get_new_mmu_context(struct mm_struct *mm);
22#ifdef CONFIG_SMP
23extern void smp_new_mmu_context_version(void);
24#else
25#define smp_new_mmu_context_version() do { } while (0)
26#endif
27
28extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
29extern void destroy_context(struct mm_struct *mm);
30
31extern void __tsb_context_switch(unsigned long pgd_pa,
32 unsigned long tsb_reg,
33 unsigned long tsb_vaddr,
34 unsigned long tsb_pte,
35 unsigned long tsb_descr_pa);
36
37static inline void tsb_context_switch(struct mm_struct *mm)
38{
39 __tsb_context_switch(__pa(mm->pgd), mm->context.tsb_reg_val,
40 mm->context.tsb_map_vaddr,
41 mm->context.tsb_map_pte,
42 __pa(&mm->context.tsb_descr));
43}
22 44
23/* Initialize a new mmu context. This is invoked when a new 45extern void tsb_grow(struct mm_struct *mm, unsigned long mm_rss);
24 * address space instance (unique or shared) is instantiated. 46#ifdef CONFIG_SMP
25 * This just needs to set mm->context to an invalid context. 47extern void smp_tsb_sync(struct mm_struct *mm);
26 */ 48#else
27#define init_new_context(__tsk, __mm) \ 49#define smp_tsb_sync(__mm) do { } while (0)
28 (((__mm)->context.sparc64_ctx_val = 0UL), 0) 50#endif
29
30/* Destroy a dead context. This occurs when mmput drops the
31 * mm_users count to zero, the mmaps have been released, and
32 * all the page tables have been flushed. Our job is to destroy
33 * any remaining processor-specific state, and in the sparc64
34 * case this just means freeing up the mmu context ID held by
35 * this task if valid.
36 */
37#define destroy_context(__mm) \
38do { spin_lock(&ctx_alloc_lock); \
39 if (CTX_VALID((__mm)->context)) { \
40 unsigned long nr = CTX_NRBITS((__mm)->context); \
41 mmu_context_bmap[nr>>6] &= ~(1UL << (nr & 63)); \
42 } \
43 spin_unlock(&ctx_alloc_lock); \
44} while(0)
45
46/* Reload the two core values used by TLB miss handler
47 * processing on sparc64. They are:
48 * 1) The physical address of mm->pgd, when full page
49 * table walks are necessary, this is where the
50 * search begins.
51 * 2) A "PGD cache". For 32-bit tasks only pgd[0] is
52 * ever used since that maps the entire low 4GB
53 * completely. To speed up TLB miss processing we
54 * make this value available to the handlers. This
55 * decreases the amount of memory traffic incurred.
56 */
57#define reload_tlbmiss_state(__tsk, __mm) \
58do { \
59 register unsigned long paddr asm("o5"); \
60 register unsigned long pgd_cache asm("o4"); \
61 paddr = __pa((__mm)->pgd); \
62 pgd_cache = 0UL; \
63 if (task_thread_info(__tsk)->flags & _TIF_32BIT) \
64 pgd_cache = get_pgd_cache((__mm)->pgd); \
65 __asm__ __volatile__("wrpr %%g0, 0x494, %%pstate\n\t" \
66 "mov %3, %%g4\n\t" \
67 "mov %0, %%g7\n\t" \
68 "stxa %1, [%%g4] %2\n\t" \
69 "membar #Sync\n\t" \
70 "wrpr %%g0, 0x096, %%pstate" \
71 : /* no outputs */ \
72 : "r" (paddr), "r" (pgd_cache),\
73 "i" (ASI_DMMU), "i" (TSB_REG)); \
74} while(0)
75 51
76/* Set MMU context in the actual hardware. */ 52/* Set MMU context in the actual hardware. */
77#define load_secondary_context(__mm) \ 53#define load_secondary_context(__mm) \
78 __asm__ __volatile__("stxa %0, [%1] %2\n\t" \ 54 __asm__ __volatile__( \
79 "flush %%g6" \ 55 "\n661: stxa %0, [%1] %2\n" \
80 : /* No outputs */ \ 56 " .section .sun4v_1insn_patch, \"ax\"\n" \
81 : "r" (CTX_HWBITS((__mm)->context)), \ 57 " .word 661b\n" \
82 "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU)) 58 " stxa %0, [%1] %3\n" \
59 " .previous\n" \
60 " flush %%g6\n" \
61 : /* No outputs */ \
62 : "r" (CTX_HWBITS((__mm)->context)), \
63 "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU), "i" (ASI_MMU))
83 64
84extern void __flush_tlb_mm(unsigned long, unsigned long); 65extern void __flush_tlb_mm(unsigned long, unsigned long);
85 66
86/* Switch the current MM context. */ 67/* Switch the current MM context. Interrupts are disabled. */
87static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk) 68static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk)
88{ 69{
89 unsigned long ctx_valid; 70 unsigned long ctx_valid, flags;
90 int cpu; 71 int cpu;
91 72
92 /* Note: page_table_lock is used here to serialize switch_mm 73 spin_lock_irqsave(&mm->context.lock, flags);
93 * and activate_mm, and their calls to get_new_mmu_context.
94 * This use of page_table_lock is unrelated to its other uses.
95 */
96 spin_lock(&mm->page_table_lock);
97 ctx_valid = CTX_VALID(mm->context); 74 ctx_valid = CTX_VALID(mm->context);
98 if (!ctx_valid) 75 if (!ctx_valid)
99 get_new_mmu_context(mm); 76 get_new_mmu_context(mm);
100 spin_unlock(&mm->page_table_lock);
101 77
102 if (!ctx_valid || (old_mm != mm)) { 78 /* We have to be extremely careful here or else we will miss
103 load_secondary_context(mm); 79 * a TSB grow if we switch back and forth between a kernel
104 reload_tlbmiss_state(tsk, mm); 80 * thread and an address space which has it's TSB size increased
105 } 81 * on another processor.
82 *
83 * It is possible to play some games in order to optimize the
84 * switch, but the safest thing to do is to unconditionally
85 * perform the secondary context load and the TSB context switch.
86 *
87 * For reference the bad case is, for address space "A":
88 *
89 * CPU 0 CPU 1
90 * run address space A
91 * set cpu0's bits in cpu_vm_mask
92 * switch to kernel thread, borrow
93 * address space A via entry_lazy_tlb
94 * run address space A
95 * set cpu1's bit in cpu_vm_mask
96 * flush_tlb_pending()
97 * reset cpu_vm_mask to just cpu1
98 * TSB grow
99 * run address space A
100 * context was valid, so skip
101 * TSB context switch
102 *
103 * At that point cpu0 continues to use a stale TSB, the one from
104 * before the TSB grow performed on cpu1. cpu1 did not cross-call
105 * cpu0 to update it's TSB because at that point the cpu_vm_mask
106 * only had cpu1 set in it.
107 */
108 load_secondary_context(mm);
109 tsb_context_switch(mm);
106 110
107 /* Even if (mm == old_mm) we _must_ check 111 /* Any time a processor runs a context on an address space
108 * the cpu_vm_mask. If we do not we could 112 * for the first time, we must flush that context out of the
109 * corrupt the TLB state because of how 113 * local TLB.
110 * smp_flush_tlb_{page,range,mm} on sparc64
111 * and lazy tlb switches work. -DaveM
112 */ 114 */
113 cpu = smp_processor_id(); 115 cpu = smp_processor_id();
114 if (!ctx_valid || !cpu_isset(cpu, mm->cpu_vm_mask)) { 116 if (!ctx_valid || !cpu_isset(cpu, mm->cpu_vm_mask)) {
@@ -116,6 +118,7 @@ static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, str
116 __flush_tlb_mm(CTX_HWBITS(mm->context), 118 __flush_tlb_mm(CTX_HWBITS(mm->context),
117 SECONDARY_CONTEXT); 119 SECONDARY_CONTEXT);
118 } 120 }
121 spin_unlock_irqrestore(&mm->context.lock, flags);
119} 122}
120 123
121#define deactivate_mm(tsk,mm) do { } while (0) 124#define deactivate_mm(tsk,mm) do { } while (0)
@@ -123,23 +126,20 @@ static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, str
123/* Activate a new MM instance for the current task. */ 126/* Activate a new MM instance for the current task. */
124static inline void activate_mm(struct mm_struct *active_mm, struct mm_struct *mm) 127static inline void activate_mm(struct mm_struct *active_mm, struct mm_struct *mm)
125{ 128{
129 unsigned long flags;
126 int cpu; 130 int cpu;
127 131
128 /* Note: page_table_lock is used here to serialize switch_mm 132 spin_lock_irqsave(&mm->context.lock, flags);
129 * and activate_mm, and their calls to get_new_mmu_context.
130 * This use of page_table_lock is unrelated to its other uses.
131 */
132 spin_lock(&mm->page_table_lock);
133 if (!CTX_VALID(mm->context)) 133 if (!CTX_VALID(mm->context))
134 get_new_mmu_context(mm); 134 get_new_mmu_context(mm);
135 cpu = smp_processor_id(); 135 cpu = smp_processor_id();
136 if (!cpu_isset(cpu, mm->cpu_vm_mask)) 136 if (!cpu_isset(cpu, mm->cpu_vm_mask))
137 cpu_set(cpu, mm->cpu_vm_mask); 137 cpu_set(cpu, mm->cpu_vm_mask);
138 spin_unlock(&mm->page_table_lock);
139 138
140 load_secondary_context(mm); 139 load_secondary_context(mm);
141 __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT); 140 __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT);
142 reload_tlbmiss_state(current, mm); 141 tsb_context_switch(mm);
142 spin_unlock_irqrestore(&mm->context.lock, flags);
143} 143}
144 144
145#endif /* !(__ASSEMBLY__) */ 145#endif /* !(__ASSEMBLY__) */
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-05 07:44:10 -0500