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-rw-r--r--include/asm-sparc64/io.h512
1 files changed, 1 insertions, 511 deletions
diff --git a/include/asm-sparc64/io.h b/include/asm-sparc64/io.h
index 3158960f3eb5..25ff258dfd33 100644
--- a/include/asm-sparc64/io.h
+++ b/include/asm-sparc64/io.h
@@ -1,511 +1 @@
1#ifndef __SPARC64_IO_H #include <asm-sparc/io.h>
2#define __SPARC64_IO_H
3
4#include <linux/kernel.h>
5#include <linux/compiler.h>
6#include <linux/types.h>
7
8#include <asm/page.h> /* IO address mapping routines need this */
9#include <asm/system.h>
10#include <asm/asi.h>
11
12/* PC crapola... */
13#define __SLOW_DOWN_IO do { } while (0)
14#define SLOW_DOWN_IO do { } while (0)
15
16/* BIO layer definitions. */
17extern unsigned long kern_base, kern_size;
18#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
19#define BIO_VMERGE_BOUNDARY 8192
20
21static inline u8 _inb(unsigned long addr)
22{
23 u8 ret;
24
25 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */"
26 : "=r" (ret)
27 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
28 : "memory");
29
30 return ret;
31}
32
33static inline u16 _inw(unsigned long addr)
34{
35 u16 ret;
36
37 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */"
38 : "=r" (ret)
39 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
40 : "memory");
41
42 return ret;
43}
44
45static inline u32 _inl(unsigned long addr)
46{
47 u32 ret;
48
49 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */"
50 : "=r" (ret)
51 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
52 : "memory");
53
54 return ret;
55}
56
57static inline void _outb(u8 b, unsigned long addr)
58{
59 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */"
60 : /* no outputs */
61 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
62 : "memory");
63}
64
65static inline void _outw(u16 w, unsigned long addr)
66{
67 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */"
68 : /* no outputs */
69 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
70 : "memory");
71}
72
73static inline void _outl(u32 l, unsigned long addr)
74{
75 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */"
76 : /* no outputs */
77 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
78 : "memory");
79}
80
81#define inb(__addr) (_inb((unsigned long)(__addr)))
82#define inw(__addr) (_inw((unsigned long)(__addr)))
83#define inl(__addr) (_inl((unsigned long)(__addr)))
84#define outb(__b, __addr) (_outb((u8)(__b), (unsigned long)(__addr)))
85#define outw(__w, __addr) (_outw((u16)(__w), (unsigned long)(__addr)))
86#define outl(__l, __addr) (_outl((u32)(__l), (unsigned long)(__addr)))
87
88#define inb_p(__addr) inb(__addr)
89#define outb_p(__b, __addr) outb(__b, __addr)
90#define inw_p(__addr) inw(__addr)
91#define outw_p(__w, __addr) outw(__w, __addr)
92#define inl_p(__addr) inl(__addr)
93#define outl_p(__l, __addr) outl(__l, __addr)
94
95extern void outsb(unsigned long, const void *, unsigned long);
96extern void outsw(unsigned long, const void *, unsigned long);
97extern void outsl(unsigned long, const void *, unsigned long);
98extern void insb(unsigned long, void *, unsigned long);
99extern void insw(unsigned long, void *, unsigned long);
100extern void insl(unsigned long, void *, unsigned long);
101
102static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
103{
104 insb((unsigned long __force)port, buf, count);
105}
106static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
107{
108 insw((unsigned long __force)port, buf, count);
109}
110
111static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
112{
113 insl((unsigned long __force)port, buf, count);
114}
115
116static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
117{
118 outsb((unsigned long __force)port, buf, count);
119}
120
121static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
122{
123 outsw((unsigned long __force)port, buf, count);
124}
125
126static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
127{
128 outsl((unsigned long __force)port, buf, count);
129}
130
131/* Memory functions, same as I/O accesses on Ultra. */
132static inline u8 _readb(const volatile void __iomem *addr)
133{ u8 ret;
134
135 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
136 : "=r" (ret)
137 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
138 : "memory");
139 return ret;
140}
141
142static inline u16 _readw(const volatile void __iomem *addr)
143{ u16 ret;
144
145 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
146 : "=r" (ret)
147 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
148 : "memory");
149
150 return ret;
151}
152
153static inline u32 _readl(const volatile void __iomem *addr)
154{ u32 ret;
155
156 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
157 : "=r" (ret)
158 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
159 : "memory");
160
161 return ret;
162}
163
164static inline u64 _readq(const volatile void __iomem *addr)
165{ u64 ret;
166
167 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
168 : "=r" (ret)
169 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
170 : "memory");
171
172 return ret;
173}
174
175static inline void _writeb(u8 b, volatile void __iomem *addr)
176{
177 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
178 : /* no outputs */
179 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
180 : "memory");
181}
182
183static inline void _writew(u16 w, volatile void __iomem *addr)
184{
185 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
186 : /* no outputs */
187 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
188 : "memory");
189}
190
191static inline void _writel(u32 l, volatile void __iomem *addr)
192{
193 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
194 : /* no outputs */
195 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
196 : "memory");
197}
198
199static inline void _writeq(u64 q, volatile void __iomem *addr)
200{
201 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
202 : /* no outputs */
203 : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
204 : "memory");
205}
206
207#define readb(__addr) _readb(__addr)
208#define readw(__addr) _readw(__addr)
209#define readl(__addr) _readl(__addr)
210#define readq(__addr) _readq(__addr)
211#define readb_relaxed(__addr) _readb(__addr)
212#define readw_relaxed(__addr) _readw(__addr)
213#define readl_relaxed(__addr) _readl(__addr)
214#define readq_relaxed(__addr) _readq(__addr)
215#define writeb(__b, __addr) _writeb(__b, __addr)
216#define writew(__w, __addr) _writew(__w, __addr)
217#define writel(__l, __addr) _writel(__l, __addr)
218#define writeq(__q, __addr) _writeq(__q, __addr)
219
220/* Now versions without byte-swapping. */
221static inline u8 _raw_readb(unsigned long addr)
222{
223 u8 ret;
224
225 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
226 : "=r" (ret)
227 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
228
229 return ret;
230}
231
232static inline u16 _raw_readw(unsigned long addr)
233{
234 u16 ret;
235
236 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
237 : "=r" (ret)
238 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
239
240 return ret;
241}
242
243static inline u32 _raw_readl(unsigned long addr)
244{
245 u32 ret;
246
247 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
248 : "=r" (ret)
249 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
250
251 return ret;
252}
253
254static inline u64 _raw_readq(unsigned long addr)
255{
256 u64 ret;
257
258 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
259 : "=r" (ret)
260 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
261
262 return ret;
263}
264
265static inline void _raw_writeb(u8 b, unsigned long addr)
266{
267 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
268 : /* no outputs */
269 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
270}
271
272static inline void _raw_writew(u16 w, unsigned long addr)
273{
274 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
275 : /* no outputs */
276 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
277}
278
279static inline void _raw_writel(u32 l, unsigned long addr)
280{
281 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
282 : /* no outputs */
283 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
284}
285
286static inline void _raw_writeq(u64 q, unsigned long addr)
287{
288 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
289 : /* no outputs */
290 : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
291}
292
293#define __raw_readb(__addr) (_raw_readb((unsigned long)(__addr)))
294#define __raw_readw(__addr) (_raw_readw((unsigned long)(__addr)))
295#define __raw_readl(__addr) (_raw_readl((unsigned long)(__addr)))
296#define __raw_readq(__addr) (_raw_readq((unsigned long)(__addr)))
297#define __raw_writeb(__b, __addr) (_raw_writeb((u8)(__b), (unsigned long)(__addr)))
298#define __raw_writew(__w, __addr) (_raw_writew((u16)(__w), (unsigned long)(__addr)))
299#define __raw_writel(__l, __addr) (_raw_writel((u32)(__l), (unsigned long)(__addr)))
300#define __raw_writeq(__q, __addr) (_raw_writeq((u64)(__q), (unsigned long)(__addr)))
301
302/* Valid I/O Space regions are anywhere, because each PCI bus supported
303 * can live in an arbitrary area of the physical address range.
304 */
305#define IO_SPACE_LIMIT 0xffffffffffffffffUL
306
307/* Now, SBUS variants, only difference from PCI is that we do
308 * not use little-endian ASIs.
309 */
310static inline u8 _sbus_readb(const volatile void __iomem *addr)
311{
312 u8 ret;
313
314 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* sbus_readb */"
315 : "=r" (ret)
316 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
317 : "memory");
318
319 return ret;
320}
321
322static inline u16 _sbus_readw(const volatile void __iomem *addr)
323{
324 u16 ret;
325
326 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* sbus_readw */"
327 : "=r" (ret)
328 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
329 : "memory");
330
331 return ret;
332}
333
334static inline u32 _sbus_readl(const volatile void __iomem *addr)
335{
336 u32 ret;
337
338 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* sbus_readl */"
339 : "=r" (ret)
340 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
341 : "memory");
342
343 return ret;
344}
345
346static inline u64 _sbus_readq(const volatile void __iomem *addr)
347{
348 u64 ret;
349
350 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* sbus_readq */"
351 : "=r" (ret)
352 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
353 : "memory");
354
355 return ret;
356}
357
358static inline void _sbus_writeb(u8 b, volatile void __iomem *addr)
359{
360 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */"
361 : /* no outputs */
362 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
363 : "memory");
364}
365
366static inline void _sbus_writew(u16 w, volatile void __iomem *addr)
367{
368 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */"
369 : /* no outputs */
370 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
371 : "memory");
372}
373
374static inline void _sbus_writel(u32 l, volatile void __iomem *addr)
375{
376 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */"
377 : /* no outputs */
378 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
379 : "memory");
380}
381
382static inline void _sbus_writeq(u64 l, volatile void __iomem *addr)
383{
384 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */"
385 : /* no outputs */
386 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
387 : "memory");
388}
389
390#define sbus_readb(__addr) _sbus_readb(__addr)
391#define sbus_readw(__addr) _sbus_readw(__addr)
392#define sbus_readl(__addr) _sbus_readl(__addr)
393#define sbus_readq(__addr) _sbus_readq(__addr)
394#define sbus_writeb(__b, __addr) _sbus_writeb(__b, __addr)
395#define sbus_writew(__w, __addr) _sbus_writew(__w, __addr)
396#define sbus_writel(__l, __addr) _sbus_writel(__l, __addr)
397#define sbus_writeq(__l, __addr) _sbus_writeq(__l, __addr)
398
399static inline void _sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
400{
401 while(n--) {
402 sbus_writeb(c, dst);
403 dst++;
404 }
405}
406
407#define sbus_memset_io(d,c,sz) _sbus_memset_io(d,c,sz)
408
409static inline void
410_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
411{
412 volatile void __iomem *d = dst;
413
414 while (n--) {
415 writeb(c, d);
416 d++;
417 }
418}
419
420#define memset_io(d,c,sz) _memset_io(d,c,sz)
421
422static inline void
423_memcpy_fromio(void *dst, const volatile void __iomem *src, __kernel_size_t n)
424{
425 char *d = dst;
426
427 while (n--) {
428 char tmp = readb(src);
429 *d++ = tmp;
430 src++;
431 }
432}
433
434#define memcpy_fromio(d,s,sz) _memcpy_fromio(d,s,sz)
435
436static inline void
437_memcpy_toio(volatile void __iomem *dst, const void *src, __kernel_size_t n)
438{
439 const char *s = src;
440 volatile void __iomem *d = dst;
441
442 while (n--) {
443 char tmp = *s++;
444 writeb(tmp, d);
445 d++;
446 }
447}
448
449#define memcpy_toio(d,s,sz) _memcpy_toio(d,s,sz)
450
451#define mmiowb()
452
453#ifdef __KERNEL__
454
455/* On sparc64 we have the whole physical IO address space accessible
456 * using physically addressed loads and stores, so this does nothing.
457 */
458static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
459{
460 return (void __iomem *)offset;
461}
462
463#define ioremap_nocache(X,Y) ioremap((X),(Y))
464
465static inline void iounmap(volatile void __iomem *addr)
466{
467}
468
469#define ioread8(X) readb(X)
470#define ioread16(X) readw(X)
471#define ioread32(X) readl(X)
472#define iowrite8(val,X) writeb(val,X)
473#define iowrite16(val,X) writew(val,X)
474#define iowrite32(val,X) writel(val,X)
475
476/* Create a virtual mapping cookie for an IO port range */
477extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
478extern void ioport_unmap(void __iomem *);
479
480/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
481struct pci_dev;
482extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
483extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
484
485/* Similarly for SBUS. */
486#define sbus_ioremap(__res, __offset, __size, __name) \
487({ unsigned long __ret; \
488 __ret = (__res)->start + (((__res)->flags & 0x1ffUL) << 32UL); \
489 __ret += (unsigned long) (__offset); \
490 if (! request_region((__ret), (__size), (__name))) \
491 __ret = 0UL; \
492 (void __iomem *) __ret; \
493})
494
495#define sbus_iounmap(__addr, __size) \
496 release_region((unsigned long)(__addr), (__size))
497
498/*
499 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
500 * access
501 */
502#define xlate_dev_mem_ptr(p) __va(p)
503
504/*
505 * Convert a virtual cached pointer to an uncached pointer
506 */
507#define xlate_dev_kmem_ptr(p) p
508
509#endif
510
511#endif /* !(__SPARC64_IO_H) */
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