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-rw-r--r--include/asm-sparc64/cpudata.h203
1 files changed, 193 insertions, 10 deletions
diff --git a/include/asm-sparc64/cpudata.h b/include/asm-sparc64/cpudata.h
index 74de79dca915..c66a81bbc84d 100644
--- a/include/asm-sparc64/cpudata.h
+++ b/include/asm-sparc64/cpudata.h
@@ -1,41 +1,224 @@
1/* cpudata.h: Per-cpu parameters. 1/* cpudata.h: Per-cpu parameters.
2 * 2 *
3 * Copyright (C) 2003, 2005 David S. Miller (davem@redhat.com) 3 * Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net)
4 */ 4 */
5 5
6#ifndef _SPARC64_CPUDATA_H 6#ifndef _SPARC64_CPUDATA_H
7#define _SPARC64_CPUDATA_H 7#define _SPARC64_CPUDATA_H
8 8
9#include <asm/hypervisor.h>
10#include <asm/asi.h>
11
12#ifndef __ASSEMBLY__
13
9#include <linux/percpu.h> 14#include <linux/percpu.h>
15#include <linux/threads.h>
10 16
11typedef struct { 17typedef struct {
12 /* Dcache line 1 */ 18 /* Dcache line 1 */
13 unsigned int __softirq_pending; /* must be 1st, see rtrap.S */ 19 unsigned int __softirq_pending; /* must be 1st, see rtrap.S */
14 unsigned int multiplier; 20 unsigned int multiplier;
15 unsigned int counter; 21 unsigned int counter;
16 unsigned int idle_volume; 22 unsigned int __pad1;
17 unsigned long clock_tick; /* %tick's per second */ 23 unsigned long clock_tick; /* %tick's per second */
18 unsigned long udelay_val; 24 unsigned long udelay_val;
19 25
20 /* Dcache line 2 */ 26 /* Dcache line 2, rarely used */
21 unsigned int pgcache_size;
22 unsigned int __pad1;
23 unsigned long *pte_cache[2];
24 unsigned long *pgd_cache;
25
26 /* Dcache line 3, rarely used */
27 unsigned int dcache_size; 27 unsigned int dcache_size;
28 unsigned int dcache_line_size; 28 unsigned int dcache_line_size;
29 unsigned int icache_size; 29 unsigned int icache_size;
30 unsigned int icache_line_size; 30 unsigned int icache_line_size;
31 unsigned int ecache_size; 31 unsigned int ecache_size;
32 unsigned int ecache_line_size; 32 unsigned int ecache_line_size;
33 unsigned int __pad2;
34 unsigned int __pad3; 33 unsigned int __pad3;
34 unsigned int __pad4;
35} cpuinfo_sparc; 35} cpuinfo_sparc;
36 36
37DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data); 37DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
38#define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu)) 38#define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu))
39#define local_cpu_data() __get_cpu_var(__cpu_data) 39#define local_cpu_data() __get_cpu_var(__cpu_data)
40 40
41/* Trap handling code needs to get at a few critical values upon
42 * trap entry and to process TSB misses. These cannot be in the
43 * per_cpu() area as we really need to lock them into the TLB and
44 * thus make them part of the main kernel image. As a result we
45 * try to make this as small as possible.
46 *
47 * This is padded out and aligned to 64-bytes to avoid false sharing
48 * on SMP.
49 */
50
51/* If you modify the size of this structure, please update
52 * TRAP_BLOCK_SZ_SHIFT below.
53 */
54struct thread_info;
55struct trap_per_cpu {
56/* D-cache line 1: Basic thread information, cpu and device mondo queues */
57 struct thread_info *thread;
58 unsigned long pgd_paddr;
59 unsigned long cpu_mondo_pa;
60 unsigned long dev_mondo_pa;
61
62/* D-cache line 2: Error Mondo Queue and kernel buffer pointers */
63 unsigned long resum_mondo_pa;
64 unsigned long resum_kernel_buf_pa;
65 unsigned long nonresum_mondo_pa;
66 unsigned long nonresum_kernel_buf_pa;
67
68/* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */
69 struct hv_fault_status fault_info;
70
71/* Dcache line 7: Physical addresses of CPU send mondo block and CPU list. */
72 unsigned long cpu_mondo_block_pa;
73 unsigned long cpu_list_pa;
74 unsigned long __pad1[2];
75
76/* Dcache line 8: Unused, needed to keep trap_block a power-of-2 in size. */
77 unsigned long __pad2[4];
78} __attribute__((aligned(64)));
79extern struct trap_per_cpu trap_block[NR_CPUS];
80extern void init_cur_cpu_trap(struct thread_info *);
81extern void setup_tba(void);
82
83struct cpuid_patch_entry {
84 unsigned int addr;
85 unsigned int cheetah_safari[4];
86 unsigned int cheetah_jbus[4];
87 unsigned int starfire[4];
88 unsigned int sun4v[4];
89};
90extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
91
92struct sun4v_1insn_patch_entry {
93 unsigned int addr;
94 unsigned int insn;
95};
96extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
97 __sun4v_1insn_patch_end;
98
99struct sun4v_2insn_patch_entry {
100 unsigned int addr;
101 unsigned int insns[2];
102};
103extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
104 __sun4v_2insn_patch_end;
105
106#endif /* !(__ASSEMBLY__) */
107
108#define TRAP_PER_CPU_THREAD 0x00
109#define TRAP_PER_CPU_PGD_PADDR 0x08
110#define TRAP_PER_CPU_CPU_MONDO_PA 0x10
111#define TRAP_PER_CPU_DEV_MONDO_PA 0x18
112#define TRAP_PER_CPU_RESUM_MONDO_PA 0x20
113#define TRAP_PER_CPU_RESUM_KBUF_PA 0x28
114#define TRAP_PER_CPU_NONRESUM_MONDO_PA 0x30
115#define TRAP_PER_CPU_NONRESUM_KBUF_PA 0x38
116#define TRAP_PER_CPU_FAULT_INFO 0x40
117#define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA 0xc0
118#define TRAP_PER_CPU_CPU_LIST_PA 0xc8
119
120#define TRAP_BLOCK_SZ_SHIFT 8
121
122#include <asm/scratchpad.h>
123
124#define __GET_CPUID(REG) \
125 /* Spitfire implementation (default). */ \
126661: ldxa [%g0] ASI_UPA_CONFIG, REG; \
127 srlx REG, 17, REG; \
128 and REG, 0x1f, REG; \
129 nop; \
130 .section .cpuid_patch, "ax"; \
131 /* Instruction location. */ \
132 .word 661b; \
133 /* Cheetah Safari implementation. */ \
134 ldxa [%g0] ASI_SAFARI_CONFIG, REG; \
135 srlx REG, 17, REG; \
136 and REG, 0x3ff, REG; \
137 nop; \
138 /* Cheetah JBUS implementation. */ \
139 ldxa [%g0] ASI_JBUS_CONFIG, REG; \
140 srlx REG, 17, REG; \
141 and REG, 0x1f, REG; \
142 nop; \
143 /* Starfire implementation. */ \
144 sethi %hi(0x1fff40000d0 >> 9), REG; \
145 sllx REG, 9, REG; \
146 or REG, 0xd0, REG; \
147 lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\
148 /* sun4v implementation. */ \
149 mov SCRATCHPAD_CPUID, REG; \
150 ldxa [REG] ASI_SCRATCHPAD, REG; \
151 nop; \
152 nop; \
153 .previous;
154
155#ifdef CONFIG_SMP
156
157#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
158 __GET_CPUID(TMP) \
159 sethi %hi(trap_block), DEST; \
160 sllx TMP, TRAP_BLOCK_SZ_SHIFT, TMP; \
161 or DEST, %lo(trap_block), DEST; \
162 add DEST, TMP, DEST; \
163
164/* Clobbers TMP, current address space PGD phys address into DEST. */
165#define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
166 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
167 ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
168
169/* Clobbers TMP, loads local processor's IRQ work area into DEST. */
170#define TRAP_LOAD_IRQ_WORK(DEST, TMP) \
171 __GET_CPUID(TMP) \
172 sethi %hi(__irq_work), DEST; \
173 sllx TMP, 6, TMP; \
174 or DEST, %lo(__irq_work), DEST; \
175 add DEST, TMP, DEST;
176
177/* Clobbers TMP, loads DEST with current thread info pointer. */
178#define TRAP_LOAD_THREAD_REG(DEST, TMP) \
179 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
180 ldx [DEST + TRAP_PER_CPU_THREAD], DEST;
181
182/* Given the current thread info pointer in THR, load the per-cpu
183 * area base of the current processor into DEST. REG1, REG2, and REG3 are
184 * clobbered.
185 *
186 * You absolutely cannot use DEST as a temporary in this code. The
187 * reason is that traps can happen during execution, and return from
188 * trap will load the fully resolved DEST per-cpu base. This can corrupt
189 * the calculations done by the macro mid-stream.
190 */
191#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \
192 ldub [THR + TI_CPU], REG1; \
193 sethi %hi(__per_cpu_shift), REG3; \
194 sethi %hi(__per_cpu_base), REG2; \
195 ldx [REG3 + %lo(__per_cpu_shift)], REG3; \
196 ldx [REG2 + %lo(__per_cpu_base)], REG2; \
197 sllx REG1, REG3, REG3; \
198 add REG3, REG2, DEST;
199
200#else
201
202#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
203 sethi %hi(trap_block), DEST; \
204 or DEST, %lo(trap_block), DEST; \
205
206/* Uniprocessor versions, we know the cpuid is zero. */
207#define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
208 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
209 ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
210
211#define TRAP_LOAD_IRQ_WORK(DEST, TMP) \
212 sethi %hi(__irq_work), DEST; \
213 or DEST, %lo(__irq_work), DEST;
214
215#define TRAP_LOAD_THREAD_REG(DEST, TMP) \
216 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
217 ldx [DEST + TRAP_PER_CPU_THREAD], DEST;
218
219/* No per-cpu areas on uniprocessor, so no need to load DEST. */
220#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
221
222#endif /* !(CONFIG_SMP) */
223
41#endif /* _SPARC64_CPUDATA_H */ 224#endif /* _SPARC64_CPUDATA_H */
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