1 files changed, 242 insertions, 0 deletions
diff --git a/include/asm-sparc64/chafsr.h b/include/asm-sparc64/chafsr.h
new file mode 100644
index 000000000000..fd1688335ace
--- /dev/null
+++ b/include/asm-sparc64/chafsr.h
@@ -0,0 +1,242 @@
+/* $Id: chafsr.h,v 1.1 2001/03/28 10:56:34 davem Exp $ */
+#ifndef _SPARC64_CHAFSR_H
+#define _SPARC64_CHAFSR_H
+/* Cheetah Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */
+/* Comments indicate which processor variants on which the bit definition
+ * is valid.  Codes are:
+ * ch   -->     cheetah
+ * ch+  -->     cheetah plus
+ * jp   -->     jalapeno
+ */
+/* All bits of this register except M_SYNDROME and E_SYNDROME are
+ * read, write 1 to clear.  M_SYNDROME and E_SYNDROME are read-only.
+ */
+/* Software bit set by linux trap handlers to indicate that the trap was
+ * signalled at %tl >= 1.
+ */
+#define CHAFSR_TL1              (1UL << 63UL) /* n/a */
+/* Unmapped error from system bus for prefetch queue or
+ * store queue read operation
+ */
+#define CHPAFSR_DTO             (1UL << 59UL) /* ch+ */
+/* Bus error from system bus for prefetch queue or store queue
+ * read operation
+ */
+#define CHPAFSR_DBERR           (1UL << 58UL) /* ch+ */
+/* Hardware corrected E-cache Tag ECC error */
+#define CHPAFSR_THCE            (1UL << 57UL) /* ch+ */
+/* System interface protocol error, hw timeout caused */
+#define JPAFSR_JETO             (1UL << 57UL) /* jp */
+/* SW handled correctable E-cache Tag ECC error */
+#define CHPAFSR_TSCE            (1UL << 56UL) /* ch+ */
+/* Parity error on system snoop results */
+#define JPAFSR_SCE              (1UL << 56UL) /* jp */
+/* Uncorrectable E-cache Tag ECC error */
+#define CHPAFSR_TUE             (1UL << 55UL) /* ch+ */
+/* System interface protocol error, illegal command detected */
+#define JPAFSR_JEIC             (1UL << 55UL) /* jp */
+/* Uncorrectable system bus data ECC error due to prefetch
+ * or store fill request
+ */
+#define CHPAFSR_DUE             (1UL << 54UL) /* ch+ */
+/* System interface protocol error, illegal ADTYPE detected */
+#define JPAFSR_JEIT             (1UL << 54UL) /* jp */
+/* Multiple errors of the same type have occurred.  This bit is set when
+ * an uncorrectable error or a SW correctable error occurs and the status
+ * bit to report that error is already set.  When multiple errors of
+ * different types are indicated by setting multiple status bits.
+ *
+ * This bit is not set if multiple HW corrected errors with the same
+ * status bit occur, only uncorrectable and SW correctable ones have
+ * this behavior.
+ *
+ * This bit is not set when multiple ECC errors happen within a single
+ * 64-byte system bus transaction.  Only the first ECC error in a 16-byte
+ * subunit will be logged.  All errors in subsequent 16-byte subunits
+ * from the same 64-byte transaction are ignored.
+ */
+#define CHAFSR_ME               (1UL << 53UL) /* ch,ch+,jp */
+/* Privileged state error has occurred.  This is a capture of PSTATE.PRIV
+ * at the time the error is detected.
+ */
+#define CHAFSR_PRIV             (1UL << 52UL) /* ch,ch+,jp */
+/* The following bits 51 (CHAFSR_PERR) to 33 (CHAFSR_CE) are sticky error
+ * bits and record the most recently detected errors.  Bits accumulate
+ * errors that have been detected since the last write to clear the bit.
+ */
+/* System interface protocol error.  The processor asserts its' ERROR
+ * pin when this event occurs and it also logs a specific cause code
+ * into a JTAG scannable flop.
+ */
+#define CHAFSR_PERR             (1UL << 51UL) /* ch,ch+,jp */
+/* Internal processor error.  The processor asserts its' ERROR
+ * pin when this event occurs and it also logs a specific cause code
+ * into a JTAG scannable flop.
+ */
+#define CHAFSR_IERR             (1UL << 50UL) /* ch,ch+,jp */
+/* System request parity error on incoming address */
+#define CHAFSR_ISAP             (1UL << 49UL) /* ch,ch+,jp */
+/* HW Corrected system bus MTAG ECC error */
+#define CHAFSR_EMC              (1UL << 48UL) /* ch,ch+ */
+/* Parity error on L2 cache tag SRAM */
+#define JPAFSR_ETP              (1UL << 48UL) /* jp */
+/* Uncorrectable system bus MTAG ECC error */
+#define CHAFSR_EMU              (1UL << 47UL) /* ch,ch+ */
+/* Out of range memory error has occurred */
+#define JPAFSR_OM               (1UL << 47UL) /* jp */
+/* HW Corrected system bus data ECC error for read of interrupt vector */
+#define CHAFSR_IVC              (1UL << 46UL) /* ch,ch+ */
+/* Error due to unsupported store */
+#define JPAFSR_UMS              (1UL << 46UL) /* jp */
+/* Uncorrectable system bus data ECC error for read of interrupt vector */
+#define CHAFSR_IVU              (1UL << 45UL) /* ch,ch+,jp */
+/* Unmapped error from system bus */
+#define CHAFSR_TO               (1UL << 44UL) /* ch,ch+,jp */
+/* Bus error response from system bus */
+#define CHAFSR_BERR             (1UL << 43UL) /* ch,ch+,jp */
+/* SW Correctable E-cache ECC error for instruction fetch or data access
+ * other than block load.
+ */
+#define CHAFSR_UCC              (1UL << 42UL) /* ch,ch+,jp */
+/* Uncorrectable E-cache ECC error for instruction fetch or data access
+ * other than block load.
+ */
+#define CHAFSR_UCU              (1UL << 41UL) /* ch,ch+,jp */
+/* Copyout HW Corrected ECC error */
+#define CHAFSR_CPC              (1UL << 40UL) /* ch,ch+,jp */
+/* Copyout Uncorrectable ECC error */
+#define CHAFSR_CPU              (1UL << 39UL) /* ch,ch+,jp */
+/* HW Corrected ECC error from E-cache for writeback */
+#define CHAFSR_WDC              (1UL << 38UL) /* ch,ch+,jp */
+/* Uncorrectable ECC error from E-cache for writeback */
+#define CHAFSR_WDU              (1UL << 37UL) /* ch,ch+,jp */
+/* HW Corrected ECC error from E-cache for store merge or block load */
+#define CHAFSR_EDC              (1UL << 36UL) /* ch,ch+,jp */
+/* Uncorrectable ECC error from E-cache for store merge or block load */
+#define CHAFSR_EDU              (1UL << 35UL) /* ch,ch+,jp */
+/* Uncorrectable system bus data ECC error for read of memory or I/O */
+#define CHAFSR_UE               (1UL << 34UL) /* ch,ch+,jp */
+/* HW Corrected system bus data ECC error for read of memory or I/O */
+#define CHAFSR_CE               (1UL << 33UL) /* ch,ch+,jp */
+/* Uncorrectable ECC error from remote cache/memory */
+#define JPAFSR_RUE              (1UL << 32UL) /* jp */
+/* Correctable ECC error from remote cache/memory */
+#define JPAFSR_RCE              (1UL << 31UL) /* jp */
+/* JBUS parity error on returned read data */
+#define JPAFSR_BP               (1UL << 30UL) /* jp */
+/* JBUS parity error on data for writeback or block store */
+#define JPAFSR_WBP              (1UL << 29UL) /* jp */
+/* Foreign read to DRAM incurring correctable ECC error */
+#define JPAFSR_FRC              (1UL << 28UL) /* jp */
+/* Foreign read to DRAM incurring uncorrectable ECC error */
+#define JPAFSR_FRU              (1UL << 27UL) /* jp */
+#define CHAFSR_ERRORS           (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \
+                                 CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \
+                                 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \
+                                 CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \
+                                 CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE)
+#define CHPAFSR_ERRORS          (CHPAFSR_DTO | CHPAFSR_DBERR | CHPAFSR_THCE | \
+                                 CHPAFSR_TSCE | CHPAFSR_TUE | CHPAFSR_DUE | \
+                                 CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \
+                                 CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \
+                                 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \
+                                 CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \
+                                 CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE)
+#define JPAFSR_ERRORS           (JPAFSR_JETO | JPAFSR_SCE | JPAFSR_JEIC | \
+                                 JPAFSR_JEIT | CHAFSR_PERR | CHAFSR_IERR | \
+                                 CHAFSR_ISAP | JPAFSR_ETP | JPAFSR_OM | \
+                                 JPAFSR_UMS | CHAFSR_IVU | CHAFSR_TO | \
+                                 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | \
+                                 CHAFSR_CPC | CHAFSR_CPU | CHAFSR_WDC | \
+                                 CHAFSR_WDU | CHAFSR_EDC | CHAFSR_EDU | \
+                                 CHAFSR_UE | CHAFSR_CE | JPAFSR_RUE | \
+                                 JPAFSR_RCE | JPAFSR_BP | JPAFSR_WBP | \
+                                 JPAFSR_FRC | JPAFSR_FRU)
+/* Active JBUS request signal when error occurred */
+#define JPAFSR_JBREQ            (0x7UL << 24UL) /* jp */
+#define JPAFSR_JBREQ_SHIFT      24UL
+/* L2 cache way information */
+#define JPAFSR_ETW              (0x3UL << 22UL) /* jp */
+#define JPAFSR_ETW_SHIFT        22UL
+/* System bus MTAG ECC syndrome.  This field captures the status of the
+ * first occurrence of the highest-priority error according to the M_SYND
+ * overwrite policy.  After the AFSR sticky bit, corresponding to the error
+ * for which the M_SYND is reported, is cleared, the contents of the M_SYND
+ * field will be unchanged by will be unfrozen for further error capture.
+ */
+#define CHAFSR_M_SYNDROME       (0xfUL << 16UL) /* ch,ch+,jp */
+#define CHAFSR_M_SYNDROME_SHIFT 16UL
+/* Agenid Id of the foreign device causing the UE/CE errors */
+#define JPAFSR_AID              (0x1fUL << 9UL) /* jp */
+#define JPAFSR_AID_SHIFT        9UL
+/* System bus or E-cache data ECC syndrome.  This field captures the status
+ * of the first occurrence of the highest-priority error according to the
+ * E_SYND overwrite policy.  After the AFSR sticky bit, corresponding to the
+ * error for which the E_SYND is reported, is cleare, the contents of the E_SYND
+ * field will be unchanged but will be unfrozen for further error capture.
+ */
+#define CHAFSR_E_SYNDROME       (0x1ffUL << 0UL) /* ch,ch+,jp */
+#define CHAFSR_E_SYNDROME_SHIFT 0UL
+/* The AFSR must be explicitly cleared by software, it is not cleared automatically
+ * by a read.  Writes to bits <51:33> with bits set will clear the corresponding
+ * bits in the AFSR.  Bits associated with disrupting traps must be cleared before
+ * interrupts are re-enabled to prevent multiple traps for the same error.  I.e.
+ * PSTATE.IE and AFSR bits control delivery of disrupting traps.
+ *
+ * Since there is only one AFAR, when multiple events have been logged by the
+ * bits in the AFSR, at most one of these events will have its status captured
+ * in the AFAR.  The highest priority of those event bits will get AFAR logging.
+ * The AFAR will be unlocked and available to capture the address of another event
+ * as soon as the one bit in AFSR that corresponds to the event logged in AFAR is
+ * cleared.  For example, if AFSR.CE is detected, then AFSR.UE (which overwrites
+ * the AFAR), and AFSR.UE is cleared by not AFSR.CE, then the AFAR will be unlocked
+ * and ready for another event, even though AFSR.CE is still set.  The same rules
+ * also apply to the M_SYNDROME and E_SYNDROME fields of the AFSR.
+ */
+#endif /* _SPARC64_CHAFSR_H */

diff --git a/include/asm-sparc64/chafsr.h b/include/asm-sparc64/chafsr.h new file mode 100644 index 000000000000..fd1688335ace --- /dev/null +++ b/include/asm-sparc64/chafsr.h
@@ -0,0 +1,242 @@
	1	/* $Id: chafsr.h,v 1.1 2001/03/28 10:56:34 davem Exp $ */
	2	#ifndef _SPARC64_CHAFSR_H
	3	#define _SPARC64_CHAFSR_H
	4
	5	/* Cheetah Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */
	6
	7	/* Comments indicate which processor variants on which the bit definition
	8	* is valid. Codes are:
	9	* ch --> cheetah
	10	* ch+ --> cheetah plus
	11	* jp --> jalapeno
	12	*/
	13
	14	/* All bits of this register except M_SYNDROME and E_SYNDROME are
	15	* read, write 1 to clear. M_SYNDROME and E_SYNDROME are read-only.
	16	*/
	17
	18	/* Software bit set by linux trap handlers to indicate that the trap was
	19	* signalled at %tl >= 1.
	20	*/
	21	#define CHAFSR_TL1 (1UL << 63UL) /* n/a */
	22
	23	/* Unmapped error from system bus for prefetch queue or
	24	* store queue read operation
	25	*/
	26	#define CHPAFSR_DTO (1UL << 59UL) /* ch+ */
	27
	28	/* Bus error from system bus for prefetch queue or store queue
	29	* read operation
	30	*/
	31	#define CHPAFSR_DBERR (1UL << 58UL) /* ch+ */
	32
	33	/* Hardware corrected E-cache Tag ECC error */
	34	#define CHPAFSR_THCE (1UL << 57UL) /* ch+ */
	35	/* System interface protocol error, hw timeout caused */
	36	#define JPAFSR_JETO (1UL << 57UL) /* jp */
	37
	38	/* SW handled correctable E-cache Tag ECC error */
	39	#define CHPAFSR_TSCE (1UL << 56UL) /* ch+ */
	40	/* Parity error on system snoop results */
	41	#define JPAFSR_SCE (1UL << 56UL) /* jp */
	42
	43	/* Uncorrectable E-cache Tag ECC error */
	44	#define CHPAFSR_TUE (1UL << 55UL) /* ch+ */
	45	/* System interface protocol error, illegal command detected */
	46	#define JPAFSR_JEIC (1UL << 55UL) /* jp */
	47
	48	/* Uncorrectable system bus data ECC error due to prefetch
	49	* or store fill request
	50	*/
	51	#define CHPAFSR_DUE (1UL << 54UL) /* ch+ */
	52	/* System interface protocol error, illegal ADTYPE detected */
	53	#define JPAFSR_JEIT (1UL << 54UL) /* jp */
	54
	55	/* Multiple errors of the same type have occurred. This bit is set when
	56	* an uncorrectable error or a SW correctable error occurs and the status
	57	* bit to report that error is already set. When multiple errors of
	58	* different types are indicated by setting multiple status bits.
	59	*
	60	* This bit is not set if multiple HW corrected errors with the same
	61	* status bit occur, only uncorrectable and SW correctable ones have
	62	* this behavior.
	63	*
	64	* This bit is not set when multiple ECC errors happen within a single
	65	* 64-byte system bus transaction. Only the first ECC error in a 16-byte
	66	* subunit will be logged. All errors in subsequent 16-byte subunits
	67	* from the same 64-byte transaction are ignored.
	68	*/
	69	#define CHAFSR_ME (1UL << 53UL) /* ch,ch+,jp */
	70
	71	/* Privileged state error has occurred. This is a capture of PSTATE.PRIV
	72	* at the time the error is detected.
	73	*/
	74	#define CHAFSR_PRIV (1UL << 52UL) /* ch,ch+,jp */
	75
	76	/* The following bits 51 (CHAFSR_PERR) to 33 (CHAFSR_CE) are sticky error
	77	* bits and record the most recently detected errors. Bits accumulate
	78	* errors that have been detected since the last write to clear the bit.
	79	*/
	80
	81	/* System interface protocol error. The processor asserts its' ERROR
	82	* pin when this event occurs and it also logs a specific cause code
	83	* into a JTAG scannable flop.
	84	*/
	85	#define CHAFSR_PERR (1UL << 51UL) /* ch,ch+,jp */
	86
	87	/* Internal processor error. The processor asserts its' ERROR
	88	* pin when this event occurs and it also logs a specific cause code
	89	* into a JTAG scannable flop.
	90	*/
	91	#define CHAFSR_IERR (1UL << 50UL) /* ch,ch+,jp */
	92
	93	/* System request parity error on incoming address */
	94	#define CHAFSR_ISAP (1UL << 49UL) /* ch,ch+,jp */
	95
	96	/* HW Corrected system bus MTAG ECC error */
	97	#define CHAFSR_EMC (1UL << 48UL) /* ch,ch+ */
	98	/* Parity error on L2 cache tag SRAM */
	99	#define JPAFSR_ETP (1UL << 48UL) /* jp */
	100
	101	/* Uncorrectable system bus MTAG ECC error */
	102	#define CHAFSR_EMU (1UL << 47UL) /* ch,ch+ */
	103	/* Out of range memory error has occurred */
	104	#define JPAFSR_OM (1UL << 47UL) /* jp */
	105
	106	/* HW Corrected system bus data ECC error for read of interrupt vector */
	107	#define CHAFSR_IVC (1UL << 46UL) /* ch,ch+ */
	108	/* Error due to unsupported store */
	109	#define JPAFSR_UMS (1UL << 46UL) /* jp */
	110
	111	/* Uncorrectable system bus data ECC error for read of interrupt vector */
	112	#define CHAFSR_IVU (1UL << 45UL) /* ch,ch+,jp */
	113
	114	/* Unmapped error from system bus */
	115	#define CHAFSR_TO (1UL << 44UL) /* ch,ch+,jp */
	116
	117	/* Bus error response from system bus */
	118	#define CHAFSR_BERR (1UL << 43UL) /* ch,ch+,jp */
	119
	120	/* SW Correctable E-cache ECC error for instruction fetch or data access
	121	* other than block load.
	122	*/
	123	#define CHAFSR_UCC (1UL << 42UL) /* ch,ch+,jp */
	124
	125	/* Uncorrectable E-cache ECC error for instruction fetch or data access
	126	* other than block load.
	127	*/
	128	#define CHAFSR_UCU (1UL << 41UL) /* ch,ch+,jp */
	129
	130	/* Copyout HW Corrected ECC error */
	131	#define CHAFSR_CPC (1UL << 40UL) /* ch,ch+,jp */
	132
	133	/* Copyout Uncorrectable ECC error */
	134	#define CHAFSR_CPU (1UL << 39UL) /* ch,ch+,jp */
	135
	136	/* HW Corrected ECC error from E-cache for writeback */
	137	#define CHAFSR_WDC (1UL << 38UL) /* ch,ch+,jp */
	138
	139	/* Uncorrectable ECC error from E-cache for writeback */
	140	#define CHAFSR_WDU (1UL << 37UL) /* ch,ch+,jp */
	141
	142	/* HW Corrected ECC error from E-cache for store merge or block load */
	143	#define CHAFSR_EDC (1UL << 36UL) /* ch,ch+,jp */
	144
	145	/* Uncorrectable ECC error from E-cache for store merge or block load */
	146	#define CHAFSR_EDU (1UL << 35UL) /* ch,ch+,jp */
	147
	148	/* Uncorrectable system bus data ECC error for read of memory or I/O */
	149	#define CHAFSR_UE (1UL << 34UL) /* ch,ch+,jp */
	150
	151	/* HW Corrected system bus data ECC error for read of memory or I/O */
	152	#define CHAFSR_CE (1UL << 33UL) /* ch,ch+,jp */
	153
	154	/* Uncorrectable ECC error from remote cache/memory */
	155	#define JPAFSR_RUE (1UL << 32UL) /* jp */
	156
	157	/* Correctable ECC error from remote cache/memory */
	158	#define JPAFSR_RCE (1UL << 31UL) /* jp */
	159
	160	/* JBUS parity error on returned read data */
	161	#define JPAFSR_BP (1UL << 30UL) /* jp */
	162
	163	/* JBUS parity error on data for writeback or block store */
	164	#define JPAFSR_WBP (1UL << 29UL) /* jp */
	165
	166	/* Foreign read to DRAM incurring correctable ECC error */
	167	#define JPAFSR_FRC (1UL << 28UL) /* jp */
	168
	169	/* Foreign read to DRAM incurring uncorrectable ECC error */
	170	#define JPAFSR_FRU (1UL << 27UL) /* jp */
	171
	172	#define CHAFSR_ERRORS (CHAFSR_PERR \| CHAFSR_IERR \| CHAFSR_ISAP \| CHAFSR_EMC \| \
	173	CHAFSR_EMU \| CHAFSR_IVC \| CHAFSR_IVU \| CHAFSR_TO \| \
	174	CHAFSR_BERR \| CHAFSR_UCC \| CHAFSR_UCU \| CHAFSR_CPC \| \
	175	CHAFSR_CPU \| CHAFSR_WDC \| CHAFSR_WDU \| CHAFSR_EDC \| \
	176	CHAFSR_EDU \| CHAFSR_UE \| CHAFSR_CE)
	177	#define CHPAFSR_ERRORS (CHPAFSR_DTO \| CHPAFSR_DBERR \| CHPAFSR_THCE \| \
	178	CHPAFSR_TSCE \| CHPAFSR_TUE \| CHPAFSR_DUE \| \
	179	CHAFSR_PERR \| CHAFSR_IERR \| CHAFSR_ISAP \| CHAFSR_EMC \| \
	180	CHAFSR_EMU \| CHAFSR_IVC \| CHAFSR_IVU \| CHAFSR_TO \| \
	181	CHAFSR_BERR \| CHAFSR_UCC \| CHAFSR_UCU \| CHAFSR_CPC \| \
	182	CHAFSR_CPU \| CHAFSR_WDC \| CHAFSR_WDU \| CHAFSR_EDC \| \
	183	CHAFSR_EDU \| CHAFSR_UE \| CHAFSR_CE)
	184	#define JPAFSR_ERRORS (JPAFSR_JETO \| JPAFSR_SCE \| JPAFSR_JEIC \| \
	185	JPAFSR_JEIT \| CHAFSR_PERR \| CHAFSR_IERR \| \
	186	CHAFSR_ISAP \| JPAFSR_ETP \| JPAFSR_OM \| \
	187	JPAFSR_UMS \| CHAFSR_IVU \| CHAFSR_TO \| \
	188	CHAFSR_BERR \| CHAFSR_UCC \| CHAFSR_UCU \| \
	189	CHAFSR_CPC \| CHAFSR_CPU \| CHAFSR_WDC \| \
	190	CHAFSR_WDU \| CHAFSR_EDC \| CHAFSR_EDU \| \
	191	CHAFSR_UE \| CHAFSR_CE \| JPAFSR_RUE \| \
	192	JPAFSR_RCE \| JPAFSR_BP \| JPAFSR_WBP \| \
	193	JPAFSR_FRC \| JPAFSR_FRU)
	194
	195	/* Active JBUS request signal when error occurred */
	196	#define JPAFSR_JBREQ (0x7UL << 24UL) /* jp */
	197	#define JPAFSR_JBREQ_SHIFT 24UL
	198
	199	/* L2 cache way information */
	200	#define JPAFSR_ETW (0x3UL << 22UL) /* jp */
	201	#define JPAFSR_ETW_SHIFT 22UL
	202
	203	/* System bus MTAG ECC syndrome. This field captures the status of the
	204	* first occurrence of the highest-priority error according to the M_SYND
	205	* overwrite policy. After the AFSR sticky bit, corresponding to the error
	206	* for which the M_SYND is reported, is cleared, the contents of the M_SYND
	207	* field will be unchanged by will be unfrozen for further error capture.
	208	*/
	209	#define CHAFSR_M_SYNDROME (0xfUL << 16UL) /* ch,ch+,jp */
	210	#define CHAFSR_M_SYNDROME_SHIFT 16UL
	211
	212	/* Agenid Id of the foreign device causing the UE/CE errors */
	213	#define JPAFSR_AID (0x1fUL << 9UL) /* jp */
	214	#define JPAFSR_AID_SHIFT 9UL
	215
	216	/* System bus or E-cache data ECC syndrome. This field captures the status
	217	* of the first occurrence of the highest-priority error according to the
	218	* E_SYND overwrite policy. After the AFSR sticky bit, corresponding to the
	219	* error for which the E_SYND is reported, is cleare, the contents of the E_SYND
	220	* field will be unchanged but will be unfrozen for further error capture.
	221	*/
	222	#define CHAFSR_E_SYNDROME (0x1ffUL << 0UL) /* ch,ch+,jp */
	223	#define CHAFSR_E_SYNDROME_SHIFT 0UL
	224
	225	/* The AFSR must be explicitly cleared by software, it is not cleared automatically
	226	* by a read. Writes to bits <51:33> with bits set will clear the corresponding
	227	* bits in the AFSR. Bits associated with disrupting traps must be cleared before
	228	* interrupts are re-enabled to prevent multiple traps for the same error. I.e.
	229	* PSTATE.IE and AFSR bits control delivery of disrupting traps.
	230	*
	231	* Since there is only one AFAR, when multiple events have been logged by the
	232	* bits in the AFSR, at most one of these events will have its status captured
	233	* in the AFAR. The highest priority of those event bits will get AFAR logging.
	234	* The AFAR will be unlocked and available to capture the address of another event
	235	* as soon as the one bit in AFSR that corresponds to the event logged in AFAR is
	236	* cleared. For example, if AFSR.CE is detected, then AFSR.UE (which overwrites
	237	* the AFAR), and AFSR.UE is cleared by not AFSR.CE, then the AFAR will be unlocked
	238	* and ready for another event, even though AFSR.CE is still set. The same rules
	239	* also apply to the M_SYNDROME and E_SYNDROME fields of the AFSR.
	240	*/
	241
	242	#endif /* _SPARC64_CHAFSR_H */