diff options
Diffstat (limited to 'include/asm-sparc64/asi.h')
| -rw-r--r-- | include/asm-sparc64/asi.h | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/include/asm-sparc64/asi.h b/include/asm-sparc64/asi.h index 534855660f2a..662a21107ae6 100644 --- a/include/asm-sparc64/asi.h +++ b/include/asm-sparc64/asi.h | |||
| @@ -25,14 +25,27 @@ | |||
| 25 | 25 | ||
| 26 | /* SpitFire and later extended ASIs. The "(III)" marker designates | 26 | /* SpitFire and later extended ASIs. The "(III)" marker designates |
| 27 | * UltraSparc-III and later specific ASIs. The "(CMT)" marker designates | 27 | * UltraSparc-III and later specific ASIs. The "(CMT)" marker designates |
| 28 | * Chip Multi Threading specific ASIs. | 28 | * Chip Multi Threading specific ASIs. "(NG)" designates Niagara specific |
| 29 | * ASIs, "(4V)" designates SUN4V specific ASIs. | ||
| 29 | */ | 30 | */ |
| 30 | #define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cachable */ | 31 | #define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cachable */ |
| 31 | #define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */ | 32 | #define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */ |
| 33 | #define ASI_BLK_AIUP_4V 0x16 /* (4V) Prim, user, block ld/st */ | ||
| 34 | #define ASI_BLK_AIUS_4V 0x17 /* (4V) Sec, user, block ld/st */ | ||
| 32 | #define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cachable, little endian*/ | 35 | #define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cachable, little endian*/ |
| 33 | #define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */ | 36 | #define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */ |
| 37 | #define ASI_BLK_AIUP_L_4V 0x1e /* (4V) Prim, user, block, l-endian*/ | ||
| 38 | #define ASI_BLK_AIUS_L_4V 0x1f /* (4V) Sec, user, block, l-endian */ | ||
| 39 | #define ASI_SCRATCHPAD 0x20 /* (4V) Scratch Pad Registers */ | ||
| 40 | #define ASI_MMU 0x21 /* (4V) MMU Context Registers */ | ||
| 41 | #define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load, | ||
| 42 | * secondary, user | ||
| 43 | */ | ||
| 34 | #define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cachable, qword load */ | 44 | #define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cachable, qword load */ |
| 45 | #define ASI_QUEUE 0x25 /* (4V) Interrupt Queue Registers */ | ||
| 46 | #define ASI_QUAD_LDD_PHYS_4V 0x26 /* (4V) Physical, qword load */ | ||
| 35 | #define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cachable, qword load, l-endian */ | 47 | #define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cachable, qword load, l-endian */ |
| 48 | #define ASI_QUAD_LDD_PHYS_L_4V 0x2e /* (4V) Phys, qword load, l-endian */ | ||
| 36 | #define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */ | 49 | #define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */ |
| 37 | #define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */ | 50 | #define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */ |
| 38 | #define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */ | 51 | #define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */ |
| @@ -137,6 +150,9 @@ | |||
| 137 | #define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/ | 150 | #define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/ |
| 138 | #define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */ | 151 | #define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */ |
| 139 | #define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */ | 152 | #define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */ |
| 153 | #define ASI_BLK_INIT_QUAD_LDD_P 0xe2 /* (NG) init-store, twin load, | ||
| 154 | * primary, implicit | ||
| 155 | */ | ||
| 140 | #define ASI_BLK_P 0xf0 /* Primary, blk ld/st */ | 156 | #define ASI_BLK_P 0xf0 /* Primary, blk ld/st */ |
| 141 | #define ASI_BLK_S 0xf1 /* Secondary, blk ld/st */ | 157 | #define ASI_BLK_S 0xf1 /* Secondary, blk ld/st */ |
| 142 | #define ASI_BLK_PL 0xf8 /* Primary, blk ld/st, little */ | 158 | #define ASI_BLK_PL 0xf8 /* Primary, blk ld/st, little */ |