1 files changed, 0 insertions, 138 deletions
diff --git a/include/asm-sparc/cache.h b/include/asm-sparc/cache.h
deleted file mode 100644
index 41f85ae4bd4a..000000000000
--- a/include/asm-sparc/cache.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/* cache.h:  Cache specific code for the Sparc.  These include flushing
- *           and direct tag/data line access.
- *
- * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
- */
-#ifndef _SPARC_CACHE_H
-#define _SPARC_CACHE_H
-#define L1_CACHE_SHIFT 5
-#define L1_CACHE_BYTES 32
-#define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
-#ifdef CONFIG_SPARC32
-#define SMP_CACHE_BYTES_SHIFT 5
-#else
-#define SMP_CACHE_BYTES_SHIFT 6
-#endif
-#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT)
-#define __read_mostly __attribute__((__section__(".data.read_mostly")))
-#ifdef CONFIG_SPARC32
-#include <asm/asi.h>
-/* Direct access to the instruction cache is provided through and
- * alternate address space.  The IDC bit must be off in the ICCR on
- * HyperSparcs for these accesses to work.  The code below does not do
- * any checking, the caller must do so.  These routines are for
- * diagnostics only, but could end up being useful.  Use with care.
- * Also, you are asking for trouble if you execute these in one of the
- * three instructions following a %asr/%psr access or modification.
- */
-/* First, cache-tag access. */
-static inline unsigned int get_icache_tag(int setnum, int tagnum)
-{
-        unsigned int vaddr, retval;
-        vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
-        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
-                             "=r" (retval) :
-                             "r" (vaddr), "i" (ASI_M_TXTC_TAG));
-        return retval;
-}
-static inline void put_icache_tag(int setnum, int tagnum, unsigned int entry)
-{
-        unsigned int vaddr;
-        vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
-        __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
-                             "r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) :
-                             "memory");
-}
-/* Second cache-data access.  The data is returned two-32bit quantities
- * at a time.
- */
-static inline void get_icache_data(int setnum, int tagnum, int subblock,
-                                       unsigned int *data)
-{
-        unsigned int value1, value2, vaddr;
-        vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
-                ((subblock&0x3) << 3);
-        __asm__ __volatile__("ldda [%2] %3, %%g2\n\t"
-                             "or %%g0, %%g2, %0\n\t"
-                             "or %%g0, %%g3, %1\n\t" :
-                             "=r" (value1), "=r" (value2) :
-                             "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
-                             "g2", "g3");
-        data[0] = value1; data[1] = value2;
-}
-static inline void put_icache_data(int setnum, int tagnum, int subblock,
-                                       unsigned int *data)
-{
-        unsigned int value1, value2, vaddr;
-        vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
-                ((subblock&0x3) << 3);
-        value1 = data[0]; value2 = data[1];
-        __asm__ __volatile__("or %%g0, %0, %%g2\n\t"
-                             "or %%g0, %1, %%g3\n\t"
-                             "stda %%g2, [%2] %3\n\t" : :
-                             "r" (value1), "r" (value2), 
-                             "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
-                             "g2", "g3", "memory" /* no joke */);
-}
-/* Different types of flushes with the ICACHE.  Some of the flushes
- * affect both the ICACHE and the external cache.  Others only clear
- * the ICACHE entries on the cpu itself.  V8's (most) allow
- * granularity of flushes on the packet (element in line), whole line,
- * and entire cache (ie. all lines) level.  The ICACHE only flushes are
- * ROSS HyperSparc specific and are in ross.h
- */
-/* Flushes which clear out both the on-chip and external caches */
-static inline void flush_ei_page(unsigned int addr)
-{
-        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
-                             "r" (addr), "i" (ASI_M_FLUSH_PAGE) :
-                             "memory");
-}
-static inline void flush_ei_seg(unsigned int addr)
-{
-        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
-                             "r" (addr), "i" (ASI_M_FLUSH_SEG) :
-                             "memory");
-}
-static inline void flush_ei_region(unsigned int addr)
-{
-        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
-                             "r" (addr), "i" (ASI_M_FLUSH_REGION) :
-                             "memory");
-}
-static inline void flush_ei_ctx(unsigned int addr)
-{
-        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
-                             "r" (addr), "i" (ASI_M_FLUSH_CTX) :
-                             "memory");
-}
-static inline void flush_ei_user(unsigned int addr)
-{
-        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
-                             "r" (addr), "i" (ASI_M_FLUSH_USER) :
-                             "memory");
-}
-#endif /* CONFIG_SPARC32 */
-#endif /* !(_SPARC_CACHE_H) */

diff --git a/include/asm-sparc/cache.h b/include/asm-sparc/cache.h deleted file mode 100644 index 41f85ae4bd4a..000000000000 --- a/include/asm-sparc/cache.h +++ /dev/null
@@ -1,138 +0,0 @@
1	/* cache.h: Cache specific code for the Sparc. These include flushing
2	* and direct tag/data line access.
3	*
4	* Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
5	*/
6
7	#ifndef _SPARC_CACHE_H
8	#define _SPARC_CACHE_H
9
10	#define L1_CACHE_SHIFT 5
11	#define L1_CACHE_BYTES 32
12	#define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
13
14	#ifdef CONFIG_SPARC32
15	#define SMP_CACHE_BYTES_SHIFT 5
16	#else
17	#define SMP_CACHE_BYTES_SHIFT 6
18	#endif
19
20	#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT)
21
22	#define __read_mostly __attribute__((__section__(".data.read_mostly")))
23
24	#ifdef CONFIG_SPARC32
25	#include <asm/asi.h>
26
27	/* Direct access to the instruction cache is provided through and
28	* alternate address space. The IDC bit must be off in the ICCR on
29	* HyperSparcs for these accesses to work. The code below does not do
30	* any checking, the caller must do so. These routines are for
31	* diagnostics only, but could end up being useful. Use with care.
32	* Also, you are asking for trouble if you execute these in one of the
33	* three instructions following a %asr/%psr access or modification.
34	*/
35
36	/* First, cache-tag access. */
37	static inline unsigned int get_icache_tag(int setnum, int tagnum)
38	{
39	unsigned int vaddr, retval;
40
41	vaddr = ((setnum&1) << 12) \| ((tagnum&0x7f) << 5);
42	__asm__ __volatile__("lda [%1] %2, %0\n\t" :
43	"=r" (retval) :
44	"r" (vaddr), "i" (ASI_M_TXTC_TAG));
45	return retval;
46	}
47
48	static inline void put_icache_tag(int setnum, int tagnum, unsigned int entry)
49	{
50	unsigned int vaddr;
51
52	vaddr = ((setnum&1) << 12) \| ((tagnum&0x7f) << 5);
53	__asm__ __volatile__("sta %0, [%1] %2\n\t" : :
54	"r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) :
55	"memory");
56	}
57
58	/* Second cache-data access. The data is returned two-32bit quantities
59	* at a time.
60	*/
61	static inline void get_icache_data(int setnum, int tagnum, int subblock,
62	unsigned int *data)
63	{
64	unsigned int value1, value2, vaddr;
65
66	vaddr = ((setnum&0x1) << 12) \| ((tagnum&0x7f) << 5) \|
67	((subblock&0x3) << 3);
68	__asm__ __volatile__("ldda [%2] %3, %%g2\n\t"
69	"or %%g0, %%g2, %0\n\t"
70	"or %%g0, %%g3, %1\n\t" :
71	"=r" (value1), "=r" (value2) :
72	"r" (vaddr), "i" (ASI_M_TXTC_DATA) :
73	"g2", "g3");
74	data[0] = value1; data[1] = value2;
75	}
76
77	static inline void put_icache_data(int setnum, int tagnum, int subblock,
78	unsigned int *data)
79	{
80	unsigned int value1, value2, vaddr;
81
82	vaddr = ((setnum&0x1) << 12) \| ((tagnum&0x7f) << 5) \|
83	((subblock&0x3) << 3);
84	value1 = data[0]; value2 = data[1];
85	__asm__ __volatile__("or %%g0, %0, %%g2\n\t"
86	"or %%g0, %1, %%g3\n\t"
87	"stda %%g2, [%2] %3\n\t" : :
88	"r" (value1), "r" (value2),
89	"r" (vaddr), "i" (ASI_M_TXTC_DATA) :
90	"g2", "g3", "memory" /* no joke */);
91	}
92
93	/* Different types of flushes with the ICACHE. Some of the flushes
94	* affect both the ICACHE and the external cache. Others only clear
95	* the ICACHE entries on the cpu itself. V8's (most) allow
96	* granularity of flushes on the packet (element in line), whole line,
97	* and entire cache (ie. all lines) level. The ICACHE only flushes are
98	* ROSS HyperSparc specific and are in ross.h
99	*/
100
101	/* Flushes which clear out both the on-chip and external caches */
102	static inline void flush_ei_page(unsigned int addr)
103	{
104	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
105	"r" (addr), "i" (ASI_M_FLUSH_PAGE) :
106	"memory");
107	}
108
109	static inline void flush_ei_seg(unsigned int addr)
110	{
111	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
112	"r" (addr), "i" (ASI_M_FLUSH_SEG) :
113	"memory");
114	}
115
116	static inline void flush_ei_region(unsigned int addr)
117	{
118	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
119	"r" (addr), "i" (ASI_M_FLUSH_REGION) :
120	"memory");
121	}
122
123	static inline void flush_ei_ctx(unsigned int addr)
124	{
125	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
126	"r" (addr), "i" (ASI_M_FLUSH_CTX) :
127	"memory");
128	}
129
130	static inline void flush_ei_user(unsigned int addr)
131	{
132	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
133	"r" (addr), "i" (ASI_M_FLUSH_USER) :
134	"memory");
135	}
136	#endif /* CONFIG_SPARC32 */
137
138	#endif /* !(_SPARC_CACHE_H) */