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-rw-r--r--include/asm-sparc/cache.h21
1 files changed, 15 insertions, 6 deletions
diff --git a/include/asm-sparc/cache.h b/include/asm-sparc/cache.h
index cb971e88aea4..41f85ae4bd4a 100644
--- a/include/asm-sparc/cache.h
+++ b/include/asm-sparc/cache.h
@@ -1,20 +1,28 @@
1/* $Id: cache.h,v 1.9 1999/08/14 03:51:58 anton Exp $ 1/* cache.h: Cache specific code for the Sparc. These include flushing
2 * cache.h: Cache specific code for the Sparc. These include flushing
3 * and direct tag/data line access. 2 * and direct tag/data line access.
4 * 3 *
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 4 * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
6 */ 5 */
7 6
8#ifndef _SPARC_CACHE_H 7#ifndef _SPARC_CACHE_H
9#define _SPARC_CACHE_H 8#define _SPARC_CACHE_H
10 9
11#include <asm/asi.h>
12
13#define L1_CACHE_SHIFT 5 10#define L1_CACHE_SHIFT 5
14#define L1_CACHE_BYTES 32 11#define L1_CACHE_BYTES 32
15#define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))) 12#define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
16 13
17#define SMP_CACHE_BYTES 32 14#ifdef CONFIG_SPARC32
15#define SMP_CACHE_BYTES_SHIFT 5
16#else
17#define SMP_CACHE_BYTES_SHIFT 6
18#endif
19
20#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT)
21
22#define __read_mostly __attribute__((__section__(".data.read_mostly")))
23
24#ifdef CONFIG_SPARC32
25#include <asm/asi.h>
18 26
19/* Direct access to the instruction cache is provided through and 27/* Direct access to the instruction cache is provided through and
20 * alternate address space. The IDC bit must be off in the ICCR on 28 * alternate address space. The IDC bit must be off in the ICCR on
@@ -125,5 +133,6 @@ static inline void flush_ei_user(unsigned int addr)
125 "r" (addr), "i" (ASI_M_FLUSH_USER) : 133 "r" (addr), "i" (ASI_M_FLUSH_USER) :
126 "memory"); 134 "memory");
127} 135}
136#endif /* CONFIG_SPARC32 */
128 137
129#endif /* !(_SPARC_CACHE_H) */ 138#endif /* !(_SPARC_CACHE_H) */