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-rw-r--r--include/asm-sh/cpu-sh2/irq.h84
-rw-r--r--include/asm-sh/cpu-sh2a/irq.h75
-rw-r--r--include/asm-sh/irq-sh73180.h314
-rw-r--r--include/asm-sh/irq-sh7343.h317
-rw-r--r--include/asm-sh/irq-sh7780.h311
-rw-r--r--include/asm-sh/irq.h654
6 files changed, 1 insertions, 1754 deletions
diff --git a/include/asm-sh/cpu-sh2/irq.h b/include/asm-sh/cpu-sh2/irq.h
deleted file mode 100644
index 4032a14d0f41..000000000000
--- a/include/asm-sh/cpu-sh2/irq.h
+++ /dev/null
@@ -1,84 +0,0 @@
1#ifndef __ASM_SH_CPU_SH2_IRQ_H
2#define __ASM_SH_CPU_SH2_IRQ_H
3
4/*
5 *
6 * linux/include/asm-sh/cpu-sh2/irq.h
7 *
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2003 Paul Mundt
11 *
12 */
13
14#include <linux/config.h>
15
16#if defined(CONFIG_CPU_SUBTYPE_SH7044)
17#define INTC_IPRA 0xffff8348UL
18#define INTC_IPRB 0xffff834aUL
19#define INTC_IPRC 0xffff834cUL
20#define INTC_IPRD 0xffff834eUL
21#define INTC_IPRE 0xffff8350UL
22#define INTC_IPRF 0xffff8352UL
23#define INTC_IPRG 0xffff8354UL
24#define INTC_IPRH 0xffff8356UL
25
26#define INTC_ICR 0xffff8358UL
27#define INTC_ISR 0xffff835aUL
28#elif defined(CONFIG_CPU_SUBTYPE_SH7604)
29#define INTC_IPRA 0xfffffee2UL
30#define INTC_IPRB 0xfffffe60UL
31
32#define INTC_VCRA 0xfffffe62UL
33#define INTC_VCRB 0xfffffe64UL
34#define INTC_VCRC 0xfffffe66UL
35#define INTC_VCRD 0xfffffe68UL
36
37#define INTC_VCRWDT 0xfffffee4UL
38#define INTC_VCRDIV 0xffffff0cUL
39#define INTC_VCRDMA0 0xffffffa0UL
40#define INTC_VCRDMA1 0xffffffa8UL
41
42#define INTC_ICR 0xfffffee0UL
43#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
44#define INTC_IPRA 0xf8140006UL
45#define INTC_IPRB 0xf8140008UL
46#define INTC_IPRC 0xf8080000UL
47#define INTC_IPRD 0xf8080002UL
48#define INTC_IPRE 0xf8080004UL
49#define INTC_IPRF 0xf8080006UL
50#define INTC_IPRG 0xf8080008UL
51
52#define INTC_ICR0 0xf8140000UL
53#define INTC_IRQCR 0xf8140002UL
54#define INTC_IRQSR 0xf8140004UL
55
56#define CMI0_IRQ 86
57#define CMI1_IRQ 87
58
59#define SCIF_ERI_IRQ 88
60#define SCIF_RXI_IRQ 89
61#define SCIF_BRI_IRQ 90
62#define SCIF_TXI_IRQ 91
63#define SCIF_IPR_ADDR INTC_IPRD
64#define SCIF_IPR_POS 3
65#define SCIF_PRIORITY 3
66
67#define SCIF1_ERI_IRQ 92
68#define SCIF1_RXI_IRQ 93
69#define SCIF1_BRI_IRQ 94
70#define SCIF1_TXI_IRQ 95
71#define SCIF1_IPR_ADDR INTC_IPRD
72#define SCIF1_IPR_POS 2
73#define SCIF1_PRIORITY 3
74
75#define SCIF2_BRI_IRQ 96
76#define SCIF2_RXI_IRQ 97
77#define SCIF2_ERI_IRQ 98
78#define SCIF2_TXI_IRQ 99
79#define SCIF2_IPR_ADDR INTC_IPRD
80#define SCIF2_IPR_POS 1
81#define SCIF2_PRIORITY 3
82#endif
83
84#endif /* __ASM_SH_CPU_SH2_IRQ_H */
diff --git a/include/asm-sh/cpu-sh2a/irq.h b/include/asm-sh/cpu-sh2a/irq.h
deleted file mode 100644
index d3d42f64148c..000000000000
--- a/include/asm-sh/cpu-sh2a/irq.h
+++ /dev/null
@@ -1,75 +0,0 @@
1#ifndef __ASM_SH_CPU_SH2A_IRQ_H
2#define __ASM_SH_CPU_SH2A_IRQ_H
3
4#define INTC_IPR01 0xfffe0818UL
5#define INTC_IPR02 0xfffe081aUL
6#define INTC_IPR05 0xfffe0820UL
7#define INTC_IPR06 0xfffe0c00UL
8#define INTC_IPR07 0xfffe0c02UL
9#define INTC_IPR08 0xfffe0c04UL
10#define INTC_IPR09 0xfffe0c06UL
11#define INTC_IPR10 0xfffe0c08UL
12#define INTC_IPR11 0xfffe0c0aUL
13#define INTC_IPR12 0xfffe0c0cUL
14#define INTC_IPR13 0xfffe0c0eUL
15#define INTC_IPR14 0xfffe0c10UL
16
17#define INTC_ICR0 0xfffe0800UL
18#define INTC_ICR1 0xfffe0802UL
19#define INTC_ICR2 0xfffe0804UL
20#define INTC_ISR 0xfffe0806UL
21
22#define IRQ0_IRQ 64
23#define IRQ1_IRQ 65
24#define IRQ2_IRQ 66
25#define IRQ3_IRQ 67
26#define IRQ4_IRQ 68
27#define IRQ5_IRQ 69
28#define IRQ6_IRQ 70
29#define IRQ7_IRQ 71
30
31#define PINT0_IRQ 80
32#define PINT1_IRQ 81
33#define PINT2_IRQ 82
34#define PINT3_IRQ 83
35#define PINT4_IRQ 84
36#define PINT5_IRQ 85
37#define PINT6_IRQ 86
38#define PINT7_IRQ 87
39
40#define CMI0_IRQ 140
41#define CMI1_IRQ 141
42
43#define SCIF_BRI_IRQ 240
44#define SCIF_ERI_IRQ 241
45#define SCIF_RXI_IRQ 242
46#define SCIF_TXI_IRQ 243
47#define SCIF_IPR_ADDR INTC_IPR14
48#define SCIF_IPR_POS 3
49#define SCIF_PRIORITY 3
50
51#define SCIF1_BRI_IRQ 244
52#define SCIF1_ERI_IRQ 245
53#define SCIF1_RXI_IRQ 246
54#define SCIF1_TXI_IRQ 247
55#define SCIF1_IPR_ADDR INTC_IPR14
56#define SCIF1_IPR_POS 2
57#define SCIF1_PRIORITY 3
58
59#define SCIF2_BRI_IRQ 248
60#define SCIF2_ERI_IRQ 249
61#define SCIF2_RXI_IRQ 250
62#define SCIF2_TXI_IRQ 251
63#define SCIF2_IPR_ADDR INTC_IPR14
64#define SCIF2_IPR_POS 1
65#define SCIF2_PRIORITY 3
66
67#define SCIF3_BRI_IRQ 252
68#define SCIF3_ERI_IRQ 253
69#define SCIF3_RXI_IRQ 254
70#define SCIF3_TXI_IRQ 255
71#define SCIF3_IPR_ADDR INTC_IPR14
72#define SCIF3_IPR_POS 0
73#define SCIF3_PRIORITY 3
74
75#endif /* __ASM_SH_CPU_SH2A_IRQ_H */
diff --git a/include/asm-sh/irq-sh73180.h b/include/asm-sh/irq-sh73180.h
deleted file mode 100644
index b28af9a69d72..000000000000
--- a/include/asm-sh/irq-sh73180.h
+++ /dev/null
@@ -1,314 +0,0 @@
1#ifndef __ASM_SH_IRQ_SH73180_H
2#define __ASM_SH_IRQ_SH73180_H
3
4/*
5 * linux/include/asm-sh/irq-sh73180.h
6 *
7 * Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp>
8 */
9
10#undef INTC_IPRA
11#undef INTC_IPRB
12#undef INTC_IPRC
13#undef INTC_IPRD
14
15#undef DMTE0_IRQ
16#undef DMTE1_IRQ
17#undef DMTE2_IRQ
18#undef DMTE3_IRQ
19#undef DMTE4_IRQ
20#undef DMTE5_IRQ
21#undef DMTE6_IRQ
22#undef DMTE7_IRQ
23#undef DMAE_IRQ
24#undef DMA_IPR_ADDR
25#undef DMA_IPR_POS
26#undef DMA_PRIORITY
27
28#undef INTC_IMCR0
29#undef INTC_IMCR1
30#undef INTC_IMCR2
31#undef INTC_IMCR3
32#undef INTC_IMCR4
33#undef INTC_IMCR5
34#undef INTC_IMCR6
35#undef INTC_IMCR7
36#undef INTC_IMCR8
37#undef INTC_IMCR9
38#undef INTC_IMCR10
39
40
41#define INTC_IPRA 0xA4080000UL
42#define INTC_IPRB 0xA4080004UL
43#define INTC_IPRC 0xA4080008UL
44#define INTC_IPRD 0xA408000CUL
45#define INTC_IPRE 0xA4080010UL
46#define INTC_IPRF 0xA4080014UL
47#define INTC_IPRG 0xA4080018UL
48#define INTC_IPRH 0xA408001CUL
49#define INTC_IPRI 0xA4080020UL
50#define INTC_IPRJ 0xA4080024UL
51#define INTC_IPRK 0xA4080028UL
52
53#define INTC_IMR0 0xA4080080UL
54#define INTC_IMR1 0xA4080084UL
55#define INTC_IMR2 0xA4080088UL
56#define INTC_IMR3 0xA408008CUL
57#define INTC_IMR4 0xA4080090UL
58#define INTC_IMR5 0xA4080094UL
59#define INTC_IMR6 0xA4080098UL
60#define INTC_IMR7 0xA408009CUL
61#define INTC_IMR8 0xA40800A0UL
62#define INTC_IMR9 0xA40800A4UL
63#define INTC_IMR10 0xA40800A8UL
64#define INTC_IMR11 0xA40800ACUL
65
66#define INTC_IMCR0 0xA40800C0UL
67#define INTC_IMCR1 0xA40800C4UL
68#define INTC_IMCR2 0xA40800C8UL
69#define INTC_IMCR3 0xA40800CCUL
70#define INTC_IMCR4 0xA40800D0UL
71#define INTC_IMCR5 0xA40800D4UL
72#define INTC_IMCR6 0xA40800D8UL
73#define INTC_IMCR7 0xA40800DCUL
74#define INTC_IMCR8 0xA40800E0UL
75#define INTC_IMCR9 0xA40800E4UL
76#define INTC_IMCR10 0xA40800E8UL
77#define INTC_IMCR11 0xA40800ECUL
78
79#define INTC_ICR0 0xA4140000UL
80#define INTC_ICR1 0xA414001CUL
81
82#define INTMSK0 0xa4140044
83#define INTMSKCLR0 0xa4140064
84#define INTC_INTPRI0 0xa4140010
85
86/*
87 NOTE:
88
89 *_IRQ = (INTEVT2 - 0x200)/0x20
90*/
91
92/* TMU0 */
93#define TMU0_IRQ 16
94#define TMU0_IPR_ADDR INTC_IPRA
95#define TMU0_IPR_POS 3
96#define TMU0_PRIORITY 2
97
98#define TIMER_IRQ 16
99#define TIMER_IPR_ADDR INTC_IPRA
100#define TIMER_IPR_POS 3
101#define TIMER_PRIORITY 2
102
103/* TMU1 */
104#define TMU1_IRQ 17
105#define TMU1_IPR_ADDR INTC_IPRA
106#define TMU1_IPR_POS 2
107#define TMU1_PRIORITY 2
108
109/* TMU2 */
110#define TMU2_IRQ 18
111#define TMU2_IPR_ADDR INTC_IPRA
112#define TMU2_IPR_POS 1
113#define TMU2_PRIORITY 2
114
115/* LCDC */
116#define LCDC_IRQ 28
117#define LCDC_IPR_ADDR INTC_IPRB
118#define LCDC_IPR_POS 2
119#define LCDC_PRIORITY 2
120
121/* VIO (Video I/O) */
122#define CEU_IRQ 52
123#define BEU_IRQ 53
124#define VEU_IRQ 54
125#define VOU_IRQ 55
126#define VIO_IPR_ADDR INTC_IPRE
127#define VIO_IPR_POS 2
128#define VIO_PRIORITY 2
129
130/* MFI (Multi Functional Interface) */
131#define MFI_IRQ 56
132#define MFI_IPR_ADDR INTC_IPRE
133#define MFI_IPR_POS 1
134#define MFI_PRIORITY 2
135
136/* VPU (Video Processing Unit) */
137#define VPU_IRQ 60
138#define VPU_IPR_ADDR INTC_IPRE
139#define VPU_IPR_POS 0
140#define VPU_PRIORITY 2
141
142/* 3DG */
143#define TDG_IRQ 63
144#define TDG_IPR_ADDR INTC_IPRJ
145#define TDG_IPR_POS 2
146#define TDG_PRIORITY 2
147
148/* DMAC(1) */
149#define DMTE0_IRQ 48
150#define DMTE1_IRQ 49
151#define DMTE2_IRQ 50
152#define DMTE3_IRQ 51
153#define DMA1_IPR_ADDR INTC_IPRE
154#define DMA1_IPR_POS 3
155#define DMA1_PRIORITY 7
156
157/* DMAC(2) */
158#define DMTE4_IRQ 76
159#define DMTE5_IRQ 77
160#define DMA2_IPR_ADDR INTC_IPRF
161#define DMA2_IPR_POS 2
162#define DMA2_PRIORITY 7
163
164/* SCIF0 */
165#define SCIF_ERI_IRQ 80
166#define SCIF_RXI_IRQ 81
167#define SCIF_BRI_IRQ 82
168#define SCIF_TXI_IRQ 83
169#define SCIF_IPR_ADDR INTC_IPRG
170#define SCIF_IPR_POS 3
171#define SCIF_PRIORITY 3
172
173/* SIOF0 */
174#define SIOF0_IRQ 84
175#define SIOF0_IPR_ADDR INTC_IPRH
176#define SIOF0_IPR_POS 3
177#define SIOF0_PRIORITY 3
178
179/* FLCTL (Flash Memory Controller) */
180#define FLSTE_IRQ 92
181#define FLTEND_IRQ 93
182#define FLTRQ0_IRQ 94
183#define FLTRQ1_IRQ 95
184#define FLCTL_IPR_ADDR INTC_IPRH
185#define FLCTL_IPR_POS 1
186#define FLCTL_PRIORITY 3
187
188/* IIC(0) (IIC Bus Interface) */
189#define IIC0_ALI_IRQ 96
190#define IIC0_TACKI_IRQ 97
191#define IIC0_WAITI_IRQ 98
192#define IIC0_DTEI_IRQ 99
193#define IIC0_IPR_ADDR INTC_IPRH
194#define IIC0_IPR_POS 0
195#define IIC0_PRIORITY 3
196
197/* IIC(1) (IIC Bus Interface) */
198#define IIC1_ALI_IRQ 44
199#define IIC1_TACKI_IRQ 45
200#define IIC1_WAITI_IRQ 46
201#define IIC1_DTEI_IRQ 47
202#define IIC1_IPR_ADDR INTC_IPRG
203#define IIC1_IPR_POS 0
204#define IIC1_PRIORITY 3
205
206/* SIO0 */
207#define SIO0_IRQ 88
208#define SIO0_IPR_ADDR INTC_IPRI
209#define SIO0_IPR_POS 3
210#define SIO0_PRIORITY 3
211
212/* SDHI */
213#define SDHI_SDHII0_IRQ 100
214#define SDHI_SDHII1_IRQ 101
215#define SDHI_SDHII2_IRQ 102
216#define SDHI_SDHII3_IRQ 103
217#define SDHI_IPR_ADDR INTC_IPRK
218#define SDHI_IPR_POS 0
219#define SDHI_PRIORITY 3
220
221/* SIU (Sound Interface Unit) */
222#define SIU_IRQ 108
223#define SIU_IPR_ADDR INTC_IPRJ
224#define SIU_IPR_POS 1
225#define SIU_PRIORITY 3
226
227#define PORT_PACR 0xA4050100UL
228#define PORT_PBCR 0xA4050102UL
229#define PORT_PCCR 0xA4050104UL
230#define PORT_PDCR 0xA4050106UL
231#define PORT_PECR 0xA4050108UL
232#define PORT_PFCR 0xA405010AUL
233#define PORT_PGCR 0xA405010CUL
234#define PORT_PHCR 0xA405010EUL
235#define PORT_PJCR 0xA4050110UL
236#define PORT_PKCR 0xA4050112UL
237#define PORT_PLCR 0xA4050114UL
238#define PORT_SCPCR 0xA4050116UL
239#define PORT_PMCR 0xA4050118UL
240#define PORT_PNCR 0xA405011AUL
241#define PORT_PQCR 0xA405011CUL
242#define PORT_PRCR 0xA405011EUL
243#define PORT_PTCR 0xA405014CUL
244#define PORT_PUCR 0xA405014EUL
245#define PORT_PVCR 0xA4050150UL
246
247#define PORT_PSELA 0xA4050140UL
248#define PORT_PSELB 0xA4050142UL
249#define PORT_PSELC 0xA4050144UL
250#define PORT_PSELE 0xA4050158UL
251
252#define PORT_HIZCRA 0xA4050146UL
253#define PORT_HIZCRB 0xA4050148UL
254#define PORT_DRVCR 0xA405014AUL
255
256#define PORT_PADR 0xA4050120UL
257#define PORT_PBDR 0xA4050122UL
258#define PORT_PCDR 0xA4050124UL
259#define PORT_PDDR 0xA4050126UL
260#define PORT_PEDR 0xA4050128UL
261#define PORT_PFDR 0xA405012AUL
262#define PORT_PGDR 0xA405012CUL
263#define PORT_PHDR 0xA405012EUL
264#define PORT_PJDR 0xA4050130UL
265#define PORT_PKDR 0xA4050132UL
266#define PORT_PLDR 0xA4050134UL
267#define PORT_SCPDR 0xA4050136UL
268#define PORT_PMDR 0xA4050138UL
269#define PORT_PNDR 0xA405013AUL
270#define PORT_PQDR 0xA405013CUL
271#define PORT_PRDR 0xA405013EUL
272#define PORT_PTDR 0xA405016CUL
273#define PORT_PUDR 0xA405016EUL
274#define PORT_PVDR 0xA4050170UL
275
276#define IRQ0_IRQ 32
277#define IRQ1_IRQ 33
278#define IRQ2_IRQ 34
279#define IRQ3_IRQ 35
280#define IRQ4_IRQ 36
281#define IRQ5_IRQ 37
282#define IRQ6_IRQ 38
283#define IRQ7_IRQ 39
284
285#define INTPRI00 0xA4140010UL
286
287#define IRQ0_IPR_ADDR INTPRI00
288#define IRQ1_IPR_ADDR INTPRI00
289#define IRQ2_IPR_ADDR INTPRI00
290#define IRQ3_IPR_ADDR INTPRI00
291#define IRQ4_IPR_ADDR INTPRI00
292#define IRQ5_IPR_ADDR INTPRI00
293#define IRQ6_IPR_ADDR INTPRI00
294#define IRQ7_IPR_ADDR INTPRI00
295
296#define IRQ0_IPR_POS 7
297#define IRQ1_IPR_POS 6
298#define IRQ2_IPR_POS 5
299#define IRQ3_IPR_POS 4
300#define IRQ4_IPR_POS 3
301#define IRQ5_IPR_POS 2
302#define IRQ6_IPR_POS 1
303#define IRQ7_IPR_POS 0
304
305#define IRQ0_PRIORITY 1
306#define IRQ1_PRIORITY 1
307#define IRQ2_PRIORITY 1
308#define IRQ3_PRIORITY 1
309#define IRQ4_PRIORITY 1
310#define IRQ5_PRIORITY 1
311#define IRQ6_PRIORITY 1
312#define IRQ7_PRIORITY 1
313
314#endif /* __ASM_SH_IRQ_SH73180_H */
diff --git a/include/asm-sh/irq-sh7343.h b/include/asm-sh/irq-sh7343.h
deleted file mode 100644
index 5d15419b53b0..000000000000
--- a/include/asm-sh/irq-sh7343.h
+++ /dev/null
@@ -1,317 +0,0 @@
1#ifndef __ASM_SH_IRQ_SH7343_H
2#define __ASM_SH_IRQ_SH7343_H
3
4/*
5 * linux/include/asm-sh/irq-sh7343.h
6 *
7 * Copyright (C) 2006 Kenati Technologies Inc.
8 * Andre Mccurdy <andre@kenati.com>
9 * Ranjit Deshpande <ranjit@kenati.com>
10 */
11
12#undef INTC_IPRA
13#undef INTC_IPRB
14#undef INTC_IPRC
15#undef INTC_IPRD
16
17#undef DMTE0_IRQ
18#undef DMTE1_IRQ
19#undef DMTE2_IRQ
20#undef DMTE3_IRQ
21#undef DMTE4_IRQ
22#undef DMTE5_IRQ
23#undef DMTE6_IRQ
24#undef DMTE7_IRQ
25#undef DMAE_IRQ
26#undef DMA_IPR_ADDR
27#undef DMA_IPR_POS
28#undef DMA_PRIORITY
29
30#undef INTC_IMCR0
31#undef INTC_IMCR1
32#undef INTC_IMCR2
33#undef INTC_IMCR3
34#undef INTC_IMCR4
35#undef INTC_IMCR5
36#undef INTC_IMCR6
37#undef INTC_IMCR7
38#undef INTC_IMCR8
39#undef INTC_IMCR9
40#undef INTC_IMCR10
41
42
43#define INTC_IPRA 0xA4080000UL
44#define INTC_IPRB 0xA4080004UL
45#define INTC_IPRC 0xA4080008UL
46#define INTC_IPRD 0xA408000CUL
47#define INTC_IPRE 0xA4080010UL
48#define INTC_IPRF 0xA4080014UL
49#define INTC_IPRG 0xA4080018UL
50#define INTC_IPRH 0xA408001CUL
51#define INTC_IPRI 0xA4080020UL
52#define INTC_IPRJ 0xA4080024UL
53#define INTC_IPRK 0xA4080028UL
54#define INTC_IPRL 0xA408002CUL
55
56#define INTC_IMR0 0xA4080080UL
57#define INTC_IMR1 0xA4080084UL
58#define INTC_IMR2 0xA4080088UL
59#define INTC_IMR3 0xA408008CUL
60#define INTC_IMR4 0xA4080090UL
61#define INTC_IMR5 0xA4080094UL
62#define INTC_IMR6 0xA4080098UL
63#define INTC_IMR7 0xA408009CUL
64#define INTC_IMR8 0xA40800A0UL
65#define INTC_IMR9 0xA40800A4UL
66#define INTC_IMR10 0xA40800A8UL
67#define INTC_IMR11 0xA40800ACUL
68
69#define INTC_IMCR0 0xA40800C0UL
70#define INTC_IMCR1 0xA40800C4UL
71#define INTC_IMCR2 0xA40800C8UL
72#define INTC_IMCR3 0xA40800CCUL
73#define INTC_IMCR4 0xA40800D0UL
74#define INTC_IMCR5 0xA40800D4UL
75#define INTC_IMCR6 0xA40800D8UL
76#define INTC_IMCR7 0xA40800DCUL
77#define INTC_IMCR8 0xA40800E0UL
78#define INTC_IMCR9 0xA40800E4UL
79#define INTC_IMCR10 0xA40800E8UL
80#define INTC_IMCR11 0xA40800ECUL
81
82#define INTC_ICR0 0xA4140000UL
83#define INTC_ICR1 0xA414001CUL
84
85#define INTMSK0 0xa4140044
86#define INTMSKCLR0 0xa4140064
87#define INTC_INTPRI0 0xa4140010
88
89/*
90 NOTE:
91
92 *_IRQ = (INTEVT2 - 0x200)/0x20
93*/
94
95/* TMU0 */
96#define TMU0_IRQ 16
97#define TMU0_IPR_ADDR INTC_IPRA
98#define TMU0_IPR_POS 3
99#define TMU0_PRIORITY 2
100
101#define TIMER_IRQ 16
102#define TIMER_IPR_ADDR INTC_IPRA
103#define TIMER_IPR_POS 3
104#define TIMER_PRIORITY 2
105
106/* TMU1 */
107#define TMU1_IRQ 17
108#define TMU1_IPR_ADDR INTC_IPRA
109#define TMU1_IPR_POS 2
110#define TMU1_PRIORITY 2
111
112/* TMU2 */
113#define TMU2_IRQ 18
114#define TMU2_IPR_ADDR INTC_IPRA
115#define TMU2_IPR_POS 1
116#define TMU2_PRIORITY 2
117
118/* LCDC */
119#define LCDC_IRQ 28
120#define LCDC_IPR_ADDR INTC_IPRB
121#define LCDC_IPR_POS 2
122#define LCDC_PRIORITY 2
123
124/* VIO (Video I/O) */
125#define CEU_IRQ 52
126#define BEU_IRQ 53
127#define VEU_IRQ 54
128#define VOU_IRQ 55
129#define VIO_IPR_ADDR INTC_IPRE
130#define VIO_IPR_POS 2
131#define VIO_PRIORITY 2
132
133/* MFI (Multi Functional Interface) */
134#define MFI_IRQ 56
135#define MFI_IPR_ADDR INTC_IPRE
136#define MFI_IPR_POS 1
137#define MFI_PRIORITY 2
138
139/* VPU (Video Processing Unit) */
140#define VPU_IRQ 60
141#define VPU_IPR_ADDR INTC_IPRE
142#define VPU_IPR_POS 0
143#define VPU_PRIORITY 2
144
145/* 3DG */
146#define TDG_IRQ 63
147#define TDG_IPR_ADDR INTC_IPRJ
148#define TDG_IPR_POS 2
149#define TDG_PRIORITY 2
150
151/* DMAC(1) */
152#define DMTE0_IRQ 48
153#define DMTE1_IRQ 49
154#define DMTE2_IRQ 50
155#define DMTE3_IRQ 51
156#define DMA1_IPR_ADDR INTC_IPRE
157#define DMA1_IPR_POS 3
158#define DMA1_PRIORITY 7
159
160/* DMAC(2) */
161#define DMTE4_IRQ 76
162#define DMTE5_IRQ 77
163#define DMA2_IPR_ADDR INTC_IPRF
164#define DMA2_IPR_POS 2
165#define DMA2_PRIORITY 7
166
167/* SCIF0 */
168#define SCIF_ERI_IRQ 80
169#define SCIF_RXI_IRQ 81
170#define SCIF_BRI_IRQ 82
171#define SCIF_TXI_IRQ 83
172#define SCIF_IPR_ADDR INTC_IPRG
173#define SCIF_IPR_POS 3
174#define SCIF_PRIORITY 3
175
176/* SIOF0 */
177#define SIOF0_IRQ 84
178#define SIOF0_IPR_ADDR INTC_IPRH
179#define SIOF0_IPR_POS 3
180#define SIOF0_PRIORITY 3
181
182/* FLCTL (Flash Memory Controller) */
183#define FLSTE_IRQ 92
184#define FLTEND_IRQ 93
185#define FLTRQ0_IRQ 94
186#define FLTRQ1_IRQ 95
187#define FLCTL_IPR_ADDR INTC_IPRH
188#define FLCTL_IPR_POS 1
189#define FLCTL_PRIORITY 3
190
191/* IIC(0) (IIC Bus Interface) */
192#define IIC0_ALI_IRQ 96
193#define IIC0_TACKI_IRQ 97
194#define IIC0_WAITI_IRQ 98
195#define IIC0_DTEI_IRQ 99
196#define IIC0_IPR_ADDR INTC_IPRH
197#define IIC0_IPR_POS 0
198#define IIC0_PRIORITY 3
199
200/* IIC(1) (IIC Bus Interface) */
201#define IIC1_ALI_IRQ 44
202#define IIC1_TACKI_IRQ 45
203#define IIC1_WAITI_IRQ 46
204#define IIC1_DTEI_IRQ 47
205#define IIC1_IPR_ADDR INTC_IPRI
206#define IIC1_IPR_POS 0
207#define IIC1_PRIORITY 3
208
209/* SIO0 */
210#define SIO0_IRQ 88
211#define SIO0_IPR_ADDR INTC_IPRI
212#define SIO0_IPR_POS 3
213#define SIO0_PRIORITY 3
214
215/* SDHI */
216#define SDHI_SDHII0_IRQ 100
217#define SDHI_SDHII1_IRQ 101
218#define SDHI_SDHII2_IRQ 102
219#define SDHI_SDHII3_IRQ 103
220#define SDHI_IPR_ADDR INTC_IPRK
221#define SDHI_IPR_POS 0
222#define SDHI_PRIORITY 3
223
224/* SIU (Sound Interface Unit) */
225#define SIU_IRQ 108
226#define SIU_IPR_ADDR INTC_IPRJ
227#define SIU_IPR_POS 1
228#define SIU_PRIORITY 3
229
230#define PORT_PACR 0xA4050100UL
231#define PORT_PBCR 0xA4050102UL
232#define PORT_PCCR 0xA4050104UL
233#define PORT_PDCR 0xA4050106UL
234#define PORT_PECR 0xA4050108UL
235#define PORT_PFCR 0xA405010AUL
236#define PORT_PGCR 0xA405010CUL
237#define PORT_PHCR 0xA405010EUL
238#define PORT_PJCR 0xA4050110UL
239#define PORT_PKCR 0xA4050112UL
240#define PORT_PLCR 0xA4050114UL
241#define PORT_SCPCR 0xA4050116UL
242#define PORT_PMCR 0xA4050118UL
243#define PORT_PNCR 0xA405011AUL
244#define PORT_PQCR 0xA405011CUL
245#define PORT_PRCR 0xA405011EUL
246#define PORT_PTCR 0xA405014CUL
247#define PORT_PUCR 0xA405014EUL
248#define PORT_PVCR 0xA4050150UL
249
250#define PORT_PSELA 0xA4050140UL
251#define PORT_PSELB 0xA4050142UL
252#define PORT_PSELC 0xA4050144UL
253#define PORT_PSELE 0xA4050158UL
254
255#define PORT_HIZCRA 0xA4050146UL
256#define PORT_HIZCRB 0xA4050148UL
257#define PORT_DRVCR 0xA405014AUL
258
259#define PORT_PADR 0xA4050120UL
260#define PORT_PBDR 0xA4050122UL
261#define PORT_PCDR 0xA4050124UL
262#define PORT_PDDR 0xA4050126UL
263#define PORT_PEDR 0xA4050128UL
264#define PORT_PFDR 0xA405012AUL
265#define PORT_PGDR 0xA405012CUL
266#define PORT_PHDR 0xA405012EUL
267#define PORT_PJDR 0xA4050130UL
268#define PORT_PKDR 0xA4050132UL
269#define PORT_PLDR 0xA4050134UL
270#define PORT_SCPDR 0xA4050136UL
271#define PORT_PMDR 0xA4050138UL
272#define PORT_PNDR 0xA405013AUL
273#define PORT_PQDR 0xA405013CUL
274#define PORT_PRDR 0xA405013EUL
275#define PORT_PTDR 0xA405016CUL
276#define PORT_PUDR 0xA405016EUL
277#define PORT_PVDR 0xA4050170UL
278
279#define IRQ0_IRQ 32
280#define IRQ1_IRQ 33
281#define IRQ2_IRQ 34
282#define IRQ3_IRQ 35
283#define IRQ4_IRQ 36
284#define IRQ5_IRQ 37
285#define IRQ6_IRQ 38
286#define IRQ7_IRQ 39
287
288#define INTPRI00 0xA4140010UL
289
290#define IRQ0_IPR_ADDR INTPRI00
291#define IRQ1_IPR_ADDR INTPRI00
292#define IRQ2_IPR_ADDR INTPRI00
293#define IRQ3_IPR_ADDR INTPRI00
294#define IRQ4_IPR_ADDR INTPRI00
295#define IRQ5_IPR_ADDR INTPRI00
296#define IRQ6_IPR_ADDR INTPRI00
297#define IRQ7_IPR_ADDR INTPRI00
298
299#define IRQ0_IPR_POS 7
300#define IRQ1_IPR_POS 6
301#define IRQ2_IPR_POS 5
302#define IRQ3_IPR_POS 4
303#define IRQ4_IPR_POS 3
304#define IRQ5_IPR_POS 2
305#define IRQ6_IPR_POS 1
306#define IRQ7_IPR_POS 0
307
308#define IRQ0_PRIORITY 1
309#define IRQ1_PRIORITY 1
310#define IRQ2_PRIORITY 1
311#define IRQ3_PRIORITY 1
312#define IRQ4_PRIORITY 1
313#define IRQ5_PRIORITY 1
314#define IRQ6_PRIORITY 1
315#define IRQ7_PRIORITY 1
316
317#endif /* __ASM_SH_IRQ_SH7343_H */
diff --git a/include/asm-sh/irq-sh7780.h b/include/asm-sh/irq-sh7780.h
deleted file mode 100644
index 19912ae6a7f7..000000000000
--- a/include/asm-sh/irq-sh7780.h
+++ /dev/null
@@ -1,311 +0,0 @@
1#ifndef __ASM_SH_IRQ_SH7780_H
2#define __ASM_SH_IRQ_SH7780_H
3
4/*
5 * linux/include/asm-sh/irq-sh7780.h
6 *
7 * Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp>
8 */
9#define INTC_BASE 0xffd00000
10#define INTC_ICR0 (INTC_BASE+0x0)
11#define INTC_ICR1 (INTC_BASE+0x1c)
12#define INTC_INTPRI (INTC_BASE+0x10)
13#define INTC_INTREQ (INTC_BASE+0x24)
14#define INTC_INTMSK0 (INTC_BASE+0x44)
15#define INTC_INTMSK1 (INTC_BASE+0x48)
16#define INTC_INTMSK2 (INTC_BASE+0x40080)
17#define INTC_INTMSKCLR0 (INTC_BASE+0x64)
18#define INTC_INTMSKCLR1 (INTC_BASE+0x68)
19#define INTC_INTMSKCLR2 (INTC_BASE+0x40084)
20#define INTC_NMIFCR (INTC_BASE+0xc0)
21#define INTC_USERIMASK (INTC_BASE+0x30000)
22
23#define INTC_INT2PRI0 (INTC_BASE+0x40000)
24#define INTC_INT2PRI1 (INTC_BASE+0x40004)
25#define INTC_INT2PRI2 (INTC_BASE+0x40008)
26#define INTC_INT2PRI3 (INTC_BASE+0x4000c)
27#define INTC_INT2PRI4 (INTC_BASE+0x40010)
28#define INTC_INT2PRI5 (INTC_BASE+0x40014)
29#define INTC_INT2PRI6 (INTC_BASE+0x40018)
30#define INTC_INT2PRI7 (INTC_BASE+0x4001c)
31#define INTC_INT2A0 (INTC_BASE+0x40030)
32#define INTC_INT2A1 (INTC_BASE+0x40034)
33#define INTC_INT2MSKR (INTC_BASE+0x40038)
34#define INTC_INT2MSKCR (INTC_BASE+0x4003c)
35#define INTC_INT2B0 (INTC_BASE+0x40040)
36#define INTC_INT2B1 (INTC_BASE+0x40044)
37#define INTC_INT2B2 (INTC_BASE+0x40048)
38#define INTC_INT2B3 (INTC_BASE+0x4004c)
39#define INTC_INT2B4 (INTC_BASE+0x40050)
40#define INTC_INT2B5 (INTC_BASE+0x40054)
41#define INTC_INT2B6 (INTC_BASE+0x40058)
42#define INTC_INT2B7 (INTC_BASE+0x4005c)
43#define INTC_INT2GPIC (INTC_BASE+0x40090)
44/*
45 NOTE:
46 *_IRQ = (INTEVT2 - 0x200)/0x20
47*/
48/* IRQ 0-7 line external int*/
49#define IRQ0_IRQ 2
50#define IRQ0_IPR_ADDR INTC_INTPRI
51#define IRQ0_IPR_POS 7
52#define IRQ0_PRIORITY 2
53
54#define IRQ1_IRQ 4
55#define IRQ1_IPR_ADDR INTC_INTPRI
56#define IRQ1_IPR_POS 6
57#define IRQ1_PRIORITY 2
58
59#define IRQ2_IRQ 6
60#define IRQ2_IPR_ADDR INTC_INTPRI
61#define IRQ2_IPR_POS 5
62#define IRQ2_PRIORITY 2
63
64#define IRQ3_IRQ 8
65#define IRQ3_IPR_ADDR INTC_INTPRI
66#define IRQ3_IPR_POS 4
67#define IRQ3_PRIORITY 2
68
69#define IRQ4_IRQ 10
70#define IRQ4_IPR_ADDR INTC_INTPRI
71#define IRQ4_IPR_POS 3
72#define IRQ4_PRIORITY 2
73
74#define IRQ5_IRQ 12
75#define IRQ5_IPR_ADDR INTC_INTPRI
76#define IRQ5_IPR_POS 2
77#define IRQ5_PRIORITY 2
78
79#define IRQ6_IRQ 14
80#define IRQ6_IPR_ADDR INTC_INTPRI
81#define IRQ6_IPR_POS 1
82#define IRQ6_PRIORITY 2
83
84#define IRQ7_IRQ 0
85#define IRQ7_IPR_ADDR INTC_INTPRI
86#define IRQ7_IPR_POS 0
87#define IRQ7_PRIORITY 2
88
89/* TMU */
90/* ch0 */
91#define TMU_IRQ 28
92#define TMU_IPR_ADDR INTC_INT2PRI0
93#define TMU_IPR_POS 3
94#define TMU_PRIORITY 2
95
96#define TIMER_IRQ 28
97#define TIMER_IPR_ADDR INTC_INT2PRI0
98#define TIMER_IPR_POS 3
99#define TIMER_PRIORITY 2
100
101/* ch 1*/
102#define TMU_CH1_IRQ 29
103#define TMU_CH1_IPR_ADDR INTC_INT2PRI0
104#define TMU_CH1_IPR_POS 2
105#define TMU_CH1_PRIORITY 2
106
107#define TIMER1_IRQ 29
108#define TIMER1_IPR_ADDR INTC_INT2PRI0
109#define TIMER1_IPR_POS 2
110#define TIMER1_PRIORITY 2
111
112/* ch 2*/
113#define TMU_CH2_IRQ 30
114#define TMU_CH2_IPR_ADDR INTC_INT2PRI0
115#define TMU_CH2_IPR_POS 1
116#define TMU_CH2_PRIORITY 2
117/* ch 2 Input capture */
118#define TMU_CH2IC_IRQ 31
119#define TMU_CH2IC_IPR_ADDR INTC_INT2PRI0
120#define TMU_CH2IC_IPR_POS 0
121#define TMU_CH2IC_PRIORITY 2
122/* ch 3 */
123#define TMU_CH3_IRQ 96
124#define TMU_CH3_IPR_ADDR INTC_INT2PRI1
125#define TMU_CH3_IPR_POS 3
126#define TMU_CH3_PRIORITY 2
127/* ch 4 */
128#define TMU_CH4_IRQ 97
129#define TMU_CH4_IPR_ADDR INTC_INT2PRI1
130#define TMU_CH4_IPR_POS 2
131#define TMU_CH4_PRIORITY 2
132/* ch 5*/
133#define TMU_CH5_IRQ 98
134#define TMU_CH5_IPR_ADDR INTC_INT2PRI1
135#define TMU_CH5_IPR_POS 1
136#define TMU_CH5_PRIORITY 2
137
138/* SCIF0 */
139#define SCIF0_ERI_IRQ 40
140#define SCIF0_RXI_IRQ 41
141#define SCIF0_BRI_IRQ 42
142#define SCIF0_TXI_IRQ 43
143#define SCIF0_IPR_ADDR INTC_INT2PRI2
144#define SCIF0_IPR_POS 3
145#define SCIF0_PRIORITY 3
146
147/* SCIF1 */
148#define SCIF1_ERI_IRQ 76
149#define SCIF1_RXI_IRQ 77
150#define SCIF1_BRI_IRQ 78
151#define SCIF1_TXI_IRQ 79
152#define SCIF1_IPR_ADDR INTC_INT2PRI2
153#define SCIF1_IPR_POS 2
154#define SCIF1_PRIORITY 3
155
156#define WDT_IRQ 27
157#define WDT_IPR_ADDR INTC_INT2PRI2
158#define WDT_IPR_POS 1
159#define WDT_PRIORITY 2
160
161/* DMAC(0) */
162#define DMINT0_IRQ 34
163#define DMINT1_IRQ 35
164#define DMINT2_IRQ 36
165#define DMINT3_IRQ 37
166#define DMINT4_IRQ 44
167#define DMINT5_IRQ 45
168#define DMINT6_IRQ 46
169#define DMINT7_IRQ 47
170#define DMAE_IRQ 38
171#define DMA0_IPR_ADDR INTC_INT2PRI3
172#define DMA0_IPR_POS 2
173#define DMA0_PRIORITY 7
174
175/* DMAC(1) */
176#define DMINT8_IRQ 92
177#define DMINT9_IRQ 93
178#define DMINT10_IRQ 94
179#define DMINT11_IRQ 95
180#define DMA1_IPR_ADDR INTC_INT2PRI3
181#define DMA1_IPR_POS 1
182#define DMA1_PRIORITY 7
183
184#define DMTE0_IRQ DMINT0_IRQ
185#define DMTE4_IRQ DMINT4_IRQ
186#define DMA_IPR_ADDR DMA0_IPR_ADDR
187#define DMA_IPR_POS DMA0_IPR_POS
188#define DMA_PRIORITY DMA0_PRIORITY
189
190/* CMT */
191#define CMT_IRQ 56
192#define CMT_IPR_ADDR INTC_INT2PRI4
193#define CMT_IPR_POS 3
194#define CMT_PRIORITY 0
195
196/* HAC */
197#define HAC_IRQ 60
198#define HAC_IPR_ADDR INTC_INT2PRI4
199#define HAC_IPR_POS 2
200#define CMT_PRIORITY 0
201
202/* PCIC(0) */
203#define PCIC0_IRQ 64
204#define PCIC0_IPR_ADDR INTC_INT2PRI4
205#define PCIC0_IPR_POS 1
206#define PCIC0_PRIORITY 2
207
208/* PCIC(1) */
209#define PCIC1_IRQ 65
210#define PCIC1_IPR_ADDR INTC_INT2PRI4
211#define PCIC1_IPR_POS 0
212#define PCIC1_PRIORITY 2
213
214/* PCIC(2) */
215#define PCIC2_IRQ 66
216#define PCIC2_IPR_ADDR INTC_INT2PRI5
217#define PCIC2_IPR_POS 3
218#define PCIC2_PRIORITY 2
219
220/* PCIC(3) */
221#define PCIC3_IRQ 67
222#define PCIC3_IPR_ADDR INTC_INT2PRI5
223#define PCIC3_IPR_POS 2
224#define PCIC3_PRIORITY 2
225
226/* PCIC(4) */
227#define PCIC4_IRQ 68
228#define PCIC4_IPR_ADDR INTC_INT2PRI5
229#define PCIC4_IPR_POS 1
230#define PCIC4_PRIORITY 2
231
232/* PCIC(5) */
233#define PCICERR_IRQ 69
234#define PCICPWD3_IRQ 70
235#define PCICPWD2_IRQ 71
236#define PCICPWD1_IRQ 72
237#define PCICPWD0_IRQ 73
238#define PCIC5_IPR_ADDR INTC_INT2PRI5
239#define PCIC5_IPR_POS 0
240#define PCIC5_PRIORITY 2
241
242/* SIOF */
243#define SIOF_IRQ 80
244#define SIOF_IPR_ADDR INTC_INT2PRI6
245#define SIOF_IPR_POS 3
246#define SIOF_PRIORITY 3
247
248/* HSPI */
249#define HSPI_IRQ 84
250#define HSPI_IPR_ADDR INTC_INT2PRI6
251#define HSPI_IPR_POS 2
252#define HSPI_PRIORITY 3
253
254/* MMCIF */
255#define MMCIF_FSTAT_IRQ 88
256#define MMCIF_TRAN_IRQ 89
257#define MMCIF_ERR_IRQ 90
258#define MMCIF_FRDY_IRQ 91
259#define MMCIF_IPR_ADDR INTC_INT2PRI6
260#define MMCIF_IPR_POS 1
261#define HSPI_PRIORITY 3
262
263/* SSI */
264#define SSI_IRQ 100
265#define SSI_IPR_ADDR INTC_INT2PRI6
266#define SSI_IPR_POS 0
267#define SSI_PRIORITY 3
268
269/* FLCTL */
270#define FLCTL_FLSTE_IRQ 104
271#define FLCTL_FLTEND_IRQ 105
272#define FLCTL_FLTRQ0_IRQ 106
273#define FLCTL_FLTRQ1_IRQ 107
274#define FLCTL_IPR_ADDR INTC_INT2PRI7
275#define FLCTL_IPR_POS 3
276#define FLCTL_PRIORITY 3
277
278/* GPIO */
279#define GPIO0_IRQ 108
280#define GPIO1_IRQ 109
281#define GPIO2_IRQ 110
282#define GPIO3_IRQ 111
283#define GPIO_IPR_ADDR INTC_INT2PRI7
284#define GPIO_IPR_POS 2
285#define GPIO_PRIORITY 3
286
287#define INTC_TMU0_MSK 0
288#define INTC_TMU3_MSK 1
289#define INTC_RTC_MSK 2
290#define INTC_SCIF0_MSK 3
291#define INTC_SCIF1_MSK 4
292#define INTC_WDT_MSK 5
293#define INTC_HUID_MSK 7
294#define INTC_DMAC0_MSK 8
295#define INTC_DMAC1_MSK 9
296#define INTC_CMT_MSK 12
297#define INTC_HAC_MSK 13
298#define INTC_PCIC0_MSK 14
299#define INTC_PCIC1_MSK 15
300#define INTC_PCIC2_MSK 16
301#define INTC_PCIC3_MSK 17
302#define INTC_PCIC4_MSK 18
303#define INTC_PCIC5_MSK 19
304#define INTC_SIOF_MSK 20
305#define INTC_HSPI_MSK 21
306#define INTC_MMCIF_MSK 22
307#define INTC_SSI_MSK 23
308#define INTC_FLCTL_MSK 24
309#define INTC_GPIO_MSK 25
310
311#endif /* __ASM_SH_IRQ_SH7780_H */
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index d71326b3c90c..f10cfc10227e 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -1,265 +1,9 @@
1#ifndef __ASM_SH_IRQ_H 1#ifndef __ASM_SH_IRQ_H
2#define __ASM_SH_IRQ_H 2#define __ASM_SH_IRQ_H
3 3
4/*
5 *
6 * linux/include/asm-sh/irq.h
7 *
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2003 Paul Mundt
11 *
12 */
13
14#include <asm/machvec.h> 4#include <asm/machvec.h>
15#include <asm/ptrace.h> /* for pt_regs */ 5#include <asm/ptrace.h> /* for pt_regs */
16 6
17#if defined(CONFIG_CPU_SH2)
18#include <asm/cpu/irq.h>
19#endif
20
21#ifndef CONFIG_CPU_SUBTYPE_SH7780
22
23#define INTC_DMAC0_MSK 0
24
25#if defined(CONFIG_CPU_SH3)
26#define INTC_IPRA 0xfffffee2UL
27#define INTC_IPRB 0xfffffee4UL
28#elif defined(CONFIG_CPU_SH4)
29#define INTC_IPRA 0xffd00004UL
30#define INTC_IPRB 0xffd00008UL
31#define INTC_IPRC 0xffd0000cUL
32#define INTC_IPRD 0xffd00010UL
33#endif
34
35#if defined(CONFIG_CPU_SUBTYPE_SH7206)
36#ifdef CONFIG_SH_CMT
37#define TIMER_IRQ CMI0_IRQ
38#define TIMER_IPR_ADDR INTC_IPR08
39#define TIMER_IPR_POS 3
40#define TIMER_PRIORITY 2
41
42#define TIMER1_IRQ CMI1_IRQ
43#define TIMER1_IPR_ADDR INTC_IPR08
44#define TIMER1_IPR_POS 2
45#define TIMER1_PRIORITY 2
46#endif
47
48#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
49#define TIMER_IRQ CMI0_IRQ
50#define TIMER_IPR_ADDR INTC_IPRC
51#define TIMER_IPR_POS 1
52#define TIMER_PRIORITY 2
53
54#define TIMER1_IRQ CMI1_IRQ
55#define TIMER1_IPR_ADDR INTC_IPRC
56#define TIMER1_IPR_POS 0
57#define TIMER1_PRIORITY 4
58
59#else
60#define TIMER_IRQ 16
61#define TIMER_IPR_ADDR INTC_IPRA
62#define TIMER_IPR_POS 3
63#define TIMER_PRIORITY 2
64
65#define TIMER1_IRQ 17
66#define TIMER1_IPR_ADDR INTC_IPRA
67#define TIMER1_IPR_POS 2
68#define TIMER1_PRIORITY 4
69#endif
70
71#if !defined(CONFIG_CPU_SH2)
72#define RTC_IRQ 22
73#define RTC_IPR_ADDR INTC_IPRA
74#define RTC_IPR_POS 0
75#define RTC_PRIORITY TIMER_PRIORITY
76#endif
77
78#if defined(CONFIG_CPU_SH3)
79#define DMTE0_IRQ 48
80#define DMTE1_IRQ 49
81#define DMTE2_IRQ 50
82#define DMTE3_IRQ 51
83#define DMA_IPR_ADDR INTC_IPRE
84#define DMA_IPR_POS 3
85#define DMA_PRIORITY 7
86#if defined(CONFIG_CPU_SUBTYPE_SH7300)
87/* TMU2 */
88#define TIMER2_IRQ 18
89#define TIMER2_IPR_ADDR INTC_IPRA
90#define TIMER2_IPR_POS 1
91#define TIMER2_PRIORITY 2
92
93/* WDT */
94#define WDT_IRQ 27
95#define WDT_IPR_ADDR INTC_IPRB
96#define WDT_IPR_POS 3
97#define WDT_PRIORITY 2
98
99/* SIM (SIM Card Module) */
100#define SIM_ERI_IRQ 23
101#define SIM_RXI_IRQ 24
102#define SIM_TXI_IRQ 25
103#define SIM_TEND_IRQ 26
104#define SIM_IPR_ADDR INTC_IPRB
105#define SIM_IPR_POS 1
106#define SIM_PRIORITY 2
107
108/* VIO (Video I/O) */
109#define VIO_IRQ 52
110#define VIO_IPR_ADDR INTC_IPRE
111#define VIO_IPR_POS 2
112#define VIO_PRIORITY 2
113
114/* MFI (Multi Functional Interface) */
115#define MFI_IRQ 56
116#define MFI_IPR_ADDR INTC_IPRE
117#define MFI_IPR_POS 1
118#define MFI_PRIORITY 2
119
120/* VPU (Video Processing Unit) */
121#define VPU_IRQ 60
122#define VPU_IPR_ADDR INTC_IPRE
123#define VPU_IPR_POS 0
124#define VPU_PRIORITY 2
125
126/* KEY (Key Scan Interface) */
127#define KEY_IRQ 79
128#define KEY_IPR_ADDR INTC_IPRF
129#define KEY_IPR_POS 3
130#define KEY_PRIORITY 2
131
132/* CMT (Compare Match Timer) */
133#define CMT_IRQ 104
134#define CMT_IPR_ADDR INTC_IPRF
135#define CMT_IPR_POS 0
136#define CMT_PRIORITY 2
137
138/* DMAC(1) */
139#define DMTE0_IRQ 48
140#define DMTE1_IRQ 49
141#define DMTE2_IRQ 50
142#define DMTE3_IRQ 51
143#define DMA1_IPR_ADDR INTC_IPRE
144#define DMA1_IPR_POS 3
145#define DMA1_PRIORITY 7
146
147/* DMAC(2) */
148#define DMTE4_IRQ 76
149#define DMTE5_IRQ 77
150#define DMA2_IPR_ADDR INTC_IPRF
151#define DMA2_IPR_POS 2
152#define DMA2_PRIORITY 7
153
154/* SIOF0 */
155#define SIOF0_IRQ 84
156#define SIOF0_IPR_ADDR INTC_IPRH
157#define SIOF0_IPR_POS 3
158#define SIOF0_PRIORITY 3
159
160/* FLCTL (Flash Memory Controller) */
161#define FLSTE_IRQ 92
162#define FLTEND_IRQ 93
163#define FLTRQ0_IRQ 94
164#define FLTRQ1_IRQ 95
165#define FLCTL_IPR_ADDR INTC_IPRH
166#define FLCTL_IPR_POS 1
167#define FLCTL_PRIORITY 3
168
169/* IIC (IIC Bus Interface) */
170#define IIC_ALI_IRQ 96
171#define IIC_TACKI_IRQ 97
172#define IIC_WAITI_IRQ 98
173#define IIC_DTEI_IRQ 99
174#define IIC_IPR_ADDR INTC_IPRH
175#define IIC_IPR_POS 0
176#define IIC_PRIORITY 3
177
178/* SIO0 */
179#define SIO0_IRQ 88
180#define SIO0_IPR_ADDR INTC_IPRI
181#define SIO0_IPR_POS 3
182#define SIO0_PRIORITY 3
183
184/* SIU (Sound Interface Unit) */
185#define SIU_IRQ 108
186#define SIU_IPR_ADDR INTC_IPRJ
187#define SIU_IPR_POS 1
188#define SIU_PRIORITY 3
189
190#endif
191#elif defined(CONFIG_CPU_SH4)
192#define DMTE0_IRQ 34
193#define DMTE1_IRQ 35
194#define DMTE2_IRQ 36
195#define DMTE3_IRQ 37
196#define DMTE4_IRQ 44 /* 7751R only */
197#define DMTE5_IRQ 45 /* 7751R only */
198#define DMTE6_IRQ 46 /* 7751R only */
199#define DMTE7_IRQ 47 /* 7751R only */
200#define DMAE_IRQ 38
201#define DMA_IPR_ADDR INTC_IPRC
202#define DMA_IPR_POS 2
203#define DMA_PRIORITY 7
204#endif
205
206#if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
207 defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
208 defined (CONFIG_CPU_SUBTYPE_SH7751) || defined (CONFIG_CPU_SUBTYPE_SH7706)
209#define SCI_ERI_IRQ 23
210#define SCI_RXI_IRQ 24
211#define SCI_TXI_IRQ 25
212#define SCI_IPR_ADDR INTC_IPRB
213#define SCI_IPR_POS 1
214#define SCI_PRIORITY 3
215#endif
216
217#if defined(CONFIG_CPU_SUBTYPE_SH7300)
218#define SCIF0_IRQ 80
219#define SCIF0_IPR_ADDR INTC_IPRG
220#define SCIF0_IPR_POS 3
221#define SCIF0_PRIORITY 3
222#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
223 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
224 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
225 defined(CONFIG_CPU_SUBTYPE_SH7709)
226#define SCIF_ERI_IRQ 56
227#define SCIF_RXI_IRQ 57
228#define SCIF_BRI_IRQ 58
229#define SCIF_TXI_IRQ 59
230#define SCIF_IPR_ADDR INTC_IPRE
231#define SCIF_IPR_POS 1
232#define SCIF_PRIORITY 3
233
234#define IRDA_ERI_IRQ 52
235#define IRDA_RXI_IRQ 53
236#define IRDA_BRI_IRQ 54
237#define IRDA_TXI_IRQ 55
238#define IRDA_IPR_ADDR INTC_IPRE
239#define IRDA_IPR_POS 2
240#define IRDA_PRIORITY 3
241#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
242 defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
243#define SCIF_ERI_IRQ 40
244#define SCIF_RXI_IRQ 41
245#define SCIF_BRI_IRQ 42
246#define SCIF_TXI_IRQ 43
247#define SCIF_IPR_ADDR INTC_IPRC
248#define SCIF_IPR_POS 1
249#define SCIF_PRIORITY 3
250#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
251#define SCIF1_ERI_IRQ 23
252#define SCIF1_RXI_IRQ 24
253#define SCIF1_BRI_IRQ 25
254#define SCIF1_TXI_IRQ 26
255#define SCIF1_IPR_ADDR INTC_IPRB
256#define SCIF1_IPR_POS 1
257#define SCIF1_PRIORITY 3
258#endif /* ST40STB1 */
259
260#endif /* 775x / SH4-202 / ST40STB1 */
261#endif /* 7780 */
262
263/* NR_IRQS is made from three components: 7/* NR_IRQS is made from three components:
264 * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules 8 * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
265 * 2. PINT_NR_IRQS - number of PINT interrupts 9 * 2. PINT_NR_IRQS - number of PINT interrupts
@@ -348,50 +92,12 @@
348/* NR_IRQS. 1+2+3 */ 92/* NR_IRQS. 1+2+3 */
349#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS) 93#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
350 94
351extern void disable_irq(unsigned int);
352extern void disable_irq_nosync(unsigned int);
353extern void enable_irq(unsigned int);
354
355/* 95/*
356 * Simple Mask Register Support 96 * Simple Mask Register Support
357 */ 97 */
358extern void make_maskreg_irq(unsigned int irq); 98extern void make_maskreg_irq(unsigned int irq);
359extern unsigned short *irq_mask_register; 99extern unsigned short *irq_mask_register;
360 100
361#if defined(CONFIG_CPU_SUBTYPE_SH7619)
362#define IRQ0_IRQ 16
363#define IRQ1_IRQ 17
364#define IRQ2_IRQ 18
365#define IRQ3_IRQ 19
366#define IRQ4_IRQ 32
367#define IRQ5_IRQ 33
368#define IRQ6_IRQ 34
369#define IRQ7_IRQ 35
370#elif !defined(CONFIG_CPU_SUBTYPE_SH7206)
371#define IRQ0_IRQ 32
372#define IRQ1_IRQ 33
373#define IRQ2_IRQ 34
374#define IRQ3_IRQ 35
375#define IRQ4_IRQ 36
376#define IRQ5_IRQ 37
377#endif
378
379#define IRQ0_PRIORITY 1
380#define IRQ1_PRIORITY 1
381#define IRQ2_PRIORITY 1
382#define IRQ3_PRIORITY 1
383#define IRQ4_PRIORITY 1
384#define IRQ5_PRIORITY 1
385
386#ifndef IRQ0_IPR_POS
387#define IRQ0_IPR_POS 0
388#define IRQ1_IPR_POS 1
389#define IRQ2_IPR_POS 2
390#define IRQ3_IPR_POS 3
391#define IRQ4_IPR_POS 0
392#define IRQ5_IPR_POS 1
393#endif
394
395/* 101/*
396 * PINT IRQs 102 * PINT IRQs
397 */ 103 */
@@ -410,350 +116,6 @@ struct ipr_data {
410extern void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs); 116extern void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
411extern void make_imask_irq(unsigned int irq); 117extern void make_imask_irq(unsigned int irq);
412 118
413#if defined(CONFIG_CPU_SUBTYPE_SH7300)
414#undef INTC_IPRA
415#undef INTC_IPRB
416#define INTC_IPRA 0xA414FEE2UL
417#define INTC_IPRB 0xA414FEE4UL
418#define INTC_IPRC 0xA4140016UL
419#define INTC_IPRD 0xA4140018UL
420#define INTC_IPRE 0xA414001AUL
421#define INTC_IPRF 0xA4080000UL
422#define INTC_IPRG 0xA4080002UL
423#define INTC_IPRH 0xA4080004UL
424#define INTC_IPRI 0xA4080006UL
425#define INTC_IPRJ 0xA4080008UL
426
427#define INTC_IMR0 0xA4080040UL
428#define INTC_IMR1 0xA4080042UL
429#define INTC_IMR2 0xA4080044UL
430#define INTC_IMR3 0xA4080046UL
431#define INTC_IMR4 0xA4080048UL
432#define INTC_IMR5 0xA408004AUL
433#define INTC_IMR6 0xA408004CUL
434#define INTC_IMR7 0xA408004EUL
435#define INTC_IMR8 0xA4080050UL
436#define INTC_IMR9 0xA4080052UL
437#define INTC_IMR10 0xA4080054UL
438
439#define INTC_IMCR0 0xA4080060UL
440#define INTC_IMCR1 0xA4080062UL
441#define INTC_IMCR2 0xA4080064UL
442#define INTC_IMCR3 0xA4080066UL
443#define INTC_IMCR4 0xA4080068UL
444#define INTC_IMCR5 0xA408006AUL
445#define INTC_IMCR6 0xA408006CUL
446#define INTC_IMCR7 0xA408006EUL
447#define INTC_IMCR8 0xA4080070UL
448#define INTC_IMCR9 0xA4080072UL
449#define INTC_IMCR10 0xA4080074UL
450
451#define INTC_ICR0 0xA414FEE0UL
452#define INTC_ICR1 0xA4140010UL
453
454#define INTC_IRR0 0xA4140004UL
455
456#define PORT_PACR 0xA4050100UL
457#define PORT_PBCR 0xA4050102UL
458#define PORT_PCCR 0xA4050104UL
459#define PORT_PDCR 0xA4050106UL
460#define PORT_PECR 0xA4050108UL
461#define PORT_PFCR 0xA405010AUL
462#define PORT_PGCR 0xA405010CUL
463#define PORT_PHCR 0xA405010EUL
464#define PORT_PJCR 0xA4050110UL
465#define PORT_PKCR 0xA4050112UL
466#define PORT_PLCR 0xA4050114UL
467#define PORT_SCPCR 0xA4050116UL
468#define PORT_PMCR 0xA4050118UL
469#define PORT_PNCR 0xA405011AUL
470#define PORT_PQCR 0xA405011CUL
471
472#define PORT_PSELA 0xA4050140UL
473#define PORT_PSELB 0xA4050142UL
474#define PORT_PSELC 0xA4050144UL
475
476#define PORT_HIZCRA 0xA4050146UL
477#define PORT_HIZCRB 0xA4050148UL
478#define PORT_DRVCR 0xA4050150UL
479
480#define PORT_PADR 0xA4050120UL
481#define PORT_PBDR 0xA4050122UL
482#define PORT_PCDR 0xA4050124UL
483#define PORT_PDDR 0xA4050126UL
484#define PORT_PEDR 0xA4050128UL
485#define PORT_PFDR 0xA405012AUL
486#define PORT_PGDR 0xA405012CUL
487#define PORT_PHDR 0xA405012EUL
488#define PORT_PJDR 0xA4050130UL
489#define PORT_PKDR 0xA4050132UL
490#define PORT_PLDR 0xA4050134UL
491#define PORT_SCPDR 0xA4050136UL
492#define PORT_PMDR 0xA4050138UL
493#define PORT_PNDR 0xA405013AUL
494#define PORT_PQDR 0xA405013CUL
495
496#define IRQ0_IRQ 32
497#define IRQ1_IRQ 33
498#define IRQ2_IRQ 34
499#define IRQ3_IRQ 35
500#define IRQ4_IRQ 36
501#define IRQ5_IRQ 37
502
503#define IRQ0_IPR_ADDR INTC_IPRC
504#define IRQ1_IPR_ADDR INTC_IPRC
505#define IRQ2_IPR_ADDR INTC_IPRC
506#define IRQ3_IPR_ADDR INTC_IPRC
507#define IRQ4_IPR_ADDR INTC_IPRD
508#define IRQ5_IPR_ADDR INTC_IPRD
509
510#define IRQ0_IPR_POS 0
511#define IRQ1_IPR_POS 1
512#define IRQ2_IPR_POS 2
513#define IRQ3_IPR_POS 3
514#define IRQ4_IPR_POS 0
515#define IRQ5_IPR_POS 1
516
517#define IRQ0_PRIORITY 1
518#define IRQ1_PRIORITY 1
519#define IRQ2_PRIORITY 1
520#define IRQ3_PRIORITY 1
521#define IRQ4_PRIORITY 1
522#define IRQ5_PRIORITY 1
523
524extern int ipr_irq_demux(int irq);
525#define __irq_demux(irq) ipr_irq_demux(irq)
526
527#elif defined(CONFIG_CPU_SUBTYPE_SH7604)
528#define INTC_IPRA 0xfffffee2UL
529#define INTC_IPRB 0xfffffe60UL
530
531#define INTC_VCRA 0xfffffe62UL
532#define INTC_VCRB 0xfffffe64UL
533#define INTC_VCRC 0xfffffe66UL
534#define INTC_VCRD 0xfffffe68UL
535
536#define INTC_VCRWDT 0xfffffee4UL
537#define INTC_VCRDIV 0xffffff0cUL
538#define INTC_VCRDMA0 0xffffffa0UL
539#define INTC_VCRDMA1 0xffffffa8UL
540
541#define INTC_ICR 0xfffffee0UL
542#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
543 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
544 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
545 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
546 defined(CONFIG_CPU_SUBTYPE_SH7710)
547#define INTC_IRR0 0xa4000004UL
548#define INTC_IRR1 0xa4000006UL
549#define INTC_IRR2 0xa4000008UL
550
551#define INTC_ICR0 0xfffffee0UL
552#define INTC_ICR1 0xa4000010UL
553#define INTC_ICR2 0xa4000012UL
554#define INTC_INTER 0xa4000014UL
555
556#define INTC_IPRC 0xa4000016UL
557#define INTC_IPRD 0xa4000018UL
558#define INTC_IPRE 0xa400001aUL
559#if defined(CONFIG_CPU_SUBTYPE_SH7707)
560#define INTC_IPRF 0xa400001cUL
561#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
562#define INTC_IPRF 0xa4080000UL
563#define INTC_IPRG 0xa4080002UL
564#define INTC_IPRH 0xa4080004UL
565#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
566/* Interrupt Controller Registers */
567#undef INTC_IPRA
568#undef INTC_IPRB
569#define INTC_IPRA 0xA414FEE2UL
570#define INTC_IPRB 0xA414FEE4UL
571#define INTC_IPRF 0xA4080000UL
572#define INTC_IPRG 0xA4080002UL
573#define INTC_IPRH 0xA4080004UL
574#define INTC_IPRI 0xA4080006UL
575
576#undef INTC_ICR0
577#undef INTC_ICR1
578#define INTC_ICR0 0xA414FEE0UL
579#define INTC_ICR1 0xA4140010UL
580
581#define INTC_IRR0 0xa4000004UL
582#define INTC_IRR1 0xa4000006UL
583#define INTC_IRR2 0xa4000008UL
584#define INTC_IRR3 0xa400000AUL
585#define INTC_IRR4 0xa400000CUL
586#define INTC_IRR5 0xa4080020UL
587#define INTC_IRR7 0xa4080024UL
588#define INTC_IRR8 0xa4080026UL
589
590/* Interrupt numbers */
591#define TIMER2_IRQ 18
592#define TIMER2_IPR_ADDR INTC_IPRA
593#define TIMER2_IPR_POS 1
594#define TIMER2_PRIORITY 2
595
596/* WDT */
597#define WDT_IRQ 27
598#define WDT_IPR_ADDR INTC_IPRB
599#define WDT_IPR_POS 3
600#define WDT_PRIORITY 2
601
602#define SCIF0_ERI_IRQ 52
603#define SCIF0_RXI_IRQ 53
604#define SCIF0_BRI_IRQ 54
605#define SCIF0_TXI_IRQ 55
606#define SCIF0_IPR_ADDR INTC_IPRE
607#define SCIF0_IPR_POS 2
608#define SCIF0_PRIORITY 3
609
610#define DMTE4_IRQ 76
611#define DMTE5_IRQ 77
612#define DMA2_IPR_ADDR INTC_IPRF
613#define DMA2_IPR_POS 2
614#define DMA2_PRIORITY 7
615
616#define IPSEC_IRQ 79
617#define IPSEC_IPR_ADDR INTC_IPRF
618#define IPSEC_IPR_POS 3
619#define IPSEC_PRIORITY 3
620
621/* EDMAC */
622#define EDMAC0_IRQ 80
623#define EDMAC0_IPR_ADDR INTC_IPRG
624#define EDMAC0_IPR_POS 3
625#define EDMAC0_PRIORITY 3
626
627#define EDMAC1_IRQ 81
628#define EDMAC1_IPR_ADDR INTC_IPRG
629#define EDMAC1_IPR_POS 2
630#define EDMAC1_PRIORITY 3
631
632#define EDMAC2_IRQ 82
633#define EDMAC2_IPR_ADDR INTC_IPRG
634#define EDMAC2_IPR_POS 1
635#define EDMAC2_PRIORITY 3
636
637/* SIOF */
638#define SIOF0_ERI_IRQ 96
639#define SIOF0_TXI_IRQ 97
640#define SIOF0_RXI_IRQ 98
641#define SIOF0_CCI_IRQ 99
642#define SIOF0_IPR_ADDR INTC_IPRH
643#define SIOF0_IPR_POS 0
644#define SIOF0_PRIORITY 7
645
646#define SIOF1_ERI_IRQ 100
647#define SIOF1_TXI_IRQ 101
648#define SIOF1_RXI_IRQ 102
649#define SIOF1_CCI_IRQ 103
650#define SIOF1_IPR_ADDR INTC_IPRI
651#define SIOF1_IPR_POS 1
652#define SIOF1_PRIORITY 7
653#endif /* CONFIG_CPU_SUBTYPE_SH7710 */
654
655#if defined(CONFIG_CPU_SUBTYPE_SH7710)
656#define PORT_PACR 0xa4050100UL
657#define PORT_PBCR 0xa4050102UL
658#define PORT_PCCR 0xa4050104UL
659#define PORT_PETCR 0xa4050106UL
660#define PORT_PADR 0xa4050120UL
661#define PORT_PBDR 0xa4050122UL
662#define PORT_PCDR 0xa4050124UL
663#else
664#define PORT_PACR 0xa4000100UL
665#define PORT_PBCR 0xa4000102UL
666#define PORT_PCCR 0xa4000104UL
667#define PORT_PFCR 0xa400010aUL
668#define PORT_PADR 0xa4000120UL
669#define PORT_PBDR 0xa4000122UL
670#define PORT_PCDR 0xa4000124UL
671#define PORT_PFDR 0xa400012aUL
672#endif
673
674#define IRQ0_IRQ 32
675#define IRQ1_IRQ 33
676#define IRQ2_IRQ 34
677#define IRQ3_IRQ 35
678#define IRQ4_IRQ 36
679#define IRQ5_IRQ 37
680
681#define IRQ0_IPR_ADDR INTC_IPRC
682#define IRQ1_IPR_ADDR INTC_IPRC
683#define IRQ2_IPR_ADDR INTC_IPRC
684#define IRQ3_IPR_ADDR INTC_IPRC
685#define IRQ4_IPR_ADDR INTC_IPRD
686#define IRQ5_IPR_ADDR INTC_IPRD
687
688#define IRQ0_IPR_POS 0
689#define IRQ1_IPR_POS 1
690#define IRQ2_IPR_POS 2
691#define IRQ3_IPR_POS 3
692#define IRQ4_IPR_POS 0
693#define IRQ5_IPR_POS 1
694
695#define IRQ0_PRIORITY 1
696#define IRQ1_PRIORITY 1
697#define IRQ2_PRIORITY 1
698#define IRQ3_PRIORITY 1
699#define IRQ4_PRIORITY 1
700#define IRQ5_PRIORITY 1
701
702#define PINT0_IRQ 40
703#define PINT8_IRQ 41
704
705#define PINT0_IPR_ADDR INTC_IPRD
706#define PINT8_IPR_ADDR INTC_IPRD
707
708#define PINT0_IPR_POS 3
709#define PINT8_IPR_POS 2
710#define PINT0_PRIORITY 2
711#define PINT8_PRIORITY 2
712
713extern int ipr_irq_demux(int irq);
714#define __irq_demux(irq) ipr_irq_demux(irq)
715#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
716
717#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
718 defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
719#define INTC_ICR 0xffd00000
720#define INTC_ICR_NMIL (1<<15)
721#define INTC_ICR_MAI (1<<14)
722#define INTC_ICR_NMIB (1<<9)
723#define INTC_ICR_NMIE (1<<8)
724#define INTC_ICR_IRLM (1<<7)
725#endif
726
727#ifdef CONFIG_CPU_SUBTYPE_SH7780
728#include <asm/irq-sh7780.h>
729#endif
730
731/* SH with INTC2-style interrupts */
732#ifdef CONFIG_CPU_HAS_INTC2_IRQ
733#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
734#define INTC2_BASE 0xfe080000
735#define INTC2_FIRST_IRQ 64
736#define INTC2_INTREQ_OFFSET 0x20
737#define INTC2_INTMSK_OFFSET 0x40
738#define INTC2_INTMSKCLR_OFFSET 0x60
739#define NR_INTC2_IRQS 25
740#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
741#define INTC2_BASE 0xfe080000
742#define INTC2_FIRST_IRQ 48 /* INTEVT 0x800 */
743#define INTC2_INTREQ_OFFSET 0x20
744#define INTC2_INTMSK_OFFSET 0x40
745#define INTC2_INTMSKCLR_OFFSET 0x60
746#define NR_INTC2_IRQS 64
747#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
748#define INTC2_BASE 0xffd40000
749#define INTC2_FIRST_IRQ 21
750#define INTC2_INTMSK_OFFSET (0x38)
751#define INTC2_INTMSKCLR_OFFSET (0x3c)
752#define NR_INTC2_IRQS 60
753#endif
754
755#define INTC2_INTPRI_OFFSET 0x00
756
757struct intc2_data { 119struct intc2_data {
758 unsigned short irq; 120 unsigned short irq;
759 unsigned char ipr_offset, ipr_shift; 121 unsigned char ipr_offset, ipr_shift;
@@ -763,20 +125,14 @@ struct intc2_data {
763 125
764void make_intc2_irq(struct intc2_data *, unsigned int nr_irqs); 126void make_intc2_irq(struct intc2_data *, unsigned int nr_irqs);
765void init_IRQ_intc2(void); 127void init_IRQ_intc2(void);
766#endif
767
768extern int shmse_irq_demux(int irq);
769 128
770static inline int generic_irq_demux(int irq) 129static inline int generic_irq_demux(int irq)
771{ 130{
772 return irq; 131 return irq;
773} 132}
774 133
775#ifndef __irq_demux
776#define __irq_demux(irq) (irq)
777#endif
778#define irq_canonicalize(irq) (irq) 134#define irq_canonicalize(irq) (irq)
779#define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq)) 135#define irq_demux(irq) sh_mv.mv_irq_demux(irq)
780 136
781#ifdef CONFIG_4KSTACKS 137#ifdef CONFIG_4KSTACKS
782extern void irq_ctx_init(int cpu); 138extern void irq_ctx_init(int cpu);
@@ -787,12 +143,4 @@ extern void irq_ctx_exit(int cpu);
787# define irq_ctx_exit(cpu) do { } while (0) 143# define irq_ctx_exit(cpu) do { } while (0)
788#endif 144#endif
789 145
790#if defined(CONFIG_CPU_SUBTYPE_SH73180)
791#include <asm/irq-sh73180.h>
792#endif
793
794#if defined(CONFIG_CPU_SUBTYPE_SH7343)
795#include <asm/irq-sh7343.h>
796#endif
797
798#endif /* __ASM_SH_IRQ_H */ 146#endif /* __ASM_SH_IRQ_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 05:07:04 -0500