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Diffstat (limited to 'include/asm-sh')
-rw-r--r--include/asm-sh/hw_irq.h5
-rw-r--r--include/asm-sh/sh03/io.h9
-rw-r--r--include/asm-sh/snapgear.h12
3 files changed, 4 insertions, 22 deletions
diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index 921ddec6ccf4..8f5bf98d053e 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -41,11 +41,6 @@ struct ipr_desc {
41 41
42void register_ipr_controller(struct ipr_desc *); 42void register_ipr_controller(struct ipr_desc *);
43 43
44/*
45 * Enable individual interrupt mode for external IPR IRQs.
46 */
47void __init ipr_irq_enable_irlm(void);
48
49typedef unsigned char intc_enum; 44typedef unsigned char intc_enum;
50 45
51struct intc_vect { 46struct intc_vect {
diff --git a/include/asm-sh/sh03/io.h b/include/asm-sh/sh03/io.h
index 4ff1eb900301..c39c785bba94 100644
--- a/include/asm-sh/sh03/io.h
+++ b/include/asm-sh/sh03/io.h
@@ -11,22 +11,13 @@
11 11
12#include <linux/time.h> 12#include <linux/time.h>
13 13
14#define INTC_IPRD 0xffd00010UL
15
16#define IRL0_IRQ 2 14#define IRL0_IRQ 2
17#define IRL0_IPR_POS 3
18#define IRL0_PRIORITY 13 15#define IRL0_PRIORITY 13
19
20#define IRL1_IRQ 5 16#define IRL1_IRQ 5
21#define IRL1_IPR_POS 2
22#define IRL1_PRIORITY 10 17#define IRL1_PRIORITY 10
23
24#define IRL2_IRQ 8 18#define IRL2_IRQ 8
25#define IRL2_IPR_POS 1
26#define IRL2_PRIORITY 7 19#define IRL2_PRIORITY 7
27
28#define IRL3_IRQ 11 20#define IRL3_IRQ 11
29#define IRL3_IPR_POS 0
30#define IRL3_PRIORITY 4 21#define IRL3_PRIORITY 4
31 22
32void heartbeat_sh03(void); 23void heartbeat_sh03(void);
diff --git a/include/asm-sh/snapgear.h b/include/asm-sh/snapgear.h
index 3554e3a74e99..042d95f51c4d 100644
--- a/include/asm-sh/snapgear.h
+++ b/include/asm-sh/snapgear.h
@@ -19,20 +19,16 @@
19 * is the interrupt :-) 19 * is the interrupt :-)
20 */ 20 */
21 21
22#define IRL0_IRQ 2 22#define IRL0_IRQ 2
23#define IRL0_IPR_POS 3
24#define IRL0_PRIORITY 13 23#define IRL0_PRIORITY 13
25 24
26#define IRL1_IRQ 5 25#define IRL1_IRQ 5
27#define IRL1_IPR_POS 2
28#define IRL1_PRIORITY 10 26#define IRL1_PRIORITY 10
29 27
30#define IRL2_IRQ 8 28#define IRL2_IRQ 8
31#define IRL2_IPR_POS 1
32#define IRL2_PRIORITY 7 29#define IRL2_PRIORITY 7
33 30
34#define IRL3_IRQ 11 31#define IRL3_IRQ 11
35#define IRL3_IPR_POS 0
36#define IRL3_PRIORITY 4 32#define IRL3_PRIORITY 4
37#endif 33#endif
38 34