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-rw-r--r--include/asm-sh/bugs.h4
-rw-r--r--include/asm-sh/cache.h4
-rw-r--r--include/asm-sh/cpu-sh2/cache.h20
-rw-r--r--include/asm-sh/cpu-sh3/timer.h4
-rw-r--r--include/asm-sh/cpu-sh4/freq.h2
-rw-r--r--include/asm-sh/cpu-sh4/timer.h57
-rw-r--r--include/asm-sh/futex-irq.h111
-rw-r--r--include/asm-sh/futex.h79
-rw-r--r--include/asm-sh/hd64461.h397
-rw-r--r--include/asm-sh/hw_irq.h42
-rw-r--r--include/asm-sh/irq.h40
-rw-r--r--include/asm-sh/machvec.h4
-rw-r--r--include/asm-sh/machvec_init.h53
-rw-r--r--include/asm-sh/mmzone.h46
-rw-r--r--include/asm-sh/page.h10
-rw-r--r--include/asm-sh/parport.h16
-rw-r--r--include/asm-sh/processor.h8
-rw-r--r--include/asm-sh/rwsem.h6
-rw-r--r--include/asm-sh/saturn/io.h19
-rw-r--r--include/asm-sh/saturn/smpc.h34
-rw-r--r--include/asm-sh/sections.h2
-rw-r--r--include/asm-sh/setup.h1
-rw-r--r--include/asm-sh/sh03/io.h4
-rw-r--r--include/asm-sh/smp.h2
-rw-r--r--include/asm-sh/snapgear.h4
-rw-r--r--include/asm-sh/sparsemem.h16
-rw-r--r--include/asm-sh/system.h16
-rw-r--r--include/asm-sh/topology.h30
-rw-r--r--include/asm-sh/uaccess.h40
-rw-r--r--include/asm-sh/ubc.h9
30 files changed, 668 insertions, 412 deletions
diff --git a/include/asm-sh/bugs.h b/include/asm-sh/bugs.h
index 5a117ec43c77..aeee8da9c54f 100644
--- a/include/asm-sh/bugs.h
+++ b/include/asm-sh/bugs.h
@@ -22,7 +22,7 @@ static void __init check_bugs(void)
22 current_cpu_data.loops_per_jiffy = loops_per_jiffy; 22 current_cpu_data.loops_per_jiffy = loops_per_jiffy;
23 23
24 switch (current_cpu_data.type) { 24 switch (current_cpu_data.type) {
25 case CPU_SH7604 ... CPU_SH7619: 25 case CPU_SH7619:
26 *p++ = '2'; 26 *p++ = '2';
27 break; 27 break;
28 case CPU_SH7206: 28 case CPU_SH7206:
@@ -35,7 +35,7 @@ static void __init check_bugs(void)
35 case CPU_SH7750 ... CPU_SH4_501: 35 case CPU_SH7750 ... CPU_SH4_501:
36 *p++ = '4'; 36 *p++ = '4';
37 break; 37 break;
38 case CPU_SH7770 ... CPU_SH7785: 38 case CPU_SH7770 ... CPU_SHX3:
39 *p++ = '4'; 39 *p++ = '4';
40 *p++ = 'a'; 40 *p++ = 'a';
41 break; 41 break;
diff --git a/include/asm-sh/cache.h b/include/asm-sh/cache.h
index 9a3cb6ba9d15..7a18649d1ccb 100644
--- a/include/asm-sh/cache.h
+++ b/include/asm-sh/cache.h
@@ -9,6 +9,7 @@
9#define __ASM_SH_CACHE_H 9#define __ASM_SH_CACHE_H
10#ifdef __KERNEL__ 10#ifdef __KERNEL__
11 11
12#include <linux/init.h>
12#include <asm/cpu/cache.h> 13#include <asm/cpu/cache.h>
13 14
14#define SH_CACHE_VALID 1 15#define SH_CACHE_VALID 1
@@ -48,6 +49,9 @@ struct cache_info {
48 49
49 unsigned long flags; 50 unsigned long flags;
50}; 51};
52
53int __init detect_cpu_and_cache_system(void);
54
51#endif /* __ASSEMBLY__ */ 55#endif /* __ASSEMBLY__ */
52#endif /* __KERNEL__ */ 56#endif /* __KERNEL__ */
53#endif /* __ASM_SH_CACHE_H */ 57#endif /* __ASM_SH_CACHE_H */
diff --git a/include/asm-sh/cpu-sh2/cache.h b/include/asm-sh/cpu-sh2/cache.h
index 20b9796842dc..f02ba7a672b2 100644
--- a/include/asm-sh/cpu-sh2/cache.h
+++ b/include/asm-sh/cpu-sh2/cache.h
@@ -12,23 +12,7 @@
12 12
13#define L1_CACHE_SHIFT 4 13#define L1_CACHE_SHIFT 4
14 14
15#if defined(CONFIG_CPU_SUBTYPE_SH7604) 15#if defined(CONFIG_CPU_SUBTYPE_SH7619)
16#define CCR 0xfffffe92 /* Address of Cache Control Register */
17
18#define CCR_CACHE_CE 0x01 /* Cache enable */
19#define CCR_CACHE_ID 0x02 /* Instruction Replacement disable */
20#define CCR_CACHE_OD 0x04 /* Data Replacement disable */
21#define CCR_CACHE_TW 0x08 /* Two-way mode */
22#define CCR_CACHE_CP 0x10 /* Cache purge */
23
24#define CACHE_OC_ADDRESS_ARRAY 0x60000000
25
26#define CCR_CACHE_ENABLE CCR_CACHE_CE
27#define CCR_CACHE_INVALIDATE CCR_CACHE_CP
28#define CCR_CACHE_ORA CCR_CACHE_TW
29#define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */
30
31#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
32#define CCR1 0xffffffec 16#define CCR1 0xffffffec
33#define CCR CCR1 17#define CCR CCR1
34 18
@@ -49,5 +33,5 @@
49#define CCR_CACHE_ENABLE CCR_CACHE_CE 33#define CCR_CACHE_ENABLE CCR_CACHE_CE
50#define CCR_CACHE_INVALIDATE CCR_CACHE_CF 34#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
51#endif 35#endif
52#endif /* __ASM_CPU_SH2_CACHE_H */
53 36
37#endif /* __ASM_CPU_SH2_CACHE_H */
diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h
index b2394cf76f49..4928b08f9d19 100644
--- a/include/asm-sh/cpu-sh3/timer.h
+++ b/include/asm-sh/cpu-sh3/timer.h
@@ -29,7 +29,7 @@
29#endif 29#endif
30 30
31#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710) 31#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710)
32#define TMU_TSTR 0xa412fe92 /* Byte access */ 32#define TMU_012_TSTR 0xa412fe92 /* Byte access */
33 33
34#define TMU0_TCOR 0xa412fe94 /* Long access */ 34#define TMU0_TCOR 0xa412fe94 /* Long access */
35#define TMU0_TCNT 0xa412fe98 /* Long access */ 35#define TMU0_TCNT 0xa412fe98 /* Long access */
@@ -44,7 +44,7 @@
44#define TMU2_TCR 0xa412feb4 /* Word access */ 44#define TMU2_TCR 0xa412feb4 /* Word access */
45 45
46#else 46#else
47#define TMU_TSTR 0xfffffe92 /* Byte access */ 47#define TMU_012_TSTR 0xfffffe92 /* Byte access */
48 48
49#define TMU0_TCOR 0xfffffe94 /* Long access */ 49#define TMU0_TCOR 0xfffffe94 /* Long access */
50#define TMU0_TCNT 0xfffffe98 /* Long access */ 50#define TMU0_TCNT 0xfffffe98 /* Long access */
diff --git a/include/asm-sh/cpu-sh4/freq.h b/include/asm-sh/cpu-sh4/freq.h
index 39f41fcd509d..026025b51cea 100644
--- a/include/asm-sh/cpu-sh4/freq.h
+++ b/include/asm-sh/cpu-sh4/freq.h
@@ -22,6 +22,8 @@
22#define FRQCR0 0xffc80000 22#define FRQCR0 0xffc80000
23#define FRQCR1 0xffc80004 23#define FRQCR1 0xffc80004
24#define FRQMR1 0xffc80014 24#define FRQMR1 0xffc80014
25#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
26#define FRQCR 0xffc00014
25#else 27#else
26#define FRQCR 0xffc00000 28#define FRQCR 0xffc00000
27#define FRQCR_PSTBY 0x0200 29#define FRQCR_PSTBY 0x0200
diff --git a/include/asm-sh/cpu-sh4/timer.h b/include/asm-sh/cpu-sh4/timer.h
index 8a4af126c890..d1e796b96888 100644
--- a/include/asm-sh/cpu-sh4/timer.h
+++ b/include/asm-sh/cpu-sh4/timer.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * include/asm-sh/cpu-sh4/timer.h 2 * include/asm-sh/cpu-sh4/timer.h
3 * 3 *
4 * Copyright (C) 2004 Lineo Solutions, Inc. 4 * Copyright (C) 2004 Lineo Solutions, Inc.
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
@@ -16,36 +16,45 @@
16 * SH7750S/SH7750R 16 * SH7750S/SH7750R
17 * SH7751/SH7751R 17 * SH7751/SH7751R
18 * SH7760 18 * SH7760
19 * SH-X3
19 * --------------------------------------------------------------------------- 20 * ---------------------------------------------------------------------------
20 */ 21 */
21 22#ifdef CONFIG_CPU_SUBTYPE_SHX3
22#if !defined(CONFIG_CPU_SUBTYPE_SH7760) 23#define TMU_012_BASE 0xffc10000
23#define TMU_TOCR 0xffd80000 /* Byte access */ 24#define TMU_345_BASE 0xffc20000
25#else
26#define TMU_012_BASE 0xffd80000
27#define TMU_345_BASE 0xfe100000
24#endif 28#endif
25#define TMU_TSTR 0xffd80004 /* Byte access */
26 29
27#define TMU0_TCOR 0xffd80008 /* Long access */ 30#define TMU_TOCR TMU_012_BASE /* Not supported on all CPUs */
28#define TMU0_TCNT 0xffd8000c /* Long access */
29#define TMU0_TCR 0xffd80010 /* Word access */
30 31
31#define TMU1_TCOR 0xffd80014 /* Long access */ 32#define TMU_012_TSTR (TMU_012_BASE + 0x04)
32#define TMU1_TCNT 0xffd80018 /* Long access */ 33#define TMU_345_TSTR (TMU_345_BASE + 0x04)
33#define TMU1_TCR 0xffd8001c /* Word access */
34 34
35#define TMU2_TCOR 0xffd80020 /* Long access */ 35#define TMU0_TCOR (TMU_012_BASE + 0x08)
36#define TMU2_TCNT 0xffd80024 /* Long access */ 36#define TMU0_TCNT (TMU_012_BASE + 0x0c)
37#define TMU2_TCR 0xffd80028 /* Word access */ 37#define TMU0_TCR (TMU_012_BASE + 0x10)
38#define TMU2_TCPR 0xffd8002c /* Long access */
39 38
40#if !defined(CONFIG_CPU_SUBTYPE_SH7760) 39#define TMU1_TCOR (TMU_012_BASE + 0x14)
41#define TMU3_TCOR 0xfe100008 /* Long access */ 40#define TMU1_TCNT (TMU_012_BASE + 0x18)
42#define TMU3_TCNT 0xfe10000c /* Long access */ 41#define TMU1_TCR (TMU_012_BASE + 0x1c)
43#define TMU3_TCR 0xfe100010 /* Word access */
44 42
45#define TMU4_TCOR 0xfe100014 /* Long access */ 43#define TMU2_TCOR (TMU_012_BASE + 0x20)
46#define TMU4_TCNT 0xfe100018 /* Long access */ 44#define TMU2_TCNT (TMU_012_BASE + 0x24)
47#define TMU4_TCR 0xfe10001c /* Word access */ 45#define TMU2_TCR (TMU_012_BASE + 0x28)
48#endif 46#define TMU2_TCPR (TMU_012_BASE + 0x2c)
49 47
50#endif /* __ASM_CPU_SH4_TIMER_H */ 48#define TMU3_TCOR (TMU_345_BASE + 0x08)
49#define TMU3_TCNT (TMU_345_BASE + 0x0c)
50#define TMU3_TCR (TMU_345_BASE + 0x10)
51 51
52#define TMU4_TCOR (TMU_345_BASE + 0x14)
53#define TMU4_TCNT (TMU_345_BASE + 0x18)
54#define TMU4_TCR (TMU_345_BASE + 0x1c)
55
56#define TMU5_TCOR (TMU_345_BASE + 0x20)
57#define TMU5_TCNT (TMU_345_BASE + 0x24)
58#define TMU5_TCR (TMU_345_BASE + 0x28)
59
60#endif /* __ASM_CPU_SH4_TIMER_H */
diff --git a/include/asm-sh/futex-irq.h b/include/asm-sh/futex-irq.h
new file mode 100644
index 000000000000..a9f16a7f9aea
--- /dev/null
+++ b/include/asm-sh/futex-irq.h
@@ -0,0 +1,111 @@
1#ifndef __ASM_SH_FUTEX_IRQ_H
2#define __ASM_SH_FUTEX_IRQ_H
3
4#include <asm/system.h>
5
6static inline int atomic_futex_op_xchg_set(int oparg, int __user *uaddr,
7 int *oldval)
8{
9 unsigned long flags;
10 int ret;
11
12 local_irq_save(flags);
13
14 ret = get_user(*oldval, uaddr);
15 if (!ret)
16 ret = put_user(oparg, uaddr);
17
18 local_irq_restore(flags);
19
20 return ret;
21}
22
23static inline int atomic_futex_op_xchg_add(int oparg, int __user *uaddr,
24 int *oldval)
25{
26 unsigned long flags;
27 int ret;
28
29 local_irq_save(flags);
30
31 ret = get_user(*oldval, uaddr);
32 if (!ret)
33 ret = put_user(*oldval + oparg, uaddr);
34
35 local_irq_restore(flags);
36
37 return ret;
38}
39
40static inline int atomic_futex_op_xchg_or(int oparg, int __user *uaddr,
41 int *oldval)
42{
43 unsigned long flags;
44 int ret;
45
46 local_irq_save(flags);
47
48 ret = get_user(*oldval, uaddr);
49 if (!ret)
50 ret = put_user(*oldval | oparg, uaddr);
51
52 local_irq_restore(flags);
53
54 return ret;
55}
56
57static inline int atomic_futex_op_xchg_and(int oparg, int __user *uaddr,
58 int *oldval)
59{
60 unsigned long flags;
61 int ret;
62
63 local_irq_save(flags);
64
65 ret = get_user(*oldval, uaddr);
66 if (!ret)
67 ret = put_user(*oldval & oparg, uaddr);
68
69 local_irq_restore(flags);
70
71 return ret;
72}
73
74static inline int atomic_futex_op_xchg_xor(int oparg, int __user *uaddr,
75 int *oldval)
76{
77 unsigned long flags;
78 int ret;
79
80 local_irq_save(flags);
81
82 ret = get_user(*oldval, uaddr);
83 if (!ret)
84 ret = put_user(*oldval ^ oparg, uaddr);
85
86 local_irq_restore(flags);
87
88 return ret;
89}
90
91static inline int atomic_futex_op_cmpxchg_inatomic(int __user *uaddr,
92 int oldval, int newval)
93{
94 unsigned long flags;
95 int ret, prev = 0;
96
97 local_irq_save(flags);
98
99 ret = get_user(prev, uaddr);
100 if (!ret && oldval == prev)
101 ret = put_user(newval, uaddr);
102
103 local_irq_restore(flags);
104
105 if (ret)
106 return ret;
107
108 return prev;
109}
110
111#endif /* __ASM_SH_FUTEX_IRQ_H */
diff --git a/include/asm-sh/futex.h b/include/asm-sh/futex.h
index 6a332a9f099c..74ed3681d33c 100644
--- a/include/asm-sh/futex.h
+++ b/include/asm-sh/futex.h
@@ -1,6 +1,77 @@
1#ifndef _ASM_FUTEX_H 1#ifndef __ASM_SH_FUTEX_H
2#define _ASM_FUTEX_H 2#define __ASM_SH_FUTEX_H
3 3
4#include <asm-generic/futex.h> 4#ifdef __KERNEL__
5 5
6#endif 6#include <linux/futex.h>
7#include <asm/errno.h>
8#include <asm/uaccess.h>
9
10/* XXX: UP variants, fix for SH-4A and SMP.. */
11#include <asm/futex-irq.h>
12
13static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
14{
15 int op = (encoded_op >> 28) & 7;
16 int cmp = (encoded_op >> 24) & 15;
17 int oparg = (encoded_op << 8) >> 20;
18 int cmparg = (encoded_op << 20) >> 20;
19 int oldval = 0, ret;
20
21 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
22 oparg = 1 << oparg;
23
24 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
25 return -EFAULT;
26
27 pagefault_disable();
28
29 switch (op) {
30 case FUTEX_OP_SET:
31 ret = atomic_futex_op_xchg_set(oparg, uaddr, &oldval);
32 break;
33 case FUTEX_OP_ADD:
34 ret = atomic_futex_op_xchg_add(oparg, uaddr, &oldval);
35 break;
36 case FUTEX_OP_OR:
37 ret = atomic_futex_op_xchg_or(oparg, uaddr, &oldval);
38 break;
39 case FUTEX_OP_ANDN:
40 ret = atomic_futex_op_xchg_and(~oparg, uaddr, &oldval);
41 break;
42 case FUTEX_OP_XOR:
43 ret = atomic_futex_op_xchg_xor(oparg, uaddr, &oldval);
44 break;
45 default:
46 ret = -ENOSYS;
47 break;
48 }
49
50 pagefault_enable();
51
52 if (!ret) {
53 switch (cmp) {
54 case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
55 case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
56 case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
57 case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
58 case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
59 case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
60 default: ret = -ENOSYS;
61 }
62 }
63
64 return ret;
65}
66
67static inline int
68futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
69{
70 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
71 return -EFAULT;
72
73 return atomic_futex_op_cmpxchg_inatomic(uaddr, oldval, newval);
74}
75
76#endif /* __KERNEL__ */
77#endif /* __ASM_SH_FUTEX_H */
diff --git a/include/asm-sh/hd64461.h b/include/asm-sh/hd64461.h
index 27e5c34e2659..4dd8592ca014 100644
--- a/include/asm-sh/hd64461.h
+++ b/include/asm-sh/hd64461.h
@@ -1,200 +1,241 @@
1#ifndef __ASM_SH_HD64461 1#ifndef __ASM_SH_HD64461
2#define __ASM_SH_HD64461 2#define __ASM_SH_HD64461
3/* 3/*
4 * $Id: hd64461.h,v 1.5 2004/03/16 00:07:51 lethal Exp $ 4 * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
5 * Copyright (C) 2004 Paul Mundt
5 * Copyright (C) 2000 YAEGASHI Takeshi 6 * Copyright (C) 2000 YAEGASHI Takeshi
6 * Hitachi HD64461 companion chip support 7 *
8 * Hitachi HD64461 companion chip support
9 * (please note manual reference 0x10000000 = 0xb0000000)
7 */ 10 */
8 11
9/* Constants for PCMCIA mappings */ 12/* Constants for PCMCIA mappings */
10#define HD64461_PCC_WINDOW 0x01000000 13#define HD64461_PCC_WINDOW 0x01000000
11 14
12#define HD64461_PCC0_BASE 0xb8000000 /* area 6 */ 15/* Area 6 - Slot 0 - memory and/or IO card */
13#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) 16#define HD64461_PCC0_BASE (CONFIG_HD64461_IOBASE + 0x8000000)
14#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) 17#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */
15#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) 18#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */
16 19#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */
17#define HD64461_PCC1_BASE 0xb4000000 /* area 5 */ 20
18#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) 21/* Area 5 - Slot 1 - memory card only */
19#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) 22#define HD64461_PCC1_BASE (CONFIG_HD64461_IOBASE + 0x4000000)
20 23#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */
21#define HD64461_STBCR 0x10000 24#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */
22#define HD64461_STBCR_CKIO_STBY 0x2000 25
23#define HD64461_STBCR_SAFECKE_IST 0x1000 26/* Standby Control Register for HD64461 */
24#define HD64461_STBCR_SLCKE_IST 0x0800 27#define HD64461_STBCR CONFIG_HD64461_IOBASE
25#define HD64461_STBCR_SAFECKE_OST 0x0400 28#define HD64461_STBCR_CKIO_STBY 0x2000
26#define HD64461_STBCR_SLCKE_OST 0x0200 29#define HD64461_STBCR_SAFECKE_IST 0x1000
27#define HD64461_STBCR_SMIAST 0x0100 30#define HD64461_STBCR_SLCKE_IST 0x0800
28#define HD64461_STBCR_SLCDST 0x0080 31#define HD64461_STBCR_SAFECKE_OST 0x0400
29#define HD64461_STBCR_SPC0ST 0x0040 32#define HD64461_STBCR_SLCKE_OST 0x0200
30#define HD64461_STBCR_SPC1ST 0x0020 33#define HD64461_STBCR_SMIAST 0x0100
31#define HD64461_STBCR_SAFEST 0x0010 34#define HD64461_STBCR_SLCDST 0x0080
32#define HD64461_STBCR_STM0ST 0x0008 35#define HD64461_STBCR_SPC0ST 0x0040
33#define HD64461_STBCR_STM1ST 0x0004 36#define HD64461_STBCR_SPC1ST 0x0020
34#define HD64461_STBCR_SIRST 0x0002 37#define HD64461_STBCR_SAFEST 0x0010
35#define HD64461_STBCR_SURTST 0x0001 38#define HD64461_STBCR_STM0ST 0x0008
36 39#define HD64461_STBCR_STM1ST 0x0004
37#define HD64461_SYSCR 0x10002 40#define HD64461_STBCR_SIRST 0x0002
38#define HD64461_SCPUCR 0x10004 41#define HD64461_STBCR_SURTST 0x0001
39 42
40#define HD64461_LCDCBAR 0x11000 43/* System Configuration Register */
41#define HD64461_LCDCLOR 0x11002 44#define HD64461_SYSCR (CONFIG_HD64461_IOBASE + 0x02)
42#define HD64461_LCDCCR 0x11004 45
43#define HD64461_LCDCCR_STBACK 0x0400 46/* CPU Data Bus Control Register */
44#define HD64461_LCDCCR_STREQ 0x0100 47#define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x04)
45#define HD64461_LCDCCR_MOFF 0x0080 48
46#define HD64461_LCDCCR_REFSEL 0x0040 49/* Base Adress Register */
47#define HD64461_LCDCCR_EPON 0x0020 50#define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x1000)
48#define HD64461_LCDCCR_SPON 0x0010 51
49 52/* Line increment adress */
50#define HD64461_LDR1 0x11010 53#define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x1002)
51#define HD64461_LDR1_DON 0x01 54
52#define HD64461_LDR1_DINV 0x80 55/* Controls LCD controller */
53 56#define HD64461_LCDCCR (CONFIG_HD64461_IOBASE + 0x1004)
54#define HD64461_LDR2 0x11012 57
55#define HD64461_LDHNCR 0x11014 58/* LCCDR control bits */
56#define HD64461_LDHNSR 0x11016 59#define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */
57#define HD64461_LDVNTR 0x11018 60#define HD64461_LCDCCR_STREQ 0x0100 /* Standby Request */
58#define HD64461_LDVNDR 0x1101a 61#define HD64461_LCDCCR_MOFF 0x0080 /* Memory Off */
59#define HD64461_LDVSPR 0x1101c 62#define HD64461_LCDCCR_REFSEL 0x0040 /* Refresh Select */
60#define HD64461_LDR3 0x1101e 63#define HD64461_LCDCCR_EPON 0x0020 /* End Power On */
61 64#define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */
62#define HD64461_CPTWAR 0x11030 65
63#define HD64461_CPTWDR 0x11032 66/* Controls LCD (1) */
64#define HD64461_CPTRAR 0x11034 67#define HD64461_LDR1 (CONFIG_HD64461_IOBASE + 0x1010)
65#define HD64461_CPTRDR 0x11036 68#define HD64461_LDR1_DON 0x01 /* Display On */
66 69#define HD64461_LDR1_DINV 0x80 /* Display Invert */
67#define HD64461_GRDOR 0x11040 70
68#define HD64461_GRSCR 0x11042 71/* Controls LCD (2) */
69#define HD64461_GRCFGR 0x11044 72#define HD64461_LDR2 (CONFIG_HD64461_IOBASE + 0x1012)
70#define HD64461_GRCFGR_ACCSTATUS 0x10 73#define HD64461_LDHNCR (CONFIG_HD64461_IOBASE + 0x1014) /* Number of horizontal characters */
71#define HD64461_GRCFGR_ACCRESET 0x08 74#define HD64461_LDHNSR (CONFIG_HD64461_IOBASE + 0x1016) /* Specify output start position + width of CL1 */
72#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 75#define HD64461_LDVNTR (CONFIG_HD64461_IOBASE + 0x1018) /* Specify total vertical lines */
73#define HD64461_GRCFGR_ACCSTART_LINE 0x04 76#define HD64461_LDVNDR (CONFIG_HD64461_IOBASE + 0x101a) /* specify number of display vertical lines */
74#define HD64461_GRCFGR_COLORDEPTH16 0x01 77#define HD64461_LDVSPR (CONFIG_HD64461_IOBASE + 0x101c) /* specify vertical synchronization pos and AC nr */
75 78
76#define HD64461_LNSARH 0x11046 79/* Controls LCD (3) */
77#define HD64461_LNSARL 0x11048 80#define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x101e)
78#define HD64461_LNAXLR 0x1104a 81
79#define HD64461_LNDGR 0x1104c 82/* Palette Registers */
80#define HD64461_LNAXR 0x1104e 83#define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x1030) /* Color Palette Write Adress Register */
81#define HD64461_LNERTR 0x11050 84#define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x1032) /* Color Palette Write Data Register */
82#define HD64461_LNMDR 0x11052 85#define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x1034) /* Color Palette Read Adress Register */
83#define HD64461_BBTSSARH 0x11054 86#define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x1036) /* Color Palette Read Data Register */
84#define HD64461_BBTSSARL 0x11056 87
85#define HD64461_BBTDSARH 0x11058 88#define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x1040) /* Display Resolution Offset Register */
86#define HD64461_BBTDSARL 0x1105a 89#define HD64461_GRSCR (CONFIG_HD64461_IOBASE + 0x1042) /* Solid Color Register */
87#define HD64461_BBTDWR 0x1105c 90#define HD64461_GRCFGR (CONFIG_HD64461_IOBASE + 0x1044) /* Accelerator Configuration Register */
88#define HD64461_BBTDHR 0x1105e 91
89#define HD64461_BBTPARH 0x11060 92#define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */
90#define HD64461_BBTPARL 0x11062 93#define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */
91#define HD64461_BBTMARH 0x11064 94#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 /* Accelerator Start BITBLT */
92#define HD64461_BBTMARL 0x11066 95#define HD64461_GRCFGR_ACCSTART_LINE 0x04 /* Accelerator Start Line Drawing */
93#define HD64461_BBTROPR 0x11068 96#define HD64461_GRCFGR_COLORDEPTH16 0x01 /* Sets Colordepth 16 for Accelerator */
94#define HD64461_BBTMDR 0x1106a 97#define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */
98
99/* Line Drawing Registers */
100#define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x1046) /* Line Start Adress Register (H) */
101#define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x1048) /* Line Start Adress Register (L) */
102#define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x104a) /* Axis Pixel Length Register */
103#define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x104c) /* Diagonal Register */
104#define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x104e) /* Axial Register */
105#define HD64461_LNERTR (CONFIG_HD64461_IOBASE + 0x1050) /* Start Error Term Register */
106#define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x1052) /* Line Mode Register */
107
108/* BitBLT Registers */
109#define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x1054) /* Source Start Adress Register (H) */
110#define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x1056) /* Source Start Adress Register (L) */
111#define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x1058) /* Destination Start Adress Register (H) */
112#define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x105a) /* Destination Start Adress Register (L) */
113#define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x105c) /* Destination Block Width Register */
114#define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x105e) /* Destination Block Height Register */
115#define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x1060) /* Pattern Start Adress Register (H) */
116#define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x1062) /* Pattern Start Adress Register (L) */
117#define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x1064) /* Mask Start Adress Register (H) */
118#define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x1066) /* Mask Start Adress Register (L) */
119#define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x1068) /* ROP Register */
120#define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x106a) /* BitBLT Mode Register */
95 121
96/* PC Card Controller Registers */ 122/* PC Card Controller Registers */
97#define HD64461_PCC0ISR 0x12000 /* socket 0 interface status */ 123/* Maps to Physical Area 6 */
98#define HD64461_PCC0GCR 0x12002 /* socket 0 general control */ 124#define HD64461_PCC0ISR (CONFIG_HD64461_IOBASE + 0x2000) /* socket 0 interface status */
99#define HD64461_PCC0CSCR 0x12004 /* socket 0 card status change */ 125#define HD64461_PCC0GCR (CONFIG_HD64461_IOBASE + 0x2002) /* socket 0 general control */
100#define HD64461_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */ 126#define HD64461_PCC0CSCR (CONFIG_HD64461_IOBASE + 0x2004) /* socket 0 card status change */
101#define HD64461_PCC0SCR 0x12008 /* socket 0 software control */ 127#define HD64461_PCC0CSCIER (CONFIG_HD64461_IOBASE + 0x2006) /* socket 0 card status change interrupt enable */
102#define HD64461_PCC1ISR 0x12010 /* socket 1 interface status */ 128#define HD64461_PCC0SCR (CONFIG_HD64461_IOBASE + 0x2008) /* socket 0 software control */
103#define HD64461_PCC1GCR 0x12012 /* socket 1 general control */ 129/* Maps to Physical Area 5 */
104#define HD64461_PCC1CSCR 0x12014 /* socket 1 card status change */ 130#define HD64461_PCC1ISR (CONFIG_HD64461_IOBASE + 0x2010) /* socket 1 interface status */
105#define HD64461_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */ 131#define HD64461_PCC1GCR (CONFIG_HD64461_IOBASE + 0x2012) /* socket 1 general control */
106#define HD64461_PCC1SCR 0x12018 /* socket 1 software control */ 132#define HD64461_PCC1CSCR (CONFIG_HD64461_IOBASE + 0x2014) /* socket 1 card status change */
133#define HD64461_PCC1CSCIER (CONFIG_HD64461_IOBASE + 0x2016) /* socket 1 card status change interrupt enable */
134#define HD64461_PCC1SCR (CONFIG_HD64461_IOBASE + 0x2018) /* socket 1 software control */
107 135
108/* PCC Interface Status Register */ 136/* PCC Interface Status Register */
109#define HD64461_PCCISR_READY 0x80 /* card ready */ 137#define HD64461_PCCISR_READY 0x80 /* card ready */
110#define HD64461_PCCISR_MWP 0x40 /* card write-protected */ 138#define HD64461_PCCISR_MWP 0x40 /* card write-protected */
111#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */ 139#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */
112#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */ 140#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */
113#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */ 141#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */
114#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */ 142#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */
115#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */ 143#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */
116#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */ 144#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */
117 145
118#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */ 146#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */
119#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */ 147#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */
120#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */ 148#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */
121#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */ 149#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */
122#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */ 150#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */
123#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */ 151#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */
124 152
125/* PCC General Control Register */ 153/* PCC General Control Register */
126#define HD64461_PCCGCR_DRVE 0x80 /* output drive */ 154#define HD64461_PCCGCR_DRVE 0x80 /* output drive */
127#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */ 155#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */
128#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ 156#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */
129#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */ 157#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */
130#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */ 158#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */
131#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */ 159#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */
132#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */ 160#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */
133#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */ 161#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */
134 162
135/* PCC Card Status Change Register */ 163/* PCC Card Status Change Register */
136#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */ 164#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */
137#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */ 165#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */
138#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */ 166#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */
139#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */ 167#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */
140#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */ 168#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */
141#define HD64461_PCCCSCR_RC 0x04 /* READY change */ 169#define HD64461_PCCCSCR_RC 0x04 /* READY change */
142#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */ 170#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */
143#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */ 171#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */
144 172
145/* PCC Card Status Change Interrupt Enable Register */ 173/* PCC Card Status Change Interrupt Enable Register */
146#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */ 174#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */
147#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */ 175#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */
148#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */ 176#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */
149#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */ 177#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */
150#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */ 178#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */
151#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */ 179#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */
152 180
153#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */ 181#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */
154#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */ 182#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */
155#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */ 183#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */
156#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */ 184#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */
157#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/ 185#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/
158 186
159/* PCC Software Control Register */ 187/* PCC Software Control Register */
160#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */ 188#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */
161#define HD64461_PCCSCR_SWP 0x01 /* write protect */ 189#define HD64461_PCCSCR_SWP 0x01 /* write protect */
162 190
163#define HD64461_P0OCR 0x1202a 191/* PCC0 Output Pins Control Register */
164#define HD64461_P1OCR 0x1202c 192#define HD64461_P0OCR (CONFIG_HD64461_IOBASE + 0x202a)
165#define HD64461_PGCR 0x1202e 193
166 194/* PCC1 Output Pins Control Register */
167#define HD64461_GPACR 0x14000 195#define HD64461_P1OCR (CONFIG_HD64461_IOBASE + 0x202c)
168#define HD64461_GPBCR 0x14002 196
169#define HD64461_GPCCR 0x14004 197/* PC Card General Control Register */
170#define HD64461_GPDCR 0x14006 198#define HD64461_PGCR (CONFIG_HD64461_IOBASE + 0x202e)
171#define HD64461_GPADR 0x14010 199
172#define HD64461_GPBDR 0x14012 200/* Port Control Registers */
173#define HD64461_GPCDR 0x14014 201#define HD64461_GPACR (CONFIG_HD64461_IOBASE + 0x4000) /* Port A - Handles IRDA/TIMER */
174#define HD64461_GPDDR 0x14016 202#define HD64461_GPBCR (CONFIG_HD64461_IOBASE + 0x4002) /* Port B - Handles UART */
175#define HD64461_GPAICR 0x14020 203#define HD64461_GPCCR (CONFIG_HD64461_IOBASE + 0x4004) /* Port C - Handles PCMCIA 1 */
176#define HD64461_GPBICR 0x14022 204#define HD64461_GPDCR (CONFIG_HD64461_IOBASE + 0x4006) /* Port D - Handles PCMCIA 1 */
177#define HD64461_GPCICR 0x14024 205
178#define HD64461_GPDICR 0x14026 206/* Port Control Data Registers */
179#define HD64461_GPAISR 0x14040 207#define HD64461_GPADR (CONFIG_HD64461_IOBASE + 0x4010) /* A */
180#define HD64461_GPBISR 0x14042 208#define HD64461_GPBDR (CONFIG_HD64461_IOBASE + 0x4012) /* B */
181#define HD64461_GPCISR 0x14044 209#define HD64461_GPCDR (CONFIG_HD64461_IOBASE + 0x4014) /* C */
182#define HD64461_GPDISR 0x14046 210#define HD64461_GPDDR (CONFIG_HD64461_IOBASE + 0x4016) /* D */
183 211
184#define HD64461_NIRR 0x15000 212/* Interrupt Control Registers */
185#define HD64461_NIMR 0x15002 213#define HD64461_GPAICR (CONFIG_HD64461_IOBASE + 0x4020) /* A */
186 214#define HD64461_GPBICR (CONFIG_HD64461_IOBASE + 0x4022) /* B */
187#define HD64461_IRQBASE OFFCHIP_IRQ_BASE 215#define HD64461_GPCICR (CONFIG_HD64461_IOBASE + 0x4024) /* C */
188#define HD64461_IRQ_NUM 16 216#define HD64461_GPDICR (CONFIG_HD64461_IOBASE + 0x4026) /* D */
189 217
190#define HD64461_IRQ_UART (HD64461_IRQBASE+5) 218/* Interrupt Status Registers */
191#define HD64461_IRQ_IRDA (HD64461_IRQBASE+6) 219#define HD64461_GPAISR (CONFIG_HD64461_IOBASE + 0x4040) /* A */
192#define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9) 220#define HD64461_GPBISR (CONFIG_HD64461_IOBASE + 0x4042) /* B */
193#define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10) 221#define HD64461_GPCISR (CONFIG_HD64461_IOBASE + 0x4044) /* C */
194#define HD64461_IRQ_GPIO (HD64461_IRQBASE+11) 222#define HD64461_GPDISR (CONFIG_HD64461_IOBASE + 0x4046) /* D */
195#define HD64461_IRQ_AFE (HD64461_IRQBASE+12) 223
196#define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13) 224/* Interrupt Request Register & Interrupt Mask Register */
197#define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14) 225#define HD64461_NIRR (CONFIG_HD64461_IOBASE + 0x5000)
226#define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x5002)
227
228#define HD64461_IRQBASE OFFCHIP_IRQ_BASE
229#define HD64461_IRQ_NUM 16
230
231#define HD64461_IRQ_UART (HD64461_IRQBASE+5)
232#define HD64461_IRQ_IRDA (HD64461_IRQBASE+6)
233#define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9)
234#define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10)
235#define HD64461_IRQ_GPIO (HD64461_IRQBASE+11)
236#define HD64461_IRQ_AFE (HD64461_IRQBASE+12)
237#define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13)
238#define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14)
198 239
199#define __IO_PREFIX hd64461 240#define __IO_PREFIX hd64461
200#include <asm/io_generic.h> 241#include <asm/io_generic.h>
diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index 80ee1cda7498..4ca3f765bacc 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -5,4 +5,46 @@
5 5
6extern atomic_t irq_err_count; 6extern atomic_t irq_err_count;
7 7
8struct intc2_data {
9 unsigned short irq;
10 unsigned char ipr_offset, ipr_shift;
11 unsigned char msk_offset, msk_shift;
12 unsigned char priority;
13};
14
15struct intc2_desc {
16 unsigned long prio_base;
17 unsigned long msk_base;
18 unsigned long mskclr_base;
19 struct intc2_data *intc2_data;
20 unsigned int nr_irqs;
21 struct irq_chip chip;
22};
23
24void register_intc2_controller(struct intc2_desc *);
25void init_IRQ_intc2(void);
26
27struct ipr_data {
28 unsigned char irq;
29 unsigned char ipr_idx; /* Index for the IPR registered */
30 unsigned char shift; /* Number of bits to shift the data */
31 unsigned char priority; /* The priority */
32};
33
34struct ipr_desc {
35 unsigned long *ipr_offsets;
36 unsigned int nr_offsets;
37 struct ipr_data *ipr_data;
38 unsigned int nr_irqs;
39 struct irq_chip chip;
40};
41
42void register_ipr_controller(struct ipr_desc *);
43void init_IRQ_ipr(void);
44
45/*
46 * Enable individual interrupt mode for external IPR IRQs.
47 */
48void ipr_irq_enable_irlm(void);
49
8#endif /* __ASM_SH_HW_IRQ_H */ 50#endif /* __ASM_SH_HW_IRQ_H */
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index e81bf21c801e..c61d902b8bff 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -31,47 +31,7 @@ extern unsigned short *irq_mask_register;
31 * PINT IRQs 31 * PINT IRQs
32 */ 32 */
33void init_IRQ_pint(void); 33void init_IRQ_pint(void);
34
35/*
36 * The shift value is now the number of bits to shift, not the number of
37 * bits/4. This is to make it easier to read the value directly from the
38 * datasheets. The IPR address, addr, will be set from ipr_idx via the
39 * map_ipridx_to_addr function.
40 */
41struct ipr_data {
42 unsigned int irq;
43 int ipr_idx; /* Index for the IPR registered */
44 int shift; /* Number of bits to shift the data */
45 int priority; /* The priority */
46 unsigned int addr; /* Address of Interrupt Priority Register */
47};
48
49/*
50 * Given an IPR IDX, map the value to an IPR register address.
51 */
52unsigned int map_ipridx_to_addr(int idx);
53
54/*
55 * Enable individual interrupt mode for external IPR IRQs.
56 */
57void ipr_irq_enable_irlm(void);
58
59/*
60 * Function for "on chip support modules".
61 */
62void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
63void make_imask_irq(unsigned int irq); 34void make_imask_irq(unsigned int irq);
64void init_IRQ_ipr(void);
65
66struct intc2_data {
67 unsigned short irq;
68 unsigned char ipr_offset, ipr_shift;
69 unsigned char msk_offset, msk_shift;
70 unsigned char priority;
71};
72
73void make_intc2_irq(struct intc2_data *, unsigned int nr_irqs);
74void init_IRQ_intc2(void);
75 35
76static inline int generic_irq_demux(int irq) 36static inline int generic_irq_demux(int irq)
77{ 37{
diff --git a/include/asm-sh/machvec.h b/include/asm-sh/machvec.h
index 70389b72ffef..088698bacf2f 100644
--- a/include/asm-sh/machvec.h
+++ b/include/asm-sh/machvec.h
@@ -13,7 +13,6 @@
13#include <linux/types.h> 13#include <linux/types.h>
14#include <linux/time.h> 14#include <linux/time.h>
15#include <asm/machtypes.h> 15#include <asm/machtypes.h>
16#include <asm/machvec_init.h>
17 16
18struct device; 17struct device;
19 18
@@ -68,4 +67,7 @@ extern struct sh_machine_vector sh_mv;
68 67
69#define get_system_type() sh_mv.mv_name 68#define get_system_type() sh_mv.mv_name
70 69
70#define __initmv \
71 __attribute_used__ __attribute__((__section__ (".machvec.init")))
72
71#endif /* _ASM_SH_MACHVEC_H */ 73#endif /* _ASM_SH_MACHVEC_H */
diff --git a/include/asm-sh/machvec_init.h b/include/asm-sh/machvec_init.h
deleted file mode 100644
index e397798ebd94..000000000000
--- a/include/asm-sh/machvec_init.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * include/asm-sh/machvec_init.h
3 *
4 * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * This file has goodies to help simplify instantiation of machine vectors.
10 */
11
12#ifndef __SH_MACHVEC_INIT_H
13#define __SH_MACHVEC_INIT_H
14
15
16/*
17 * In a GENERIC kernel, we have lots of these vectors floating about,
18 * all but one of which we want to go away. In a non-GENERIC kernel,
19 * we want only one, ever.
20 *
21 * Accomplish this in the GENERIC kernel by puting all of the vectors
22 * in the .init.data section where they'll go away. We'll copy the
23 * one we want to the real alpha_mv vector in setup_arch.
24 *
25 * Accomplish this in a non-GENERIC kernel by ifdef'ing out all but
26 * one of the vectors, which will not reside in .init.data. We then
27 * alias this one vector to alpha_mv, so no copy is needed.
28 *
29 * Upshot: set __initdata to nothing for non-GENERIC kernels.
30 *
31 * Note we do the same thing for the UNKNOWN kernel, as we need to write
32 * to the machine vector while setting it up.
33 */
34
35#if defined(CONFIG_SH_GENERIC) || defined(CONFIG_SH_UNKNOWN)
36#define __initmv __attribute__((unused,__section__ (".machvec.init")))
37#define ALIAS_MV(x)
38#else
39#define __initmv
40
41/* GCC actually has a syntax for defining aliases, but is under some
42 delusion that you shouldn't be able to declare it extern somewhere
43 else beforehand. Fine. We'll do it ourselves. */
44#if 0
45#define ALIAS_MV(system) \
46 struct sh_machine_vector sh_mv __attribute__((alias("mv_"#system)));
47#else
48#define ALIAS_MV(system) \
49 asm(".global sh_mv\nsh_mv = mv_"#system );
50#endif
51#endif /* GENERIC */
52
53#endif /* __SH_MACHVEC_INIT_H */
diff --git a/include/asm-sh/mmzone.h b/include/asm-sh/mmzone.h
new file mode 100644
index 000000000000..7969f381dff2
--- /dev/null
+++ b/include/asm-sh/mmzone.h
@@ -0,0 +1,46 @@
1#ifndef __ASM_SH_MMZONE_H
2#define __ASM_SH_MMZONE_H
3
4#ifdef __KERNEL__
5
6#ifdef CONFIG_NEED_MULTIPLE_NODES
7extern struct pglist_data *node_data[];
8#define NODE_DATA(nid) (node_data[nid])
9
10#define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn)
11#define node_end_pfn(nid) (NODE_DATA(nid)->node_start_pfn + \
12 NODE_DATA(nid)->node_spanned_pages)
13
14static inline int pfn_to_nid(unsigned long pfn)
15{
16 int nid;
17
18 for (nid = 0; nid < MAX_NUMNODES; nid++)
19 if (pfn >= node_start_pfn(nid) && pfn <= node_end_pfn(nid))
20 break;
21
22 return nid;
23}
24
25static inline struct pglist_data *pfn_to_pgdat(unsigned long pfn)
26{
27 return NODE_DATA(pfn_to_nid(pfn));
28}
29
30/* arch/sh/mm/numa.c */
31void __init setup_bootmem_node(int nid, unsigned long start, unsigned long end);
32#else
33static inline void
34setup_bootmem_node(int nid, unsigned long start, unsigned long end)
35{
36}
37#endif /* CONFIG_NEED_MULTIPLE_NODES */
38
39/* Platform specific mem init */
40void __init plat_mem_setup(void);
41
42/* arch/sh/kernel/setup.c */
43void __init setup_bootmem_allocator(unsigned long start_pfn);
44
45#endif /* __KERNEL__ */
46#endif /* __ASM_SH_MMZONE_H */
diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h
index 7464de4ba07d..6bc9bba10105 100644
--- a/include/asm-sh/page.h
+++ b/include/asm-sh/page.h
@@ -60,6 +60,7 @@ extern void (*copy_page)(void *to, void *from);
60 60
61extern unsigned long shm_align_mask; 61extern unsigned long shm_align_mask;
62extern unsigned long max_low_pfn, min_low_pfn; 62extern unsigned long max_low_pfn, min_low_pfn;
63extern unsigned long memory_start, memory_end;
63 64
64#ifdef CONFIG_MMU 65#ifdef CONFIG_MMU
65extern void clear_page_slow(void *to); 66extern void clear_page_slow(void *to);
@@ -134,7 +135,9 @@ typedef struct { unsigned long pgd; } pgd_t;
134#define PFN_START (__MEMORY_START >> PAGE_SHIFT) 135#define PFN_START (__MEMORY_START >> PAGE_SHIFT)
135#define ARCH_PFN_OFFSET (PFN_START) 136#define ARCH_PFN_OFFSET (PFN_START)
136#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) 137#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
138#ifdef CONFIG_FLATMEM
137#define pfn_valid(pfn) ((pfn) >= min_low_pfn && (pfn) < max_low_pfn) 139#define pfn_valid(pfn) ((pfn) >= min_low_pfn && (pfn) < max_low_pfn)
140#endif
138#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) 141#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
139 142
140#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ 143#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
@@ -148,5 +151,12 @@ typedef struct { unsigned long pgd; } pgd_t;
148#define __HAVE_ARCH_GATE_AREA 151#define __HAVE_ARCH_GATE_AREA
149#endif 152#endif
150 153
154/*
155 * Slub defaults to 8-byte alignment, we're only interested in 4.
156 * Slab defaults to BYTES_PER_WORD, which ends up being the same anyways.
157 */
158#define ARCH_KMALLOC_MINALIGN 4
159#define ARCH_SLAB_MINALIGN 4
160
151#endif /* __KERNEL__ */ 161#endif /* __KERNEL__ */
152#endif /* __ASM_SH_PAGE_H */ 162#endif /* __ASM_SH_PAGE_H */
diff --git a/include/asm-sh/parport.h b/include/asm-sh/parport.h
new file mode 100644
index 000000000000..f67ba60a2acd
--- /dev/null
+++ b/include/asm-sh/parport.h
@@ -0,0 +1,16 @@
1/*
2 * Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk>
3 *
4 * This file should only be included by drivers/parport/parport_pc.c.
5 */
6#ifndef __ASM_SH_PARPORT_H
7#define __ASM_SH_PARPORT_H
8
9static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma);
10
11static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma)
12{
13 return parport_pc_find_isa_ports(autoirq, autodma);
14}
15
16#endif /* __ASM_SH_PARPORT_H */
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index d42f68e724fa..2252e75daa26 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -36,7 +36,7 @@
36 */ 36 */
37enum cpu_type { 37enum cpu_type {
38 /* SH-2 types */ 38 /* SH-2 types */
39 CPU_SH7604, CPU_SH7619, 39 CPU_SH7619,
40 40
41 /* SH-2A types */ 41 /* SH-2A types */
42 CPU_SH7206, 42 CPU_SH7206,
@@ -52,7 +52,7 @@ enum cpu_type {
52 CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501, 52 CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501,
53 53
54 /* SH-4A types */ 54 /* SH-4A types */
55 CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, 55 CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3,
56 56
57 /* SH4AL-DSP types */ 57 /* SH4AL-DSP types */
58 CPU_SH73180, CPU_SH7343, CPU_SH7722, 58 CPU_SH73180, CPU_SH7343, CPU_SH7722,
@@ -228,11 +228,7 @@ static __inline__ void grab_fpu(struct pt_regs *regs)
228 regs->sr &= ~SR_FD; 228 regs->sr &= ~SR_FD;
229} 229}
230 230
231#ifdef CONFIG_CPU_SH4
232extern void save_fpu(struct task_struct *__tsk, struct pt_regs *regs); 231extern void save_fpu(struct task_struct *__tsk, struct pt_regs *regs);
233#else
234#define save_fpu(tsk) do { } while (0)
235#endif
236 232
237#define unlazy_fpu(tsk, regs) do { \ 233#define unlazy_fpu(tsk, regs) do { \
238 if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { \ 234 if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { \
diff --git a/include/asm-sh/rwsem.h b/include/asm-sh/rwsem.h
index 4931ba817d73..1987f3ea7f1b 100644
--- a/include/asm-sh/rwsem.h
+++ b/include/asm-sh/rwsem.h
@@ -1,11 +1,15 @@
1/* 1/*
2 * include/asm-ppc/rwsem.h: R/W semaphores for SH using the stuff 2 * include/asm-sh/rwsem.h: R/W semaphores for SH using the stuff
3 * in lib/rwsem.c. 3 * in lib/rwsem.c.
4 */ 4 */
5 5
6#ifndef _ASM_SH_RWSEM_H 6#ifndef _ASM_SH_RWSEM_H
7#define _ASM_SH_RWSEM_H 7#define _ASM_SH_RWSEM_H
8 8
9#ifndef _LINUX_RWSEM_H
10#error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
11#endif
12
9#ifdef __KERNEL__ 13#ifdef __KERNEL__
10#include <linux/list.h> 14#include <linux/list.h>
11#include <linux/spinlock.h> 15#include <linux/spinlock.h>
diff --git a/include/asm-sh/saturn/io.h b/include/asm-sh/saturn/io.h
deleted file mode 100644
index f1b9b5d633f4..000000000000
--- a/include/asm-sh/saturn/io.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * include/asm-sh/saturn/io.h
3 *
4 * I/O functions for use on the Sega Saturn.
5 *
6 * Copyright (C) 2002 Paul Mundt
7 *
8 * Released under the terms of the GNU GPL v2.0.
9 */
10#ifndef __ASM_SH_SATURN_IO_H
11#define __ASM_SH_SATURN_IO_H
12
13/* arch/sh/boards/saturn/io.c */
14extern unsigned long saturn_isa_port2addr(unsigned long offset);
15extern void *saturn_ioremap(unsigned long offset, unsigned long size);
16extern void saturn_iounmap(void *addr);
17
18#endif /* __ASM_SH_SATURN_IO_H */
19
diff --git a/include/asm-sh/saturn/smpc.h b/include/asm-sh/saturn/smpc.h
deleted file mode 100644
index 5de5c12d6347..000000000000
--- a/include/asm-sh/saturn/smpc.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * include/asm-sh/saturn/smpc.h
3 *
4 * System Manager / Peripheral Control definitions.
5 *
6 * Copyright (C) 2002 Paul Mundt
7 *
8 * Released under the terms of the GNU GPL v2.0.
9 */
10#ifndef __ASM_SH_SATURN_SMPC_H
11#define __ASM_SH_SATURN_SMPC_H
12
13#include <asm/io.h>
14
15#define SMPC_COMMAND 0x2010001f /* SMPC command register */
16#define SMPC_RESULT 0x2010005f /* SMPC result register */
17#define SMPC_STATUS 0x20100063 /* SMPC status register */
18
19#define SMPC_CMD_MSHON 0x0001 /* Master SH On */
20#define SMPC_CMD_SSHON 0x0002 /* Slave SH On */
21#define SMPC_CMD_SSHOFF 0x0003 /* Slave SH Off */
22#define SMPC_CMD_SNDON 0x0004 /* Sound On */
23#define SMPC_CMD_SNDOFF 0x0005 /* Sound Off */
24#define SMPC_CMD_CDON 0x0006 /* CD On */
25#define SMPC_CMD_CDOFF 0x0007 /* CD Off */
26
27static inline void smpc_barrier(void)
28{
29 while ((ctrl_inb(SMPC_STATUS) & 0x0001) == 0x0001)
30 ;
31}
32
33#endif /* __ASM_SH_SATURN_SMPC_H */
34
diff --git a/include/asm-sh/sections.h b/include/asm-sh/sections.h
index 57abd708b236..2a696b8ee4f5 100644
--- a/include/asm-sh/sections.h
+++ b/include/asm-sh/sections.h
@@ -3,7 +3,7 @@
3 3
4#include <asm-generic/sections.h> 4#include <asm-generic/sections.h>
5 5
6extern char _end[]; 6extern long __machvec_start, __machvec_end;
7 7
8#endif /* __ASM_SH_SECTIONS_H */ 8#endif /* __ASM_SH_SECTIONS_H */
9 9
diff --git a/include/asm-sh/setup.h b/include/asm-sh/setup.h
index 1583c6b7bdaa..586a9711a75d 100644
--- a/include/asm-sh/setup.h
+++ b/include/asm-sh/setup.h
@@ -6,6 +6,7 @@
6#ifdef __KERNEL__ 6#ifdef __KERNEL__
7 7
8int setup_early_printk(char *); 8int setup_early_printk(char *);
9void sh_mv_setup(void);
9 10
10#endif /* __KERNEL__ */ 11#endif /* __KERNEL__ */
11 12
diff --git a/include/asm-sh/sh03/io.h b/include/asm-sh/sh03/io.h
index df3b187ef883..4ff1eb900301 100644
--- a/include/asm-sh/sh03/io.h
+++ b/include/asm-sh/sh03/io.h
@@ -14,22 +14,18 @@
14#define INTC_IPRD 0xffd00010UL 14#define INTC_IPRD 0xffd00010UL
15 15
16#define IRL0_IRQ 2 16#define IRL0_IRQ 2
17#define IRL0_IPR_ADDR INTC_IPRD
18#define IRL0_IPR_POS 3 17#define IRL0_IPR_POS 3
19#define IRL0_PRIORITY 13 18#define IRL0_PRIORITY 13
20 19
21#define IRL1_IRQ 5 20#define IRL1_IRQ 5
22#define IRL1_IPR_ADDR INTC_IPRD
23#define IRL1_IPR_POS 2 21#define IRL1_IPR_POS 2
24#define IRL1_PRIORITY 10 22#define IRL1_PRIORITY 10
25 23
26#define IRL2_IRQ 8 24#define IRL2_IRQ 8
27#define IRL2_IPR_ADDR INTC_IPRD
28#define IRL2_IPR_POS 1 25#define IRL2_IPR_POS 1
29#define IRL2_PRIORITY 7 26#define IRL2_PRIORITY 7
30 27
31#define IRL3_IRQ 11 28#define IRL3_IRQ 11
32#define IRL3_IPR_ADDR INTC_IPRD
33#define IRL3_IPR_POS 0 29#define IRL3_IPR_POS 0
34#define IRL3_PRIORITY 4 30#define IRL3_PRIORITY 4
35 31
diff --git a/include/asm-sh/smp.h b/include/asm-sh/smp.h
index caa7b93f1bce..b99ca786c0c1 100644
--- a/include/asm-sh/smp.h
+++ b/include/asm-sh/smp.h
@@ -39,4 +39,6 @@ extern struct smp_fn_call_struct smp_fn_call;
39 39
40#endif /* CONFIG_SMP */ 40#endif /* CONFIG_SMP */
41 41
42#define hard_smp_processor_id() (0)
43
42#endif /* __ASM_SH_SMP_H */ 44#endif /* __ASM_SH_SMP_H */
diff --git a/include/asm-sh/snapgear.h b/include/asm-sh/snapgear.h
index 2d712e72c9e5..3554e3a74e99 100644
--- a/include/asm-sh/snapgear.h
+++ b/include/asm-sh/snapgear.h
@@ -20,22 +20,18 @@
20 */ 20 */
21 21
22#define IRL0_IRQ 2 22#define IRL0_IRQ 2
23#define IRL0_IPR_ADDR INTC_IPRD
24#define IRL0_IPR_POS 3 23#define IRL0_IPR_POS 3
25#define IRL0_PRIORITY 13 24#define IRL0_PRIORITY 13
26 25
27#define IRL1_IRQ 5 26#define IRL1_IRQ 5
28#define IRL1_IPR_ADDR INTC_IPRD
29#define IRL1_IPR_POS 2 27#define IRL1_IPR_POS 2
30#define IRL1_PRIORITY 10 28#define IRL1_PRIORITY 10
31 29
32#define IRL2_IRQ 8 30#define IRL2_IRQ 8
33#define IRL2_IPR_ADDR INTC_IPRD
34#define IRL2_IPR_POS 1 31#define IRL2_IPR_POS 1
35#define IRL2_PRIORITY 7 32#define IRL2_PRIORITY 7
36 33
37#define IRL3_IRQ 11 34#define IRL3_IRQ 11
38#define IRL3_IPR_ADDR INTC_IPRD
39#define IRL3_IPR_POS 0 35#define IRL3_IPR_POS 0
40#define IRL3_PRIORITY 4 36#define IRL3_PRIORITY 4
41#endif 37#endif
diff --git a/include/asm-sh/sparsemem.h b/include/asm-sh/sparsemem.h
new file mode 100644
index 000000000000..547a540b6667
--- /dev/null
+++ b/include/asm-sh/sparsemem.h
@@ -0,0 +1,16 @@
1#ifndef __ASM_SH_SPARSEMEM_H
2#define __ASM_SH_SPARSEMEM_H
3
4#ifdef __KERNEL__
5/*
6 * SECTION_SIZE_BITS 2^N: how big each section will be
7 * MAX_PHYSADDR_BITS 2^N: how much physical address space we have
8 * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space
9 */
10#define SECTION_SIZE_BITS 26
11#define MAX_PHYSADDR_BITS 32
12#define MAX_PHYSMEM_BITS 32
13
14#endif
15
16#endif /* __ASM_SH_SPARSEMEM_H */
diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h
index 82f3e229e621..7c75045ae22b 100644
--- a/include/asm-sh/system.h
+++ b/include/asm-sh/system.h
@@ -8,9 +8,13 @@
8 8
9#include <linux/irqflags.h> 9#include <linux/irqflags.h>
10#include <linux/compiler.h> 10#include <linux/compiler.h>
11#include <linux/linkage.h>
11#include <asm/types.h> 12#include <asm/types.h>
12#include <asm/ptrace.h> 13#include <asm/ptrace.h>
13 14
15struct task_struct *__switch_to(struct task_struct *prev,
16 struct task_struct *next);
17
14/* 18/*
15 * switch_to() should switch tasks to task nr n, first 19 * switch_to() should switch tasks to task nr n, first
16 */ 20 */
@@ -122,7 +126,7 @@ static inline void sched_cacheflush(void)
122#define smp_read_barrier_depends() do { } while(0) 126#define smp_read_barrier_depends() do { } while(0)
123#endif 127#endif
124 128
125#define set_mb(var, value) do { xchg(&var, value); } while (0) 129#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
126 130
127/* 131/*
128 * Jump to P2 area. 132 * Jump to P2 area.
@@ -271,6 +275,16 @@ extern unsigned int instruction_size(unsigned int insn);
271void disable_hlt(void); 275void disable_hlt(void);
272void enable_hlt(void); 276void enable_hlt(void);
273 277
278void default_idle(void);
279
280asmlinkage void break_point_trap(void);
281asmlinkage void debug_trap_handler(unsigned long r4, unsigned long r5,
282 unsigned long r6, unsigned long r7,
283 struct pt_regs __regs);
284asmlinkage void bug_trap_handler(unsigned long r4, unsigned long r5,
285 unsigned long r6, unsigned long r7,
286 struct pt_regs __regs);
287
274#define arch_align_stack(x) (x) 288#define arch_align_stack(x) (x)
275 289
276#endif 290#endif
diff --git a/include/asm-sh/topology.h b/include/asm-sh/topology.h
index cff001c316fe..f402a3b1cfa4 100644
--- a/include/asm-sh/topology.h
+++ b/include/asm-sh/topology.h
@@ -1,6 +1,36 @@
1#ifndef _ASM_SH_TOPOLOGY_H 1#ifndef _ASM_SH_TOPOLOGY_H
2#define _ASM_SH_TOPOLOGY_H 2#define _ASM_SH_TOPOLOGY_H
3 3
4#ifdef CONFIG_NUMA
5
6/* sched_domains SD_NODE_INIT for sh machines */
7#define SD_NODE_INIT (struct sched_domain) { \
8 .span = CPU_MASK_NONE, \
9 .parent = NULL, \
10 .child = NULL, \
11 .groups = NULL, \
12 .min_interval = 8, \
13 .max_interval = 32, \
14 .busy_factor = 32, \
15 .imbalance_pct = 125, \
16 .cache_nice_tries = 2, \
17 .busy_idx = 3, \
18 .idle_idx = 2, \
19 .newidle_idx = 0, \
20 .wake_idx = 1, \
21 .forkexec_idx = 1, \
22 .flags = SD_LOAD_BALANCE \
23 | SD_BALANCE_FORK \
24 | SD_BALANCE_EXEC \
25 | SD_SERIALIZE \
26 | SD_WAKE_BALANCE, \
27 .last_balance = jiffies, \
28 .balance_interval = 1, \
29 .nr_balance_failed = 0, \
30}
31
32#endif
33
4#include <asm-generic/topology.h> 34#include <asm-generic/topology.h>
5 35
6#endif /* _ASM_SH_TOPOLOGY_H */ 36#endif /* _ASM_SH_TOPOLOGY_H */
diff --git a/include/asm-sh/uaccess.h b/include/asm-sh/uaccess.h
index 5c49ed6715f2..f18a1a5c95c0 100644
--- a/include/asm-sh/uaccess.h
+++ b/include/asm-sh/uaccess.h
@@ -61,8 +61,6 @@ static inline void set_fs(mm_segment_t s)
61 */ 61 */
62static inline int __access_ok(unsigned long addr, unsigned long size) 62static inline int __access_ok(unsigned long addr, unsigned long size)
63{ 63{
64 extern unsigned long memory_start, memory_end;
65
66 return ((addr >= memory_start) && ((addr + size) < memory_end)); 64 return ((addr >= memory_start) && ((addr + size) < memory_end));
67} 65}
68#else /* CONFIG_MMU */ 66#else /* CONFIG_MMU */
@@ -76,7 +74,7 @@ static inline int __access_ok(unsigned long addr, unsigned long size)
76 * __access_ok: Check if address with size is OK or not. 74 * __access_ok: Check if address with size is OK or not.
77 * 75 *
78 * We do three checks: 76 * We do three checks:
79 * (1) is it user space? 77 * (1) is it user space?
80 * (2) addr + size --> carry? 78 * (2) addr + size --> carry?
81 * (3) addr + size >= 0x80000000 (PAGE_OFFSET) 79 * (3) addr + size >= 0x80000000 (PAGE_OFFSET)
82 * 80 *
@@ -142,11 +140,12 @@ static inline int access_ok(int type, const void __user *p, unsigned long size)
142 __get_user_nocheck((x),(ptr),sizeof(*(ptr))) 140 __get_user_nocheck((x),(ptr),sizeof(*(ptr)))
143 141
144struct __large_struct { unsigned long buf[100]; }; 142struct __large_struct { unsigned long buf[100]; };
145#define __m(x) (*(struct __large_struct *)(x)) 143#define __m(x) (*(struct __large_struct __user *)(x))
146 144
147#define __get_user_size(x,ptr,size,retval) \ 145#define __get_user_size(x,ptr,size,retval) \
148do { \ 146do { \
149 retval = 0; \ 147 retval = 0; \
148 __chk_user_ptr(ptr); \
150 switch (size) { \ 149 switch (size) { \
151 case 1: \ 150 case 1: \
152 __get_user_asm(x, ptr, retval, "b"); \ 151 __get_user_asm(x, ptr, retval, "b"); \
@@ -175,6 +174,7 @@ do { \
175#define __get_user_check(x,ptr,size) \ 174#define __get_user_check(x,ptr,size) \
176({ \ 175({ \
177 long __gu_err, __gu_val; \ 176 long __gu_err, __gu_val; \
177 __chk_user_ptr(ptr); \
178 switch (size) { \ 178 switch (size) { \
179 case 1: \ 179 case 1: \
180 __get_user_1(__gu_val, (ptr), __gu_err); \ 180 __get_user_1(__gu_val, (ptr), __gu_err); \
@@ -300,6 +300,7 @@ extern void __get_user_unknown(void);
300#define __put_user_size(x,ptr,size,retval) \ 300#define __put_user_size(x,ptr,size,retval) \
301do { \ 301do { \
302 retval = 0; \ 302 retval = 0; \
303 __chk_user_ptr(ptr); \
303 switch (size) { \ 304 switch (size) { \
304 case 1: \ 305 case 1: \
305 __put_user_asm(x, ptr, retval, "b"); \ 306 __put_user_asm(x, ptr, retval, "b"); \
@@ -328,7 +329,7 @@ do { \
328#define __put_user_check(x,ptr,size) \ 329#define __put_user_check(x,ptr,size) \
329({ \ 330({ \
330 long __pu_err = -EFAULT; \ 331 long __pu_err = -EFAULT; \
331 __typeof__(*(ptr)) *__pu_addr = (ptr); \ 332 __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
332 \ 333 \
333 if (__access_ok((unsigned long)__pu_addr,size)) \ 334 if (__access_ok((unsigned long)__pu_addr,size)) \
334 __put_user_size((x),__pu_addr,(size),__pu_err); \ 335 __put_user_size((x),__pu_addr,(size),__pu_err); \
@@ -406,10 +407,10 @@ __asm__ __volatile__( \
406#endif 407#endif
407 408
408extern void __put_user_unknown(void); 409extern void __put_user_unknown(void);
409 410
410/* Generic arbitrary sized copy. */ 411/* Generic arbitrary sized copy. */
411/* Return the number of bytes NOT copied */ 412/* Return the number of bytes NOT copied */
412extern __kernel_size_t __copy_user(void *to, const void *from, __kernel_size_t n); 413__kernel_size_t __copy_user(void *to, const void *from, __kernel_size_t n);
413 414
414#define copy_to_user(to,from,n) ({ \ 415#define copy_to_user(to,from,n) ({ \
415void *__copy_to = (void *) (to); \ 416void *__copy_to = (void *) (to); \
@@ -420,14 +421,6 @@ __copy_res = __copy_user(__copy_to, (void *) (from), __copy_size); \
420} else __copy_res = __copy_size; \ 421} else __copy_res = __copy_size; \
421__copy_res; }) 422__copy_res; })
422 423
423#define __copy_to_user(to,from,n) \
424 __copy_user((void *)(to), \
425 (void *)(from), n)
426
427#define __copy_to_user_inatomic __copy_to_user
428#define __copy_from_user_inatomic __copy_from_user
429
430
431#define copy_from_user(to,from,n) ({ \ 424#define copy_from_user(to,from,n) ({ \
432void *__copy_to = (void *) (to); \ 425void *__copy_to = (void *) (to); \
433void *__copy_from = (void *) (from); \ 426void *__copy_from = (void *) (from); \
@@ -438,9 +431,20 @@ __copy_res = __copy_user(__copy_to, __copy_from, __copy_size); \
438} else __copy_res = __copy_size; \ 431} else __copy_res = __copy_size; \
439__copy_res; }) 432__copy_res; })
440 433
441#define __copy_from_user(to,from,n) \ 434static __always_inline unsigned long
442 __copy_user((void *)(to), \ 435__copy_from_user(void *to, const void __user *from, unsigned long n)
443 (void *)(from), n) 436{
437 return __copy_user(to, (__force void *)from, n);
438}
439
440static __always_inline unsigned long __must_check
441__copy_to_user(void __user *to, const void *from, unsigned long n)
442{
443 return __copy_user((__force void *)to, from, n);
444}
445
446#define __copy_to_user_inatomic __copy_to_user
447#define __copy_from_user_inatomic __copy_from_user
444 448
445/* 449/*
446 * Clear the area and return remaining number of bytes 450 * Clear the area and return remaining number of bytes
diff --git a/include/asm-sh/ubc.h b/include/asm-sh/ubc.h
index ae9bbdeefbe1..38d46e01b846 100644
--- a/include/asm-sh/ubc.h
+++ b/include/asm-sh/ubc.h
@@ -51,9 +51,14 @@
51#define BRCR_UBDE (1 << 0) 51#define BRCR_UBDE (1 << 0)
52 52
53#ifndef __ASSEMBLY__ 53#ifndef __ASSEMBLY__
54/* arch/sh/kernel/ubc.S */ 54/* arch/sh/kernel/cpu/ubc.S */
55extern void ubc_wakeup(void);
56extern void ubc_sleep(void); 55extern void ubc_sleep(void);
56
57#ifdef CONFIG_UBC_WAKEUP
58extern void ubc_wakeup(void);
59#else
60#define ubc_wakeup() do { } while (0)
61#endif
57#endif 62#endif
58 63
59#endif /* __KERNEL__ */ 64#endif /* __KERNEL__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 17:56:46 -0500