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-rw-r--r--include/asm-sh/a.out.h26
-rw-r--r--include/asm-sh/adc.h13
-rw-r--r--include/asm-sh/addrspace.h38
-rw-r--r--include/asm-sh/adx/io.h86
-rw-r--r--include/asm-sh/atomic.h114
-rw-r--r--include/asm-sh/bigsur/bigsur.h80
-rw-r--r--include/asm-sh/bigsur/io.h35
-rw-r--r--include/asm-sh/bigsur/serial.h27
-rw-r--r--include/asm-sh/bitops.h476
-rw-r--r--include/asm-sh/bug.h17
-rw-r--r--include/asm-sh/bugs.h50
-rw-r--r--include/asm-sh/bus-sh.h65
-rw-r--r--include/asm-sh/byteorder.h56
-rw-r--r--include/asm-sh/cache.h48
-rw-r--r--include/asm-sh/cacheflush.h31
-rw-r--r--include/asm-sh/cat68701/io.h22
-rw-r--r--include/asm-sh/checksum.h216
-rw-r--r--include/asm-sh/cpu-sh2/addrspace.h16
-rw-r--r--include/asm-sh/cpu-sh2/cache.h31
-rw-r--r--include/asm-sh/cpu-sh2/cacheflush.h42
-rw-r--r--include/asm-sh/cpu-sh2/dma.h23
-rw-r--r--include/asm-sh/cpu-sh2/shmparam.h16
-rw-r--r--include/asm-sh/cpu-sh2/sigcontext.h17
-rw-r--r--include/asm-sh/cpu-sh2/ubc.h32
-rw-r--r--include/asm-sh/cpu-sh2/watchdog.h69
-rw-r--r--include/asm-sh/cpu-sh3/adc.h28
-rw-r--r--include/asm-sh/cpu-sh3/addrspace.h16
-rw-r--r--include/asm-sh/cpu-sh3/cache.h37
-rw-r--r--include/asm-sh/cpu-sh3/cacheflush.h87
-rw-r--r--include/asm-sh/cpu-sh3/dac.h41
-rw-r--r--include/asm-sh/cpu-sh3/dma.h7
-rw-r--r--include/asm-sh/cpu-sh3/freq.h22
-rw-r--r--include/asm-sh/cpu-sh3/mmu_context.h28
-rw-r--r--include/asm-sh/cpu-sh3/rtc.h25
-rw-r--r--include/asm-sh/cpu-sh3/shmparam.h16
-rw-r--r--include/asm-sh/cpu-sh3/sigcontext.h17
-rw-r--r--include/asm-sh/cpu-sh3/timer.h64
-rw-r--r--include/asm-sh/cpu-sh3/ubc.h27
-rw-r--r--include/asm-sh/cpu-sh3/watchdog.h25
-rw-r--r--include/asm-sh/cpu-sh4/addrspace.h26
-rw-r--r--include/asm-sh/cpu-sh4/cache.h35
-rw-r--r--include/asm-sh/cpu-sh4/cacheflush.h64
-rw-r--r--include/asm-sh/cpu-sh4/dma.h17
-rw-r--r--include/asm-sh/cpu-sh4/freq.h22
-rw-r--r--include/asm-sh/cpu-sh4/mmu_context.h39
-rw-r--r--include/asm-sh/cpu-sh4/rtc.h25
-rw-r--r--include/asm-sh/cpu-sh4/shmparam.h19
-rw-r--r--include/asm-sh/cpu-sh4/sigcontext.h24
-rw-r--r--include/asm-sh/cpu-sh4/sq.h48
-rw-r--r--include/asm-sh/cpu-sh4/timer.h51
-rw-r--r--include/asm-sh/cpu-sh4/ubc.h27
-rw-r--r--include/asm-sh/cpu-sh4/watchdog.h25
-rw-r--r--include/asm-sh/cputime.h6
-rw-r--r--include/asm-sh/cqreek/cqreek.h27
-rw-r--r--include/asm-sh/current.h20
-rw-r--r--include/asm-sh/delay.h27
-rw-r--r--include/asm-sh/div64.h1
-rw-r--r--include/asm-sh/dma-mapping.h179
-rw-r--r--include/asm-sh/dma.h143
-rw-r--r--include/asm-sh/dmida/io.h10
-rw-r--r--include/asm-sh/dreamcast/dma.h34
-rw-r--r--include/asm-sh/dreamcast/pci.h25
-rw-r--r--include/asm-sh/dreamcast/sysasic.h43
-rw-r--r--include/asm-sh/ec3104/ec3104.h43
-rw-r--r--include/asm-sh/ec3104/io.h16
-rw-r--r--include/asm-sh/ec3104/keyboard.h17
-rw-r--r--include/asm-sh/ec3104/serial.h22
-rw-r--r--include/asm-sh/edosk7705/io.h30
-rw-r--r--include/asm-sh/elf.h121
-rw-r--r--include/asm-sh/errno.h6
-rw-r--r--include/asm-sh/fcntl.h88
-rw-r--r--include/asm-sh/fixmap.h111
-rw-r--r--include/asm-sh/flat.h23
-rw-r--r--include/asm-sh/floppy.h274
-rw-r--r--include/asm-sh/freq.h29
-rw-r--r--include/asm-sh/hardirq.h17
-rw-r--r--include/asm-sh/harp/harp.h43
-rw-r--r--include/asm-sh/harp/io.h10
-rw-r--r--include/asm-sh/hd64461/hd64461.h203
-rw-r--r--include/asm-sh/hd64461/io.h43
-rw-r--r--include/asm-sh/hd64465/gpio.h46
-rw-r--r--include/asm-sh/hd64465/hd64465.h257
-rw-r--r--include/asm-sh/hd64465/io.h44
-rw-r--r--include/asm-sh/hdreg.h1
-rw-r--r--include/asm-sh/hp6xx/hp6xx.h31
-rw-r--r--include/asm-sh/hp6xx/ide.h8
-rw-r--r--include/asm-sh/hp6xx/io.h10
-rw-r--r--include/asm-sh/hs7751rvoip/hs7751rvoip.h47
-rw-r--r--include/asm-sh/hs7751rvoip/ide.h8
-rw-r--r--include/asm-sh/hs7751rvoip/io.h39
-rw-r--r--include/asm-sh/hw_irq.h9
-rw-r--r--include/asm-sh/ide.h29
-rw-r--r--include/asm-sh/io.h311
-rw-r--r--include/asm-sh/io_generic.h51
-rw-r--r--include/asm-sh/ioctl.h75
-rw-r--r--include/asm-sh/ioctls.h99
-rw-r--r--include/asm-sh/ipc.h1
-rw-r--r--include/asm-sh/ipcbuf.h29
-rw-r--r--include/asm-sh/irq-sh73180.h350
-rw-r--r--include/asm-sh/irq.h598
-rw-r--r--include/asm-sh/keyboard.h14
-rw-r--r--include/asm-sh/kgdb.h131
-rw-r--r--include/asm-sh/kmap_types.h33
-rw-r--r--include/asm-sh/linkage.h7
-rw-r--r--include/asm-sh/local.h7
-rw-r--r--include/asm-sh/machvec.h73
-rw-r--r--include/asm-sh/machvec_init.h54
-rw-r--r--include/asm-sh/mc146818rtc.h176
-rw-r--r--include/asm-sh/microdev/io.h53
-rw-r--r--include/asm-sh/microdev/irq.h72
-rw-r--r--include/asm-sh/mman.h43
-rw-r--r--include/asm-sh/mmu.h29
-rw-r--r--include/asm-sh/mmu_context.h206
-rw-r--r--include/asm-sh/mmzone.h61
-rw-r--r--include/asm-sh/module.h40
-rw-r--r--include/asm-sh/mpc1211/dma.h304
-rw-r--r--include/asm-sh/mpc1211/io.h22
-rw-r--r--include/asm-sh/mpc1211/keyboard.h64
-rw-r--r--include/asm-sh/mpc1211/m1543c.h200
-rw-r--r--include/asm-sh/mpc1211/mc146818rtc.h6
-rw-r--r--include/asm-sh/mpc1211/mpc1211.h18
-rw-r--r--include/asm-sh/mpc1211/pci.h40
-rw-r--r--include/asm-sh/msgbuf.h31
-rw-r--r--include/asm-sh/namei.h17
-rw-r--r--include/asm-sh/numnodes.h7
-rw-r--r--include/asm-sh/overdrive/fpga.h15
-rw-r--r--include/asm-sh/overdrive/gt64111.h109
-rw-r--r--include/asm-sh/overdrive/io.h39
-rw-r--r--include/asm-sh/overdrive/overdrive.h89
-rw-r--r--include/asm-sh/page.h144
-rw-r--r--include/asm-sh/param.h26
-rw-r--r--include/asm-sh/pci.h120
-rw-r--r--include/asm-sh/percpu.h6
-rw-r--r--include/asm-sh/pgalloc.h88
-rw-r--r--include/asm-sh/pgtable-2level.h67
-rw-r--r--include/asm-sh/pgtable.h306
-rw-r--r--include/asm-sh/poll.h26
-rw-r--r--include/asm-sh/posix_types.h122
-rw-r--r--include/asm-sh/processor.h275
-rw-r--r--include/asm-sh/ptrace.h104
-rw-r--r--include/asm-sh/resource.h6
-rw-r--r--include/asm-sh/rtc.h29
-rw-r--r--include/asm-sh/rts7751r2d/ide.h8
-rw-r--r--include/asm-sh/rts7751r2d/io.h37
-rw-r--r--include/asm-sh/rts7751r2d/rts7751r2d.h73
-rw-r--r--include/asm-sh/rts7751r2d/voyagergx_reg.h313
-rw-r--r--include/asm-sh/rwsem.h170
-rw-r--r--include/asm-sh/saturn/io.h19
-rw-r--r--include/asm-sh/saturn/smpc.h34
-rw-r--r--include/asm-sh/scatterlist.h13
-rw-r--r--include/asm-sh/se/io.h35
-rw-r--r--include/asm-sh/se/se.h77
-rw-r--r--include/asm-sh/se/smc37c93x.h190
-rw-r--r--include/asm-sh/se7300/io.h29
-rw-r--r--include/asm-sh/se7300/se7300.h61
-rw-r--r--include/asm-sh/se73180/io.h32
-rw-r--r--include/asm-sh/se73180/se73180.h62
-rw-r--r--include/asm-sh/se7751/io.h42
-rw-r--r--include/asm-sh/se7751/se7751.h68
-rw-r--r--include/asm-sh/sections.h9
-rw-r--r--include/asm-sh/segment.h6
-rw-r--r--include/asm-sh/semaphore-helper.h89
-rw-r--r--include/asm-sh/semaphore.h119
-rw-r--r--include/asm-sh/sembuf.h25
-rw-r--r--include/asm-sh/serial.h48
-rw-r--r--include/asm-sh/setup.h8
-rw-r--r--include/asm-sh/sh03/ide.h7
-rw-r--r--include/asm-sh/sh03/io.h46
-rw-r--r--include/asm-sh/sh03/sh03.h18
-rw-r--r--include/asm-sh/sh2000/sh2000.h8
-rw-r--r--include/asm-sh/sh_bios.h19
-rw-r--r--include/asm-sh/shmbuf.h42
-rw-r--r--include/asm-sh/shmparam.h8
-rw-r--r--include/asm-sh/sigcontext.h26
-rw-r--r--include/asm-sh/siginfo.h6
-rw-r--r--include/asm-sh/signal.h185
-rw-r--r--include/asm-sh/smp.h48
-rw-r--r--include/asm-sh/snapgear/io.h92
-rw-r--r--include/asm-sh/socket.h50
-rw-r--r--include/asm-sh/sockios.h13
-rw-r--r--include/asm-sh/spinlock.h124
-rw-r--r--include/asm-sh/stat.h84
-rw-r--r--include/asm-sh/statfs.h6
-rw-r--r--include/asm-sh/string.h127
-rw-r--r--include/asm-sh/system.h264
-rw-r--r--include/asm-sh/systemh/7751systemh.h68
-rw-r--r--include/asm-sh/systemh/io.h43
-rw-r--r--include/asm-sh/termbits.h173
-rw-r--r--include/asm-sh/termios.h106
-rw-r--r--include/asm-sh/thread_info.h102
-rw-r--r--include/asm-sh/timex.h18
-rw-r--r--include/asm-sh/tlb.h18
-rw-r--r--include/asm-sh/tlbflush.h31
-rw-r--r--include/asm-sh/topology.h6
-rw-r--r--include/asm-sh/types.h67
-rw-r--r--include/asm-sh/uaccess.h600
-rw-r--r--include/asm-sh/ubc.h60
-rw-r--r--include/asm-sh/ucontext.h12
-rw-r--r--include/asm-sh/unaligned.h7
-rw-r--r--include/asm-sh/unistd.h523
-rw-r--r--include/asm-sh/user.h60
-rw-r--r--include/asm-sh/watchdog.h111
-rw-r--r--include/asm-sh/xor.h1
203 files changed, 14187 insertions, 0 deletions
diff --git a/include/asm-sh/a.out.h b/include/asm-sh/a.out.h
new file mode 100644
index 000000000000..6e9fca9ee333
--- /dev/null
+++ b/include/asm-sh/a.out.h
@@ -0,0 +1,26 @@
1#ifndef __ASM_SH_A_OUT_H
2#define __ASM_SH_A_OUT_H
3
4struct exec
5{
6 unsigned long a_info; /* Use macros N_MAGIC, etc for access */
7 unsigned a_text; /* length of text, in bytes */
8 unsigned a_data; /* length of data, in bytes */
9 unsigned a_bss; /* length of uninitialized data area for file, in bytes */
10 unsigned a_syms; /* length of symbol table data in file, in bytes */
11 unsigned a_entry; /* start address */
12 unsigned a_trsize; /* length of relocation info for text, in bytes */
13 unsigned a_drsize; /* length of relocation info for data, in bytes */
14};
15
16#define N_TRSIZE(a) ((a).a_trsize)
17#define N_DRSIZE(a) ((a).a_drsize)
18#define N_SYMSIZE(a) ((a).a_syms)
19
20#ifdef __KERNEL__
21
22#define STACK_TOP TASK_SIZE
23
24#endif
25
26#endif /* __ASM_SH_A_OUT_H */
diff --git a/include/asm-sh/adc.h b/include/asm-sh/adc.h
new file mode 100644
index 000000000000..5f85cf74d59d
--- /dev/null
+++ b/include/asm-sh/adc.h
@@ -0,0 +1,13 @@
1#ifndef __ASM_ADC_H
2#define __ASM_ADC_H
3#ifdef __KERNEL__
4/*
5 * Copyright (C) 2004 Andriy Skulysh
6 */
7
8#include <asm/cpu/adc.h>
9
10int adc_single(unsigned int channel);
11
12#endif /* __KERNEL__ */
13#endif /* __ASM_ADC_H */
diff --git a/include/asm-sh/addrspace.h b/include/asm-sh/addrspace.h
new file mode 100644
index 000000000000..dbb05d1a26d1
--- /dev/null
+++ b/include/asm-sh/addrspace.h
@@ -0,0 +1,38 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999 by Kaz Kojima
7 *
8 * Defitions for the address spaces of the SH CPUs.
9 */
10#ifndef __ASM_SH_ADDRSPACE_H
11#define __ASM_SH_ADDRSPACE_H
12#ifdef __KERNEL__
13
14#include <asm/cpu/addrspace.h>
15
16/* Memory segments (32bit Priviledged mode addresses) */
17#define P0SEG 0x00000000
18#define P1SEG 0x80000000
19#define P2SEG 0xa0000000
20#define P3SEG 0xc0000000
21#define P4SEG 0xe0000000
22
23/* Returns the privileged segment base of a given address */
24#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000)
25
26/* Returns the physical address of a PnSEG (n=1,2) address */
27#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
28
29/*
30 * Map an address to a certain privileged segment
31 */
32#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))
33#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))
34#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
35#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
36
37#endif /* __KERNEL__ */
38#endif /* __ASM_SH_ADDRSPACE_H */
diff --git a/include/asm-sh/adx/io.h b/include/asm-sh/adx/io.h
new file mode 100644
index 000000000000..ab1225f1d557
--- /dev/null
+++ b/include/asm-sh/adx/io.h
@@ -0,0 +1,86 @@
1/*
2 * include/asm-sh/io_adx.h
3 *
4 * Copyright (C) 2001 A&D Co., Ltd.
5 *
6 * This file may be copied or modified under the terms of the GNU
7 * General Public License. See linux/COPYING for more information.
8 *
9 * IO functions for an A&D ADX Board
10 */
11
12#ifndef _ASM_SH_IO_ADX_H
13#define _ASM_SH_IO_ADX_H
14
15#include <asm/io_generic.h>
16
17extern unsigned char adx_inb(unsigned long port);
18extern unsigned short adx_inw(unsigned long port);
19extern unsigned int adx_inl(unsigned long port);
20
21extern void adx_outb(unsigned char value, unsigned long port);
22extern void adx_outw(unsigned short value, unsigned long port);
23extern void adx_outl(unsigned int value, unsigned long port);
24
25extern unsigned char adx_inb_p(unsigned long port);
26extern void adx_outb_p(unsigned char value, unsigned long port);
27
28extern void adx_insb(unsigned long port, void *addr, unsigned long count);
29extern void adx_insw(unsigned long port, void *addr, unsigned long count);
30extern void adx_insl(unsigned long port, void *addr, unsigned long count);
31extern void adx_outsb(unsigned long port, const void *addr, unsigned long count);
32extern void adx_outsw(unsigned long port, const void *addr, unsigned long count);
33extern void adx_outsl(unsigned long port, const void *addr, unsigned long count);
34
35extern unsigned char adx_readb(unsigned long addr);
36extern unsigned short adx_readw(unsigned long addr);
37extern unsigned int adx_readl(unsigned long addr);
38extern void adx_writeb(unsigned char b, unsigned long addr);
39extern void adx_writew(unsigned short b, unsigned long addr);
40extern void adx_writel(unsigned int b, unsigned long addr);
41
42extern void * adx_ioremap(unsigned long offset, unsigned long size);
43extern void adx_iounmap(void *addr);
44
45extern unsigned long adx_isa_port2addr(unsigned long offset);
46
47extern void setup_adx(void);
48extern void init_adx_IRQ(void);
49
50#ifdef __WANT_IO_DEF
51
52#define __inb adx_inb
53#define __inw adx_inw
54#define __inl adx_inl
55#define __outb adx_outb
56#define __outw adx_outw
57#define __outl adx_outl
58
59#define __inb_p adx_inb_p
60#define __inw_p adx_inw
61#define __inl_p adx_inl
62#define __outb_p adx_outb_p
63#define __outw_p adx_outw
64#define __outl_p adx_outl
65
66#define __insb adx_insb
67#define __insw adx_insw
68#define __insl adx_insl
69#define __outsb adx_outsb
70#define __outsw adx_outsw
71#define __outsl adx_outsl
72
73#define __readb adx_readb
74#define __readw adx_readw
75#define __readl adx_readl
76#define __writeb adx_writeb
77#define __writew adx_writew
78#define __writel adx_writel
79
80#define __isa_port2addr adx_isa_port2addr
81#define __ioremap adx_ioremap
82#define __iounmap adx_iounmap
83
84#endif
85
86#endif /* _ASM_SH_IO_AANDD_H */
diff --git a/include/asm-sh/atomic.h b/include/asm-sh/atomic.h
new file mode 100644
index 000000000000..3c4f805da1ac
--- /dev/null
+++ b/include/asm-sh/atomic.h
@@ -0,0 +1,114 @@
1#ifndef __ASM_SH_ATOMIC_H
2#define __ASM_SH_ATOMIC_H
3
4/*
5 * Atomic operations that C can't guarantee us. Useful for
6 * resource counting etc..
7 *
8 */
9
10typedef struct { volatile int counter; } atomic_t;
11
12#define ATOMIC_INIT(i) ( (atomic_t) { (i) } )
13
14#define atomic_read(v) ((v)->counter)
15#define atomic_set(v,i) ((v)->counter = (i))
16
17#include <asm/system.h>
18
19/*
20 * To get proper branch prediction for the main line, we must branch
21 * forward to code at the end of this object's .text section, then
22 * branch back to restart the operation.
23 */
24
25static __inline__ void atomic_add(int i, atomic_t * v)
26{
27 unsigned long flags;
28
29 local_irq_save(flags);
30 *(long *)v += i;
31 local_irq_restore(flags);
32}
33
34static __inline__ void atomic_sub(int i, atomic_t *v)
35{
36 unsigned long flags;
37
38 local_irq_save(flags);
39 *(long *)v -= i;
40 local_irq_restore(flags);
41}
42
43static __inline__ int atomic_add_return(int i, atomic_t * v)
44{
45 unsigned long temp, flags;
46
47 local_irq_save(flags);
48 temp = *(long *)v;
49 temp += i;
50 *(long *)v = temp;
51 local_irq_restore(flags);
52
53 return temp;
54}
55
56#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
57
58static __inline__ int atomic_sub_return(int i, atomic_t * v)
59{
60 unsigned long temp, flags;
61
62 local_irq_save(flags);
63 temp = *(long *)v;
64 temp -= i;
65 *(long *)v = temp;
66 local_irq_restore(flags);
67
68 return temp;
69}
70
71#define atomic_dec_return(v) atomic_sub_return(1,(v))
72#define atomic_inc_return(v) atomic_add_return(1,(v))
73
74/*
75 * atomic_inc_and_test - increment and test
76 * @v: pointer of type atomic_t
77 *
78 * Atomically increments @v by 1
79 * and returns true if the result is zero, or false for all
80 * other cases.
81 */
82#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
83
84#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
85#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
86
87#define atomic_inc(v) atomic_add(1,(v))
88#define atomic_dec(v) atomic_sub(1,(v))
89
90static __inline__ void atomic_clear_mask(unsigned int mask, atomic_t *v)
91{
92 unsigned long flags;
93
94 local_irq_save(flags);
95 *(long *)v &= ~mask;
96 local_irq_restore(flags);
97}
98
99static __inline__ void atomic_set_mask(unsigned int mask, atomic_t *v)
100{
101 unsigned long flags;
102
103 local_irq_save(flags);
104 *(long *)v |= mask;
105 local_irq_restore(flags);
106}
107
108/* Atomic operations are already serializing on SH */
109#define smp_mb__before_atomic_dec() barrier()
110#define smp_mb__after_atomic_dec() barrier()
111#define smp_mb__before_atomic_inc() barrier()
112#define smp_mb__after_atomic_inc() barrier()
113
114#endif /* __ASM_SH_ATOMIC_H */
diff --git a/include/asm-sh/bigsur/bigsur.h b/include/asm-sh/bigsur/bigsur.h
new file mode 100644
index 000000000000..427245f93589
--- /dev/null
+++ b/include/asm-sh/bigsur/bigsur.h
@@ -0,0 +1,80 @@
1/*
2 *
3 * Hitachi Big Sur Eval Board support
4 *
5 * Dustin McIntire (dustin@sensoria.com)
6 *
7 * May be copied or modified under the terms of the GNU General Public
8 * License. See linux/COPYING for more information.
9 *
10 * Derived from Hitachi SH7751 reference manual
11 *
12 */
13
14#ifndef _ASM_BIGSUR_H_
15#define _ASM_BIGSUR_H_
16
17#include <asm/irq.h>
18#include <asm/hd64465/hd64465.h>
19
20/* 7751 Internal IRQ's used by external CPLD controller */
21#define BIGSUR_IRQ_LOW 0
22#define BIGSUR_IRQ_NUM 14 /* External CPLD level 1 IRQs */
23#define BIGSUR_IRQ_HIGH (BIGSUR_IRQ_LOW + BIGSUR_IRQ_NUM)
24#define BIGSUR_2NDLVL_IRQ_LOW (HD64465_IRQ_BASE+HD64465_IRQ_NUM)
25#define BIGSUR_2NDLVL_IRQ_NUM 32 /* Level 2 IRQs = 4 regs * 8 bits */
26#define BIGSUR_2NDLVL_IRQ_HIGH (BIGSUR_2NDLVL_IRQ_LOW + \
27 BIGSUR_2NDLVL_IRQ_NUM)
28
29/* PCI interrupt base number (A_INTA-A_INTD) */
30#define BIGSUR_SH7751_PCI_IRQ_BASE (BIGSUR_2NDLVL_IRQ_LOW+10)
31
32/* CPLD registers and external chip addresses */
33#define BIGSUR_HD64464_ADDR 0xB2000000
34#define BIGSUR_DGDR 0xB1FFFE00
35#define BIGSUR_BIDR 0xB1FFFD00
36#define BIGSUR_CSLR 0xB1FFFC00
37#define BIGSUR_SW1R 0xB1FFFB00
38#define BIGSUR_DBGR 0xB1FFFA00
39#define BIGSUR_BDTR 0xB1FFF900
40#define BIGSUR_BDRR 0xB1FFF800
41#define BIGSUR_PPR1 0xB1FFF700
42#define BIGSUR_PPR2 0xB1FFF600
43#define BIGSUR_IDE2 0xB1FFF500
44#define BIGSUR_IDE3 0xB1FFF400
45#define BIGSUR_SPCR 0xB1FFF300
46#define BIGSUR_ETHR 0xB1FE0000
47#define BIGSUR_PPDR 0xB1FDFF00
48#define BIGSUR_ICTL 0xB1FDFE00
49#define BIGSUR_ICMD 0xB1FDFD00
50#define BIGSUR_DMA0 0xB1FDFC00
51#define BIGSUR_DMA1 0xB1FDFB00
52#define BIGSUR_IRQ0 0xB1FDFA00
53#define BIGSUR_IRQ1 0xB1FDF900
54#define BIGSUR_IRQ2 0xB1FDF800
55#define BIGSUR_IRQ3 0xB1FDF700
56#define BIGSUR_IMR0 0xB1FDF600
57#define BIGSUR_IMR1 0xB1FDF500
58#define BIGSUR_IMR2 0xB1FDF400
59#define BIGSUR_IMR3 0xB1FDF300
60#define BIGSUR_IRLMR0 0xB1FDF200
61#define BIGSUR_IRLMR1 0xB1FDF100
62#define BIGSUR_V320USC_ADDR 0xB1000000
63#define BIGSUR_HD64465_ADDR 0xB0000000
64#define BIGSUR_INTERNAL_BASE 0xB0000000
65
66/* SMC ethernet card parameters */
67#define BIGSUR_ETHER_IOPORT 0x220
68
69/* IDE register paramters */
70#define BIGSUR_IDECMD_IOPORT 0x1f0
71#define BIGSUR_IDECTL_IOPORT 0x1f8
72
73/* LED bit position in BIGSUR_CSLR */
74#define BIGSUR_LED (1<<4)
75
76/* PCI: default LOCAL memory window sizes (seen from PCI bus) */
77#define BIGSUR_LSR0_SIZE (64*(1<<20)) //64MB
78#define BIGSUR_LSR1_SIZE (64*(1<<20)) //64MB
79
80#endif /* _ASM_BIGSUR_H_ */
diff --git a/include/asm-sh/bigsur/io.h b/include/asm-sh/bigsur/io.h
new file mode 100644
index 000000000000..939735ee8dc5
--- /dev/null
+++ b/include/asm-sh/bigsur/io.h
@@ -0,0 +1,35 @@
1/*
2 * include/asm-sh/io_bigsur.h
3 *
4 * By Dustin McIntire (dustin@sensoria.com) (c)2001
5 * Derived from io_hd64465.h, which bore the message:
6 * By Greg Banks <gbanks@pocketpenguins.com>
7 * (c) 2000 PocketPenguins Inc.
8 * and from io_hd64461.h, which bore the message:
9 * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
10 *
11 * May be copied or modified under the terms of the GNU General Public
12 * License. See linux/COPYING for more information.
13 *
14 * IO functions for a Hitachi Big Sur Evaluation Board.
15 */
16
17#ifndef _ASM_SH_IO_BIGSUR_H
18#define _ASM_SH_IO_BIGSUR_H
19
20#include <linux/types.h>
21
22extern unsigned long bigsur_isa_port2addr(unsigned long offset);
23extern int bigsur_irq_demux(int irq);
24/* Provision for generic secondary demux step -- used by PCMCIA code */
25extern void bigsur_register_irq_demux(int irq,
26 int (*demux)(int irq, void *dev), void *dev);
27extern void bigsur_unregister_irq_demux(int irq);
28/* Set this variable to 1 to see port traffic */
29extern int bigsur_io_debug;
30/* Map a range of ports to a range of kernel virtual memory. */
31extern void bigsur_port_map(u32 baseport, u32 nports, u32 addr, u8 shift);
32extern void bigsur_port_unmap(u32 baseport, u32 nports);
33
34#endif /* _ASM_SH_IO_BIGSUR_H */
35
diff --git a/include/asm-sh/bigsur/serial.h b/include/asm-sh/bigsur/serial.h
new file mode 100644
index 000000000000..540f12205923
--- /dev/null
+++ b/include/asm-sh/bigsur/serial.h
@@ -0,0 +1,27 @@
1/*
2 * include/asm-sh/serial-bigsur.h
3 *
4 * Configuration details for Big Sur 16550 based serial ports
5 * i.e. HD64465, PCMCIA, etc.
6 */
7
8#ifndef _ASM_SERIAL_BIGSUR_H
9#define _ASM_SERIAL_BIGSUR_H
10#include <asm/hd64465.h>
11
12#define BASE_BAUD (3379200 / 16)
13
14#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
15
16
17#define STD_SERIAL_PORT_DEFNS \
18 /* UART CLK PORT IRQ FLAGS */ \
19 { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */
20
21
22#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS
23
24/* XXX: This should be moved ino irq.h */
25#define irq_cannonicalize(x) (x)
26
27#endif /* _ASM_SERIAL_BIGSUR_H */
diff --git a/include/asm-sh/bitops.h b/include/asm-sh/bitops.h
new file mode 100644
index 000000000000..5163d1ff2f1b
--- /dev/null
+++ b/include/asm-sh/bitops.h
@@ -0,0 +1,476 @@
1#ifndef __ASM_SH_BITOPS_H
2#define __ASM_SH_BITOPS_H
3
4#ifdef __KERNEL__
5#include <asm/system.h>
6/* For __swab32 */
7#include <asm/byteorder.h>
8
9static __inline__ void set_bit(int nr, volatile void * addr)
10{
11 int mask;
12 volatile unsigned int *a = addr;
13 unsigned long flags;
14
15 a += nr >> 5;
16 mask = 1 << (nr & 0x1f);
17 local_irq_save(flags);
18 *a |= mask;
19 local_irq_restore(flags);
20}
21
22static __inline__ void __set_bit(int nr, volatile void * addr)
23{
24 int mask;
25 volatile unsigned int *a = addr;
26
27 a += nr >> 5;
28 mask = 1 << (nr & 0x1f);
29 *a |= mask;
30}
31
32/*
33 * clear_bit() doesn't provide any barrier for the compiler.
34 */
35#define smp_mb__before_clear_bit() barrier()
36#define smp_mb__after_clear_bit() barrier()
37static __inline__ void clear_bit(int nr, volatile void * addr)
38{
39 int mask;
40 volatile unsigned int *a = addr;
41 unsigned long flags;
42
43 a += nr >> 5;
44 mask = 1 << (nr & 0x1f);
45 local_irq_save(flags);
46 *a &= ~mask;
47 local_irq_restore(flags);
48}
49
50static __inline__ void __clear_bit(int nr, volatile void * addr)
51{
52 int mask;
53 volatile unsigned int *a = addr;
54
55 a += nr >> 5;
56 mask = 1 << (nr & 0x1f);
57 *a &= ~mask;
58}
59
60static __inline__ void change_bit(int nr, volatile void * addr)
61{
62 int mask;
63 volatile unsigned int *a = addr;
64 unsigned long flags;
65
66 a += nr >> 5;
67 mask = 1 << (nr & 0x1f);
68 local_irq_save(flags);
69 *a ^= mask;
70 local_irq_restore(flags);
71}
72
73static __inline__ void __change_bit(int nr, volatile void * addr)
74{
75 int mask;
76 volatile unsigned int *a = addr;
77
78 a += nr >> 5;
79 mask = 1 << (nr & 0x1f);
80 *a ^= mask;
81}
82
83static __inline__ int test_and_set_bit(int nr, volatile void * addr)
84{
85 int mask, retval;
86 volatile unsigned int *a = addr;
87 unsigned long flags;
88
89 a += nr >> 5;
90 mask = 1 << (nr & 0x1f);
91 local_irq_save(flags);
92 retval = (mask & *a) != 0;
93 *a |= mask;
94 local_irq_restore(flags);
95
96 return retval;
97}
98
99static __inline__ int __test_and_set_bit(int nr, volatile void * addr)
100{
101 int mask, retval;
102 volatile unsigned int *a = addr;
103
104 a += nr >> 5;
105 mask = 1 << (nr & 0x1f);
106 retval = (mask & *a) != 0;
107 *a |= mask;
108
109 return retval;
110}
111
112static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
113{
114 int mask, retval;
115 volatile unsigned int *a = addr;
116 unsigned long flags;
117
118 a += nr >> 5;
119 mask = 1 << (nr & 0x1f);
120 local_irq_save(flags);
121 retval = (mask & *a) != 0;
122 *a &= ~mask;
123 local_irq_restore(flags);
124
125 return retval;
126}
127
128static __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
129{
130 int mask, retval;
131 volatile unsigned int *a = addr;
132
133 a += nr >> 5;
134 mask = 1 << (nr & 0x1f);
135 retval = (mask & *a) != 0;
136 *a &= ~mask;
137
138 return retval;
139}
140
141static __inline__ int test_and_change_bit(int nr, volatile void * addr)
142{
143 int mask, retval;
144 volatile unsigned int *a = addr;
145 unsigned long flags;
146
147 a += nr >> 5;
148 mask = 1 << (nr & 0x1f);
149 local_irq_save(flags);
150 retval = (mask & *a) != 0;
151 *a ^= mask;
152 local_irq_restore(flags);
153
154 return retval;
155}
156
157static __inline__ int __test_and_change_bit(int nr, volatile void * addr)
158{
159 int mask, retval;
160 volatile unsigned int *a = addr;
161
162 a += nr >> 5;
163 mask = 1 << (nr & 0x1f);
164 retval = (mask & *a) != 0;
165 *a ^= mask;
166
167 return retval;
168}
169
170static __inline__ int test_bit(int nr, const volatile void *addr)
171{
172 return 1UL & (((const volatile unsigned int *) addr)[nr >> 5] >> (nr & 31));
173}
174
175static __inline__ unsigned long ffz(unsigned long word)
176{
177 unsigned long result;
178
179 __asm__("1:\n\t"
180 "shlr %1\n\t"
181 "bt/s 1b\n\t"
182 " add #1, %0"
183 : "=r" (result), "=r" (word)
184 : "0" (~0L), "1" (word)
185 : "t");
186 return result;
187}
188
189/**
190 * __ffs - find first bit in word.
191 * @word: The word to search
192 *
193 * Undefined if no bit exists, so code should check against 0 first.
194 */
195static __inline__ unsigned long __ffs(unsigned long word)
196{
197 unsigned long result;
198
199 __asm__("1:\n\t"
200 "shlr %1\n\t"
201 "bf/s 1b\n\t"
202 " add #1, %0"
203 : "=r" (result), "=r" (word)
204 : "0" (~0L), "1" (word)
205 : "t");
206 return result;
207}
208
209/**
210 * find_next_bit - find the next set bit in a memory region
211 * @addr: The address to base the search on
212 * @offset: The bitnumber to start searching at
213 * @size: The maximum size to search
214 */
215static __inline__ unsigned long find_next_bit(const unsigned long *addr,
216 unsigned long size, unsigned long offset)
217{
218 unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
219 unsigned int result = offset & ~31UL;
220 unsigned int tmp;
221
222 if (offset >= size)
223 return size;
224 size -= result;
225 offset &= 31UL;
226 if (offset) {
227 tmp = *p++;
228 tmp &= ~0UL << offset;
229 if (size < 32)
230 goto found_first;
231 if (tmp)
232 goto found_middle;
233 size -= 32;
234 result += 32;
235 }
236 while (size >= 32) {
237 if ((tmp = *p++) != 0)
238 goto found_middle;
239 result += 32;
240 size -= 32;
241 }
242 if (!size)
243 return result;
244 tmp = *p;
245
246found_first:
247 tmp &= ~0UL >> (32 - size);
248 if (tmp == 0UL) /* Are any bits set? */
249 return result + size; /* Nope. */
250found_middle:
251 return result + __ffs(tmp);
252}
253
254/**
255 * find_first_bit - find the first set bit in a memory region
256 * @addr: The address to start the search at
257 * @size: The maximum size to search
258 *
259 * Returns the bit-number of the first set bit, not the number of the byte
260 * containing a bit.
261 */
262#define find_first_bit(addr, size) \
263 find_next_bit((addr), (size), 0)
264
265static __inline__ int find_next_zero_bit(const unsigned long *addr, int size, int offset)
266{
267 const unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
268 unsigned long result = offset & ~31UL;
269 unsigned long tmp;
270
271 if (offset >= size)
272 return size;
273 size -= result;
274 offset &= 31UL;
275 if (offset) {
276 tmp = *(p++);
277 tmp |= ~0UL >> (32-offset);
278 if (size < 32)
279 goto found_first;
280 if (~tmp)
281 goto found_middle;
282 size -= 32;
283 result += 32;
284 }
285 while (size & ~31UL) {
286 if (~(tmp = *(p++)))
287 goto found_middle;
288 result += 32;
289 size -= 32;
290 }
291 if (!size)
292 return result;
293 tmp = *p;
294
295found_first:
296 tmp |= ~0UL << size;
297found_middle:
298 return result + ffz(tmp);
299}
300
301#define find_first_zero_bit(addr, size) \
302 find_next_zero_bit((addr), (size), 0)
303
304/*
305 * ffs: find first bit set. This is defined the same way as
306 * the libc and compiler builtin ffs routines, therefore
307 * differs in spirit from the above ffz (man ffs).
308 */
309
310#define ffs(x) generic_ffs(x)
311
312/*
313 * hweightN: returns the hamming weight (i.e. the number
314 * of bits set) of a N-bit word
315 */
316
317#define hweight32(x) generic_hweight32(x)
318#define hweight16(x) generic_hweight16(x)
319#define hweight8(x) generic_hweight8(x)
320
321/*
322 * Every architecture must define this function. It's the fastest
323 * way of searching a 140-bit bitmap where the first 100 bits are
324 * unlikely to be set. It's guaranteed that at least one of the 140
325 * bits is cleared.
326 */
327
328static inline int sched_find_first_bit(const unsigned long *b)
329{
330 if (unlikely(b[0]))
331 return __ffs(b[0]);
332 if (unlikely(b[1]))
333 return __ffs(b[1]) + 32;
334 if (unlikely(b[2]))
335 return __ffs(b[2]) + 64;
336 if (b[3])
337 return __ffs(b[3]) + 96;
338 return __ffs(b[4]) + 128;
339}
340
341#ifdef __LITTLE_ENDIAN__
342#define ext2_set_bit(nr, addr) test_and_set_bit((nr), (addr))
343#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr), (addr))
344#define ext2_test_bit(nr, addr) test_bit((nr), (addr))
345#define ext2_find_first_zero_bit(addr, size) find_first_zero_bit((addr), (size))
346#define ext2_find_next_zero_bit(addr, size, offset) \
347 find_next_zero_bit((unsigned long *)(addr), (size), (offset))
348#else
349static __inline__ int ext2_set_bit(int nr, volatile void * addr)
350{
351 int mask, retval;
352 unsigned long flags;
353 volatile unsigned char *ADDR = (unsigned char *) addr;
354
355 ADDR += nr >> 3;
356 mask = 1 << (nr & 0x07);
357 local_irq_save(flags);
358 retval = (mask & *ADDR) != 0;
359 *ADDR |= mask;
360 local_irq_restore(flags);
361 return retval;
362}
363
364static __inline__ int ext2_clear_bit(int nr, volatile void * addr)
365{
366 int mask, retval;
367 unsigned long flags;
368 volatile unsigned char *ADDR = (unsigned char *) addr;
369
370 ADDR += nr >> 3;
371 mask = 1 << (nr & 0x07);
372 local_irq_save(flags);
373 retval = (mask & *ADDR) != 0;
374 *ADDR &= ~mask;
375 local_irq_restore(flags);
376 return retval;
377}
378
379static __inline__ int ext2_test_bit(int nr, const volatile void * addr)
380{
381 int mask;
382 const volatile unsigned char *ADDR = (const unsigned char *) addr;
383
384 ADDR += nr >> 3;
385 mask = 1 << (nr & 0x07);
386 return ((mask & *ADDR) != 0);
387}
388
389#define ext2_find_first_zero_bit(addr, size) \
390 ext2_find_next_zero_bit((addr), (size), 0)
391
392static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
393{
394 unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
395 unsigned long result = offset & ~31UL;
396 unsigned long tmp;
397
398 if (offset >= size)
399 return size;
400 size -= result;
401 offset &= 31UL;
402 if(offset) {
403 /* We hold the little endian value in tmp, but then the
404 * shift is illegal. So we could keep a big endian value
405 * in tmp, like this:
406 *
407 * tmp = __swab32(*(p++));
408 * tmp |= ~0UL >> (32-offset);
409 *
410 * but this would decrease preformance, so we change the
411 * shift:
412 */
413 tmp = *(p++);
414 tmp |= __swab32(~0UL >> (32-offset));
415 if(size < 32)
416 goto found_first;
417 if(~tmp)
418 goto found_middle;
419 size -= 32;
420 result += 32;
421 }
422 while(size & ~31UL) {
423 if(~(tmp = *(p++)))
424 goto found_middle;
425 result += 32;
426 size -= 32;
427 }
428 if(!size)
429 return result;
430 tmp = *p;
431
432found_first:
433 /* tmp is little endian, so we would have to swab the shift,
434 * see above. But then we have to swab tmp below for ffz, so
435 * we might as well do this here.
436 */
437 return result + ffz(__swab32(tmp) | (~0UL << size));
438found_middle:
439 return result + ffz(__swab32(tmp));
440}
441#endif
442
443#define ext2_set_bit_atomic(lock, nr, addr) \
444 ({ \
445 int ret; \
446 spin_lock(lock); \
447 ret = ext2_set_bit((nr), (addr)); \
448 spin_unlock(lock); \
449 ret; \
450 })
451
452#define ext2_clear_bit_atomic(lock, nr, addr) \
453 ({ \
454 int ret; \
455 spin_lock(lock); \
456 ret = ext2_clear_bit((nr), (addr)); \
457 spin_unlock(lock); \
458 ret; \
459 })
460
461/* Bitmap functions for the minix filesystem. */
462#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr)
463#define minix_set_bit(nr,addr) set_bit(nr,addr)
464#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr)
465#define minix_test_bit(nr,addr) test_bit(nr,addr)
466#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
467
468/*
469 * fls: find last bit set.
470 */
471
472#define fls(x) generic_fls(x)
473
474#endif /* __KERNEL__ */
475
476#endif /* __ASM_SH_BITOPS_H */
diff --git a/include/asm-sh/bug.h b/include/asm-sh/bug.h
new file mode 100644
index 000000000000..70172217140f
--- /dev/null
+++ b/include/asm-sh/bug.h
@@ -0,0 +1,17 @@
1#ifndef __ASM_SH_BUG_H
2#define __ASM_SH_BUG_H
3
4#include <linux/config.h>
5
6/*
7 * Tell the user there is some problem.
8 */
9#define BUG() do { \
10 printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
11 *(volatile int *)0 = 0; \
12} while (0)
13
14#define HAVE_ARCH_BUG
15#include <asm-generic/bug.h>
16
17#endif
diff --git a/include/asm-sh/bugs.h b/include/asm-sh/bugs.h
new file mode 100644
index 000000000000..a6de3d06a3d9
--- /dev/null
+++ b/include/asm-sh/bugs.h
@@ -0,0 +1,50 @@
1#ifndef __ASM_SH_BUGS_H
2#define __ASM_SH_BUGS_H
3
4/*
5 * This is included by init/main.c to check for architecture-dependent bugs.
6 *
7 * Needs:
8 * void check_bugs(void);
9 */
10
11/*
12 * I don't know of any Super-H bugs yet.
13 */
14
15#include <asm/processor.h>
16
17static void __init check_bugs(void)
18{
19 extern char *get_cpu_subtype(void);
20 extern unsigned long loops_per_jiffy;
21 char *p= &system_utsname.machine[2]; /* "sh" */
22
23 cpu_data->loops_per_jiffy = loops_per_jiffy;
24
25 switch (cpu_data->type) {
26 case CPU_SH7604:
27 *p++ = '2';
28 break;
29 case CPU_SH7705 ... CPU_SH7300:
30 *p++ = '3';
31 break;
32 case CPU_SH7750 ... CPU_SH4_501:
33 *p++ = '4';
34 break;
35 default:
36 *p++ = '?';
37 *p++ = '!';
38 break;
39 }
40
41 printk("CPU: %s\n", get_cpu_subtype());
42
43#ifndef __LITTLE_ENDIAN__
44 /* 'eb' means 'Endian Big' */
45 *p++ = 'e';
46 *p++ = 'b';
47#endif
48 *p = '\0';
49}
50#endif /* __ASM_SH_BUGS_H */
diff --git a/include/asm-sh/bus-sh.h b/include/asm-sh/bus-sh.h
new file mode 100644
index 000000000000..f782a33a98fa
--- /dev/null
+++ b/include/asm-sh/bus-sh.h
@@ -0,0 +1,65 @@
1/*
2 * include/asm-sh/bus-sh.h
3 *
4 * Copyright (C) 2004 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_SH_BUS_SH_H
11#define __ASM_SH_BUS_SH_H
12
13extern struct bus_type sh_bus_types[];
14
15struct sh_dev {
16 struct device dev;
17 char *name;
18 unsigned int dev_id;
19 unsigned int bus_id;
20 struct resource res;
21 void *mapbase;
22 unsigned int irq[6];
23 u64 *dma_mask;
24};
25
26#define to_sh_dev(d) container_of((d), struct sh_dev, dev)
27
28#define sh_get_drvdata(d) dev_get_drvdata(&(d)->dev)
29#define sh_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, (p))
30
31struct sh_driver {
32 struct device_driver drv;
33 unsigned int dev_id;
34 unsigned int bus_id;
35 int (*probe)(struct sh_dev *);
36 int (*remove)(struct sh_dev *);
37 int (*suspend)(struct sh_dev *, u32);
38 int (*resume)(struct sh_dev *);
39};
40
41#define to_sh_driver(d) container_of((d), struct sh_driver, drv)
42#define sh_name(d) ((d)->dev.driver->name)
43
44/*
45 * Device ID numbers for bus types
46 */
47enum {
48 SH_DEV_ID_USB_OHCI,
49};
50
51#define SH_NR_BUSES 1
52#define SH_BUS_NAME_VIRT "shbus"
53
54enum {
55 SH_BUS_VIRT,
56};
57
58/* arch/sh/kernel/cpu/bus.c */
59extern int sh_device_register(struct sh_dev *dev);
60extern void sh_device_unregister(struct sh_dev *dev);
61extern int sh_driver_register(struct sh_driver *drv);
62extern void sh_driver_unregister(struct sh_driver *drv);
63
64#endif /* __ASM_SH_BUS_SH_H */
65
diff --git a/include/asm-sh/byteorder.h b/include/asm-sh/byteorder.h
new file mode 100644
index 000000000000..bff2b1382e01
--- /dev/null
+++ b/include/asm-sh/byteorder.h
@@ -0,0 +1,56 @@
1#ifndef __ASM_SH_BYTEORDER_H
2#define __ASM_SH_BYTEORDER_H
3
4/*
5 * Copyright (C) 1999 Niibe Yutaka
6 */
7
8#include <asm/types.h>
9#include <linux/compiler.h>
10
11static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
12{
13 __asm__("swap.b %0, %0\n\t"
14 "swap.w %0, %0\n\t"
15 "swap.b %0, %0"
16 : "=r" (x)
17 : "0" (x));
18 return x;
19}
20
21static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
22{
23 __asm__("swap.b %0, %0"
24 : "=r" (x)
25 : "0" (x));
26 return x;
27}
28
29static inline __u64 ___arch__swab64(__u64 val)
30{
31 union {
32 struct { __u32 a,b; } s;
33 __u64 u;
34 } v, w;
35 v.u = val;
36 w.s.b = ___arch__swab32(v.s.a);
37 w.s.a = ___arch__swab32(v.s.b);
38 return w.u;
39}
40
41#define __arch__swab64(x) ___arch__swab64(x)
42#define __arch__swab32(x) ___arch__swab32(x)
43#define __arch__swab16(x) ___arch__swab16(x)
44
45#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
46# define __BYTEORDER_HAS_U64__
47# define __SWAB_64_THRU_32__
48#endif
49
50#ifdef __LITTLE_ENDIAN__
51#include <linux/byteorder/little_endian.h>
52#else
53#include <linux/byteorder/big_endian.h>
54#endif
55
56#endif /* __ASM_SH_BYTEORDER_H */
diff --git a/include/asm-sh/cache.h b/include/asm-sh/cache.h
new file mode 100644
index 000000000000..9b4dd6d8212e
--- /dev/null
+++ b/include/asm-sh/cache.h
@@ -0,0 +1,48 @@
1/* $Id: cache.h,v 1.6 2004/03/11 18:08:05 lethal Exp $
2 *
3 * include/asm-sh/cache.h
4 *
5 * Copyright 1999 (C) Niibe Yutaka
6 * Copyright 2002, 2003 (C) Paul Mundt
7 */
8#ifndef __ASM_SH_CACHE_H
9#define __ASM_SH_CACHE_H
10#ifdef __KERNEL__
11
12#include <asm/cpu/cache.h>
13#include <asm/cpu/cacheflush.h>
14
15#define SH_CACHE_VALID 1
16#define SH_CACHE_UPDATED 2
17#define SH_CACHE_COMBINED 4
18#define SH_CACHE_ASSOC 8
19
20#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
21#define SMP_CACHE_BYTES L1_CACHE_BYTES
22
23#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
24
25#define L1_CACHE_SHIFT_MAX 5 /* largest L1 which this arch supports */
26
27struct cache_info {
28 unsigned int ways;
29 unsigned int sets;
30 unsigned int linesz;
31
32 unsigned int way_incr;
33
34 unsigned int entry_shift;
35 unsigned int entry_mask;
36
37 unsigned long flags;
38};
39
40/* Flush (write-back only) a region (smaller than a page) */
41extern void __flush_wback_region(void *start, int size);
42/* Flush (write-back & invalidate) a region (smaller than a page) */
43extern void __flush_purge_region(void *start, int size);
44/* Flush (invalidate only) a region (smaller than a page) */
45extern void __flush_invalidate_region(void *start, int size);
46
47#endif /* __KERNEL__ */
48#endif /* __ASM_SH_CACHE_H */
diff --git a/include/asm-sh/cacheflush.h b/include/asm-sh/cacheflush.h
new file mode 100644
index 000000000000..9dfb33edb008
--- /dev/null
+++ b/include/asm-sh/cacheflush.h
@@ -0,0 +1,31 @@
1#ifndef __ASM_SH_CACHEFLUSH_H
2#define __ASM_SH_CACHEFLUSH_H
3#ifdef __KERNEL__
4
5#include <asm/cpu/cacheflush.h>
6
7/* Flush (write-back only) a region (smaller than a page) */
8extern void __flush_wback_region(void *start, int size);
9/* Flush (write-back & invalidate) a region (smaller than a page) */
10extern void __flush_purge_region(void *start, int size);
11/* Flush (invalidate only) a region (smaller than a page) */
12extern void __flush_invalidate_region(void *start, int size);
13
14#define flush_cache_vmap(start, end) flush_cache_all()
15#define flush_cache_vunmap(start, end) flush_cache_all()
16
17#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
18 do { \
19 flush_cache_page(vma, vaddr, page_to_pfn(page));\
20 memcpy(dst, src, len); \
21 flush_icache_user_range(vma, page, vaddr, len); \
22 } while (0)
23
24#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
25 do { \
26 flush_cache_page(vma, vaddr, page_to_pfn(page));\
27 memcpy(dst, src, len); \
28 } while (0)
29
30#endif /* __KERNEL__ */
31#endif /* __ASM_SH_CACHEFLUSH_H */
diff --git a/include/asm-sh/cat68701/io.h b/include/asm-sh/cat68701/io.h
new file mode 100644
index 000000000000..753b8466ad11
--- /dev/null
+++ b/include/asm-sh/cat68701/io.h
@@ -0,0 +1,22 @@
1/*
2 * include/asm-sh/io_cat68701.h
3 *
4 * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
5 * 2001 Yutarou Ebihar (ebihara@si-linux.com)
6 *
7 * May be copied or modified under the terms of the GNU General Public
8 * License. See linux/COPYING for more information.
9 *
10 * IO functions for an AONE Corp. CAT-68701 SH7708 Borad
11 */
12
13#ifndef _ASM_SH_IO_CAT68701_H
14#define _ASM_SH_IO_CAT68701_H
15
16extern unsigned long cat68701_isa_port2addr(unsigned long offset);
17extern int cat68701_irq_demux(int irq);
18
19extern void init_cat68701_IRQ(void);
20extern void heartbeat_cat68701(void);
21
22#endif /* _ASM_SH_IO_CAT68701_H */
diff --git a/include/asm-sh/checksum.h b/include/asm-sh/checksum.h
new file mode 100644
index 000000000000..5113c7f8a739
--- /dev/null
+++ b/include/asm-sh/checksum.h
@@ -0,0 +1,216 @@
1#ifndef __ASM_SH_CHECKSUM_H
2#define __ASM_SH_CHECKSUM_H
3
4/*
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * Copyright (C) 1999 by Kaz Kojima & Niibe Yutaka
10 */
11
12#include <linux/config.h>
13#include <linux/in6.h>
14
15/*
16 * computes the checksum of a memory block at buff, length len,
17 * and adds in "sum" (32-bit)
18 *
19 * returns a 32-bit number suitable for feeding into itself
20 * or csum_tcpudp_magic
21 *
22 * this function must be called with even lengths, except
23 * for the last fragment, which may be odd
24 *
25 * it's best to have buff aligned on a 32-bit boundary
26 */
27asmlinkage unsigned int csum_partial(const unsigned char * buff, int len, unsigned int sum);
28
29/*
30 * the same as csum_partial, but copies from src while it
31 * checksums, and handles user-space pointer exceptions correctly, when needed.
32 *
33 * here even more important to align src and dst on a 32-bit (or even
34 * better 64-bit) boundary
35 */
36
37asmlinkage unsigned int csum_partial_copy_generic(const unsigned char *src, unsigned char *dst,
38 int len, int sum, int *src_err_ptr, int *dst_err_ptr);
39
40/*
41 * Note: when you get a NULL pointer exception here this means someone
42 * passed in an incorrect kernel address to one of these functions.
43 *
44 * If you use these functions directly please don't forget the
45 * verify_area().
46 */
47static __inline__
48unsigned int csum_partial_copy_nocheck (const unsigned char *src, unsigned char *dst,
49 int len, int sum)
50{
51 return csum_partial_copy_generic ( src, dst, len, sum, NULL, NULL);
52}
53
54static __inline__
55unsigned int csum_partial_copy_from_user (const unsigned char *src, unsigned char *dst,
56 int len, int sum, int *err_ptr)
57{
58 return csum_partial_copy_generic ( src, dst, len, sum, err_ptr, NULL);
59}
60
61/*
62 * Fold a partial checksum
63 */
64
65static __inline__ unsigned int csum_fold(unsigned int sum)
66{
67 unsigned int __dummy;
68 __asm__("swap.w %0, %1\n\t"
69 "extu.w %0, %0\n\t"
70 "extu.w %1, %1\n\t"
71 "add %1, %0\n\t"
72 "swap.w %0, %1\n\t"
73 "add %1, %0\n\t"
74 "not %0, %0\n\t"
75 : "=r" (sum), "=&r" (__dummy)
76 : "0" (sum)
77 : "t");
78 return sum;
79}
80
81/*
82 * This is a version of ip_compute_csum() optimized for IP headers,
83 * which always checksum on 4 octet boundaries.
84 *
85 * i386 version by Jorge Cwik <jorge@laser.satlink.net>, adapted
86 * for linux by * Arnt Gulbrandsen.
87 */
88static __inline__ unsigned short ip_fast_csum(unsigned char * iph, unsigned int ihl)
89{
90 unsigned int sum, __dummy0, __dummy1;
91
92 __asm__ __volatile__(
93 "mov.l @%1+, %0\n\t"
94 "mov.l @%1+, %3\n\t"
95 "add #-2, %2\n\t"
96 "clrt\n\t"
97 "1:\t"
98 "addc %3, %0\n\t"
99 "movt %4\n\t"
100 "mov.l @%1+, %3\n\t"
101 "dt %2\n\t"
102 "bf/s 1b\n\t"
103 " cmp/eq #1, %4\n\t"
104 "addc %3, %0\n\t"
105 "addc %2, %0" /* Here %2 is 0, add carry-bit */
106 /* Since the input registers which are loaded with iph and ihl
107 are modified, we must also specify them as outputs, or gcc
108 will assume they contain their original values. */
109 : "=r" (sum), "=r" (iph), "=r" (ihl), "=&r" (__dummy0), "=&z" (__dummy1)
110 : "1" (iph), "2" (ihl)
111 : "t");
112
113 return csum_fold(sum);
114}
115
116static __inline__ unsigned long csum_tcpudp_nofold(unsigned long saddr,
117 unsigned long daddr,
118 unsigned short len,
119 unsigned short proto,
120 unsigned int sum)
121{
122#ifdef __LITTLE_ENDIAN__
123 unsigned long len_proto = (ntohs(len)<<16)+proto*256;
124#else
125 unsigned long len_proto = (proto<<16)+len;
126#endif
127 __asm__("clrt\n\t"
128 "addc %0, %1\n\t"
129 "addc %2, %1\n\t"
130 "addc %3, %1\n\t"
131 "movt %0\n\t"
132 "add %1, %0"
133 : "=r" (sum), "=r" (len_proto)
134 : "r" (daddr), "r" (saddr), "1" (len_proto), "0" (sum)
135 : "t");
136 return sum;
137}
138
139/*
140 * computes the checksum of the TCP/UDP pseudo-header
141 * returns a 16-bit checksum, already complemented
142 */
143static __inline__ unsigned short int csum_tcpudp_magic(unsigned long saddr,
144 unsigned long daddr,
145 unsigned short len,
146 unsigned short proto,
147 unsigned int sum)
148{
149 return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
150}
151
152/*
153 * this routine is used for miscellaneous IP-like checksums, mainly
154 * in icmp.c
155 */
156
157static __inline__ unsigned short ip_compute_csum(unsigned char * buff, int len)
158{
159 return csum_fold (csum_partial(buff, len, 0));
160}
161
162#define _HAVE_ARCH_IPV6_CSUM
163static __inline__ unsigned short int csum_ipv6_magic(struct in6_addr *saddr,
164 struct in6_addr *daddr,
165 __u32 len,
166 unsigned short proto,
167 unsigned int sum)
168{
169 unsigned int __dummy;
170 __asm__("clrt\n\t"
171 "mov.l @(0,%2), %1\n\t"
172 "addc %1, %0\n\t"
173 "mov.l @(4,%2), %1\n\t"
174 "addc %1, %0\n\t"
175 "mov.l @(8,%2), %1\n\t"
176 "addc %1, %0\n\t"
177 "mov.l @(12,%2), %1\n\t"
178 "addc %1, %0\n\t"
179 "mov.l @(0,%3), %1\n\t"
180 "addc %1, %0\n\t"
181 "mov.l @(4,%3), %1\n\t"
182 "addc %1, %0\n\t"
183 "mov.l @(8,%3), %1\n\t"
184 "addc %1, %0\n\t"
185 "mov.l @(12,%3), %1\n\t"
186 "addc %1, %0\n\t"
187 "addc %4, %0\n\t"
188 "addc %5, %0\n\t"
189 "movt %1\n\t"
190 "add %1, %0\n"
191 : "=r" (sum), "=&r" (__dummy)
192 : "r" (saddr), "r" (daddr),
193 "r" (htonl(len)), "r" (htonl(proto)), "0" (sum)
194 : "t");
195
196 return csum_fold(sum);
197}
198
199/*
200 * Copy and checksum to user
201 */
202#define HAVE_CSUM_COPY_USER
203static __inline__ unsigned int csum_and_copy_to_user (const unsigned char *src,
204 unsigned char __user *dst,
205 int len, int sum,
206 int *err_ptr)
207{
208 if (access_ok(VERIFY_WRITE, dst, len))
209 return csum_partial_copy_generic(src, dst, len, sum, NULL, err_ptr);
210
211 if (len)
212 *err_ptr = -EFAULT;
213
214 return -1; /* invalid checksum */
215}
216#endif /* __ASM_SH_CHECKSUM_H */
diff --git a/include/asm-sh/cpu-sh2/addrspace.h b/include/asm-sh/cpu-sh2/addrspace.h
new file mode 100644
index 000000000000..8706c903c5a0
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/addrspace.h
@@ -0,0 +1,16 @@
1/*
2 * Definitions for the address spaces of the SH-2 CPUs.
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_ADDRSPACE_H
11#define __ASM_CPU_SH2_ADDRSPACE_H
12
13/* Should fill here */
14
15#endif /* __ASM_CPU_SH2_ADDRSPACE_H */
16
diff --git a/include/asm-sh/cpu-sh2/cache.h b/include/asm-sh/cpu-sh2/cache.h
new file mode 100644
index 000000000000..cd96402e8562
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/cache.h
@@ -0,0 +1,31 @@
1/*
2 * include/asm-sh/cpu-sh2/cache.h
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_CACHE_H
11#define __ASM_CPU_SH2_CACHE_H
12
13#define L1_CACHE_SHIFT 4
14
15#define CCR 0xfffffe92 /* Address of Cache Control Register */
16
17#define CCR_CACHE_CE 0x01 /* Cache enable */
18#define CCR_CACHE_ID 0x02 /* Instruction Replacement disable */
19#define CCR_CACHE_OD 0x04 /* Data Replacement disable */
20#define CCR_CACHE_TW 0x08 /* Two-way mode */
21#define CCR_CACHE_CP 0x10 /* Cache purge */
22
23#define CACHE_OC_ADDRESS_ARRAY 0x60000000
24
25#define CCR_CACHE_ENABLE CCR_CACHE_CE
26#define CCR_CACHE_INVALIDATE CCR_CACHE_CP
27#define CCR_CACHE_ORA CCR_CACHE_TW
28#define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */
29
30#endif /* __ASM_CPU_SH2_CACHE_H */
31
diff --git a/include/asm-sh/cpu-sh2/cacheflush.h b/include/asm-sh/cpu-sh2/cacheflush.h
new file mode 100644
index 000000000000..f556fa80ea97
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/cacheflush.h
@@ -0,0 +1,42 @@
1/*
2 * include/asm-sh/cpu-sh2/cacheflush.h
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_CACHEFLUSH_H
11#define __ASM_CPU_SH2_CACHEFLUSH_H
12
13/*
14 * Cache flushing:
15 *
16 * - flush_cache_all() flushes entire cache
17 * - flush_cache_mm(mm) flushes the specified mm context's cache lines
18 * - flush_cache_page(mm, vmaddr, pfn) flushes a single page
19 * - flush_cache_range(vma, start, end) flushes a range of pages
20 *
21 * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
22 * - flush_icache_range(start, end) flushes(invalidates) a range for icache
23 * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
24 *
25 * Caches are indexed (effectively) by physical address on SH-2, so
26 * we don't need them.
27 */
28#define flush_cache_all() do { } while (0)
29#define flush_cache_mm(mm) do { } while (0)
30#define flush_cache_range(vma, start, end) do { } while (0)
31#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
32#define flush_dcache_page(page) do { } while (0)
33#define flush_dcache_mmap_lock(mapping) do { } while (0)
34#define flush_dcache_mmap_unlock(mapping) do { } while (0)
35#define flush_icache_range(start, end) do { } while (0)
36#define flush_icache_page(vma,pg) do { } while (0)
37#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
38#define flush_cache_sigtramp(vaddr) do { } while (0)
39
40#define p3_cache_init() do { } while (0)
41#endif /* __ASM_CPU_SH2_CACHEFLUSH_H */
42
diff --git a/include/asm-sh/cpu-sh2/dma.h b/include/asm-sh/cpu-sh2/dma.h
new file mode 100644
index 000000000000..d66b43cdc637
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/dma.h
@@ -0,0 +1,23 @@
1/*
2 * Definitions for the SH-2 DMAC.
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_DMA_H
11#define __ASM_CPU_SH2_DMA_H
12
13#define SH_MAX_DMA_CHANNELS 2
14
15#define SAR ((unsigned long[]){ 0xffffff80, 0xffffff90 })
16#define DAR ((unsigned long[]){ 0xffffff84, 0xffffff94 })
17#define DMATCR ((unsigned long[]){ 0xffffff88, 0xffffff98 })
18#define CHCR ((unsigned long[]){ 0xfffffffc, 0xffffff9c })
19
20#define DMAOR 0xffffffb0
21
22#endif /* __ASM_CPU_SH2_DMA_H */
23
diff --git a/include/asm-sh/cpu-sh2/shmparam.h b/include/asm-sh/cpu-sh2/shmparam.h
new file mode 100644
index 000000000000..817c1821ee4b
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/shmparam.h
@@ -0,0 +1,16 @@
1/*
2 * include/asm-sh/cpu-sh2/shmparam.h
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_SHMPARAM_H
11#define __ASM_CPU_SH2_SHMPARAM_H
12
13#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
14
15#endif /* __ASM_CPU_SH2_SHMPARAM_H */
16
diff --git a/include/asm-sh/cpu-sh2/sigcontext.h b/include/asm-sh/cpu-sh2/sigcontext.h
new file mode 100644
index 000000000000..fe5c15dd6e87
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/sigcontext.h
@@ -0,0 +1,17 @@
1#ifndef __ASM_CPU_SH2_SIGCONTEXT_H
2#define __ASM_CPU_SH2_SIGCONTEXT_H
3
4struct sigcontext {
5 unsigned long oldmask;
6
7 /* CPU registers */
8 unsigned long sc_regs[16];
9 unsigned long sc_pc;
10 unsigned long sc_pr;
11 unsigned long sc_sr;
12 unsigned long sc_gbr;
13 unsigned long sc_mach;
14 unsigned long sc_macl;
15};
16
17#endif /* __ASM_CPU_SH2_SIGCONTEXT_H */
diff --git a/include/asm-sh/cpu-sh2/ubc.h b/include/asm-sh/cpu-sh2/ubc.h
new file mode 100644
index 000000000000..ba0e87f19c7a
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/ubc.h
@@ -0,0 +1,32 @@
1/*
2 * include/asm-sh/cpu-sh2/ubc.h
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_UBC_H
11#define __ASM_CPU_SH2_UBC_H
12
13#define UBC_BARA 0xffffff40
14#define UBC_BAMRA 0xffffff44
15#define UBC_BBRA 0xffffff48
16#define UBC_BARB 0xffffff60
17#define UBC_BAMRB 0xffffff64
18#define UBC_BBRB 0xffffff68
19#define UBC_BDRB 0xffffff70
20#define UBC_BDMRB 0xffffff74
21#define UBC_BRCR 0xffffff78
22
23/*
24 * We don't have any ASID changes to make in the UBC on the SH-2.
25 *
26 * Make these purposely invalid to track misuse.
27 */
28#define UBC_BASRA 0x00000000
29#define UBC_BASRB 0x00000000
30
31#endif /* __ASM_CPU_SH2_UBC_H */
32
diff --git a/include/asm-sh/cpu-sh2/watchdog.h b/include/asm-sh/cpu-sh2/watchdog.h
new file mode 100644
index 000000000000..393161c9c6d0
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/watchdog.h
@@ -0,0 +1,69 @@
1/*
2 * include/asm-sh/cpu-sh2/watchdog.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_WATCHDOG_H
11#define __ASM_CPU_SH2_WATCHDOG_H
12
13/*
14 * More SH-2 brilliance .. its not good enough that we can't read
15 * and write the same sizes to WTCNT, now we have to read and write
16 * with different sizes at different addresses for WTCNT _and_ RSTCSR.
17 *
18 * At least on the bright side no one has managed to screw over WTCSR
19 * in this fashion .. yet.
20 */
21/* Register definitions */
22#define WTCNT 0xfffffe80
23#define WTCSR 0xfffffe80
24#define RSTCSR 0xfffffe82
25
26#define WTCNT_R (WTCNT + 1)
27#define RSTCSR_R (RSTCSR + 1)
28
29/* Bit definitions */
30#define WTCSR_IOVF 0x80
31#define WTCSR_WT 0x40
32#define WTCSR_TME 0x20
33#define WTCSR_RSTS 0x00
34
35#define RSTCSR_RSTS 0x20
36
37/**
38 * sh_wdt_read_rstcsr - Read from Reset Control/Status Register
39 *
40 * Reads back the RSTCSR value.
41 */
42static inline __u8 sh_wdt_read_rstcsr(void)
43{
44 /*
45 * Same read/write brain-damage as for WTCNT here..
46 */
47 return ctrl_inb(RSTCSR_R);
48}
49
50/**
51 * sh_wdt_write_csr - Write to Reset Control/Status Register
52 *
53 * @val: Value to write
54 *
55 * Writes the given value @val to the lower byte of the control/status
56 * register. The upper byte is set manually on each write.
57 */
58static inline void sh_wdt_write_rstcsr(__u8 val)
59{
60 /*
61 * Note: Due to the brain-damaged nature of this register,
62 * we can't presently touch the WOVF bit, since the upper byte
63 * has to be swapped for this. So just leave it alone..
64 */
65 ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, RSTCSR);
66}
67
68#endif /* __ASM_CPU_SH2_WATCHDOG_H */
69
diff --git a/include/asm-sh/cpu-sh3/adc.h b/include/asm-sh/cpu-sh3/adc.h
new file mode 100644
index 000000000000..b289e3ca19a6
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/adc.h
@@ -0,0 +1,28 @@
1#ifndef __ASM_CPU_SH3_ADC_H
2#define __ASM_CPU_SH3_ADC_H
3
4/*
5 * Copyright (C) 2004 Andriy Skulysh
6 */
7
8
9#define ADDRAH 0xa4000080
10#define ADDRAL 0xa4000082
11#define ADDRBH 0xa4000084
12#define ADDRBL 0xa4000086
13#define ADDRCH 0xa4000088
14#define ADDRCL 0xa400008a
15#define ADDRDH 0xa400008c
16#define ADDRDL 0xa400008e
17#define ADCSR 0xa4000090
18
19#define ADCSR_ADF 0x80
20#define ADCSR_ADIE 0x40
21#define ADCSR_ADST 0x20
22#define ADCSR_MULTI 0x10
23#define ADCSR_CKS 0x08
24#define ADCSR_CH_MASK 0x07
25
26#define ADCR 0xa4000092
27
28#endif /* __ASM_CPU_SH3_ADC_H */
diff --git a/include/asm-sh/cpu-sh3/addrspace.h b/include/asm-sh/cpu-sh3/addrspace.h
new file mode 100644
index 000000000000..872e9e1b548c
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/addrspace.h
@@ -0,0 +1,16 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999 by Kaz Kojima
7 *
8 * Defitions for the address spaces of the SH-3 CPUs.
9 */
10#ifndef __ASM_CPU_SH3_ADDRSPACE_H
11#define __ASM_CPU_SH3_ADDRSPACE_H
12
13/* Should fill here */
14
15#endif /* __ASM_CPU_SH3_ADDRSPACE_H */
16
diff --git a/include/asm-sh/cpu-sh3/cache.h b/include/asm-sh/cpu-sh3/cache.h
new file mode 100644
index 000000000000..406aa8d9b947
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/cache.h
@@ -0,0 +1,37 @@
1/*
2 * include/asm-sh/cpu-sh3/cache.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_CACHE_H
11#define __ASM_CPU_SH3_CACHE_H
12
13#define L1_CACHE_SHIFT 4
14
15#define CCR 0xffffffec /* Address of Cache Control Register */
16
17#define CCR_CACHE_CE 0x01 /* Cache Enable */
18#define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */
19#define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */
20#define CCR_CACHE_CF 0x08 /* Cache Flush */
21#define CCR_CACHE_ORA 0x20 /* RAM mode */
22
23#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
24#define CACHE_PHYSADDR_MASK 0x1ffffc00
25
26#define CCR_CACHE_ENABLE CCR_CACHE_CE
27#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
28
29#if defined(CONFIG_CPU_SUBTYPE_SH7705)
30#define CCR3 0xa40000b4
31#define CCR_CACHE_16KB 0x00010000
32#define CCR_CACHE_32KB 0x00020000
33#endif
34
35
36#endif /* __ASM_CPU_SH3_CACHE_H */
37
diff --git a/include/asm-sh/cpu-sh3/cacheflush.h b/include/asm-sh/cpu-sh3/cacheflush.h
new file mode 100644
index 000000000000..f51aed00c68f
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/cacheflush.h
@@ -0,0 +1,87 @@
1/*
2 * include/asm-sh/cpu-sh3/cacheflush.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_CACHEFLUSH_H
11#define __ASM_CPU_SH3_CACHEFLUSH_H
12
13/*
14 * Cache flushing:
15 *
16 * - flush_cache_all() flushes entire cache
17 * - flush_cache_mm(mm) flushes the specified mm context's cache lines
18 * - flush_cache_page(mm, vmaddr, pfn) flushes a single page
19 * - flush_cache_range(vma, start, end) flushes a range of pages
20 *
21 * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
22 * - flush_icache_range(start, end) flushes(invalidates) a range for icache
23 * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
24 *
25 * Caches are indexed (effectively) by physical address on SH-3, so
26 * we don't need them.
27 */
28
29#if defined(CONFIG_SH7705_CACHE_32KB)
30
31/* SH7705 is an SH3 processor with 32KB cache. This has alias issues like the
32 * SH4. Unlike the SH4 this is a unified cache so we need to do some work
33 * in mmap when 'exec'ing a new binary
34 */
35 /* 32KB cache, 4kb PAGE sizes need to check bit 12 */
36#define CACHE_ALIAS 0x00001000
37
38struct page;
39struct mm_struct;
40struct vm_area_struct;
41
42extern void flush_cache_all(void);
43extern void flush_cache_mm(struct mm_struct *mm);
44extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
45 unsigned long end);
46extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
47extern void flush_dcache_page(struct page *pg);
48extern void flush_icache_range(unsigned long start, unsigned long end);
49extern void flush_icache_page(struct vm_area_struct *vma, struct page *page);
50
51#define flush_dcache_mmap_lock(mapping) do { } while (0)
52#define flush_dcache_mmap_unlock(mapping) do { } while (0)
53
54/* SH3 has unified cache so no special action needed here */
55#define flush_cache_sigtramp(vaddr) do { } while (0)
56#define flush_page_to_ram(page) do { } while (0)
57#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
58
59#define p3_cache_init() do { } while (0)
60
61#define PG_mapped PG_arch_1
62
63/* We provide our own get_unmapped_area to avoid cache alias issue */
64#define HAVE_ARCH_UNMAPPED_AREA
65
66#else
67
68#define flush_cache_all() do { } while (0)
69#define flush_cache_mm(mm) do { } while (0)
70#define flush_cache_range(vma, start, end) do { } while (0)
71#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
72#define flush_dcache_page(page) do { } while (0)
73#define flush_dcache_mmap_lock(mapping) do { } while (0)
74#define flush_dcache_mmap_unlock(mapping) do { } while (0)
75#define flush_icache_range(start, end) do { } while (0)
76#define flush_icache_page(vma,pg) do { } while (0)
77#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
78#define flush_cache_sigtramp(vaddr) do { } while (0)
79
80#define p3_cache_init() do { } while (0)
81
82#define HAVE_ARCH_UNMAPPED_AREA
83
84#endif
85
86#endif /* __ASM_CPU_SH3_CACHEFLUSH_H */
87
diff --git a/include/asm-sh/cpu-sh3/dac.h b/include/asm-sh/cpu-sh3/dac.h
new file mode 100644
index 000000000000..05fda8316ebc
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/dac.h
@@ -0,0 +1,41 @@
1#ifndef __ASM_CPU_SH3_DAC_H
2#define __ASM_CPU_SH3_DAC_H
3
4/*
5 * Copyright (C) 2003 Andriy Skulysh
6 */
7
8
9#define DADR0 0xa40000a0
10#define DADR1 0xa40000a2
11#define DACR 0xa40000a4
12#define DACR_DAOE1 0x80
13#define DACR_DAOE0 0x40
14#define DACR_DAE 0x20
15
16
17static __inline__ void sh_dac_enable(int channel)
18{
19 unsigned char v;
20 v = ctrl_inb(DACR);
21 if(channel) v |= DACR_DAOE1;
22 else v |= DACR_DAOE0;
23 ctrl_outb(v,DACR);
24}
25
26static __inline__ void sh_dac_disable(int channel)
27{
28 unsigned char v;
29 v = ctrl_inb(DACR);
30 if(channel) v &= ~DACR_DAOE1;
31 else v &= ~DACR_DAOE0;
32 ctrl_outb(v,DACR);
33}
34
35static __inline__ void sh_dac_output(u8 value, int channel)
36{
37 if(channel) ctrl_outb(value,DADR1);
38 else ctrl_outb(value,DADR0);
39}
40
41#endif /* __ASM_CPU_SH3_DAC_H */
diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h
new file mode 100644
index 000000000000..b972e715f9ee
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/dma.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_CPU_SH3_DMA_H
2#define __ASM_CPU_SH3_DMA_H
3
4#define SH_DMAC_BASE 0xa4000020
5
6#endif /* __ASM_CPU_SH3_DMA_H */
7
diff --git a/include/asm-sh/cpu-sh3/freq.h b/include/asm-sh/cpu-sh3/freq.h
new file mode 100644
index 000000000000..b61b6e331df0
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/freq.h
@@ -0,0 +1,22 @@
1/*
2 * include/asm-sh/cpu-sh3/freq.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_FREQ_H
11#define __ASM_CPU_SH3_FREQ_H
12
13#if defined(CONFIG_CPU_SUBTYPE_SH7300)
14#define FRQCR 0xa415ff80
15#else
16#define FRQCR 0xffffff80
17#endif
18#define MIN_DIVISOR_NR 0
19#define MAX_DIVISOR_NR 4
20
21#endif /* __ASM_CPU_SH3_FREQ_H */
22
diff --git a/include/asm-sh/cpu-sh3/mmu_context.h b/include/asm-sh/cpu-sh3/mmu_context.h
new file mode 100644
index 000000000000..5cfaa6bcf1ed
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/mmu_context.h
@@ -0,0 +1,28 @@
1/*
2 * include/asm-sh/cpu-sh3/mmu_context.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_MMU_CONTEXT_H
11#define __ASM_CPU_SH3_MMU_CONTEXT_H
12
13#define MMU_PTEH 0xFFFFFFF0 /* Page table entry register HIGH */
14#define MMU_PTEL 0xFFFFFFF4 /* Page table entry register LOW */
15#define MMU_TTB 0xFFFFFFF8 /* Translation table base register */
16#define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */
17
18#define MMUCR 0xFFFFFFE0 /* MMU Control Register */
19
20#define MMU_TLB_ADDRESS_ARRAY 0xF2000000
21#define MMU_PAGE_ASSOC_BIT 0x80
22
23#define MMU_NTLB_ENTRIES 128 /* for 7708 */
24#define MMU_NTLB_WAYS 4
25#define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */
26
27#endif /* __ASM_CPU_SH3_MMU_CONTEXT_H */
28
diff --git a/include/asm-sh/cpu-sh3/rtc.h b/include/asm-sh/cpu-sh3/rtc.h
new file mode 100644
index 000000000000..2d926671115a
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/rtc.h
@@ -0,0 +1,25 @@
1#ifndef __ASM_CPU_SH3_RTC_H
2#define __ASM_CPU_SH3_RTC_H
3
4/* SH-3 RTC */
5#define R64CNT 0xfffffec0
6#define RSECCNT 0xfffffec2
7#define RMINCNT 0xfffffec4
8#define RHRCNT 0xfffffec6
9#define RWKCNT 0xfffffec8
10#define RDAYCNT 0xfffffeca
11#define RMONCNT 0xfffffecc
12#define RYRCNT 0xfffffece
13#define RSECAR 0xfffffed0
14#define RMINAR 0xfffffed2
15#define RHRAR 0xfffffed4
16#define RWKAR 0xfffffed6
17#define RDAYAR 0xfffffed8
18#define RMONAR 0xfffffeda
19#define RCR1 0xfffffedc
20#define RCR2 0xfffffede
21
22#define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */
23
24#endif /* __ASM_CPU_SH3_RTC_H */
25
diff --git a/include/asm-sh/cpu-sh3/shmparam.h b/include/asm-sh/cpu-sh3/shmparam.h
new file mode 100644
index 000000000000..da5b5eec81ee
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/shmparam.h
@@ -0,0 +1,16 @@
1/*
2 * include/asm-sh/cpu-sh3/shmparam.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_SHMPARAM_H
11#define __ASM_CPU_SH3_SHMPARAM_H
12
13#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
14
15#endif /* __ASM_CPU_SH3_SHMPARAM_H */
16
diff --git a/include/asm-sh/cpu-sh3/sigcontext.h b/include/asm-sh/cpu-sh3/sigcontext.h
new file mode 100644
index 000000000000..17310dc03dcd
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/sigcontext.h
@@ -0,0 +1,17 @@
1#ifndef __ASM_CPU_SH3_SIGCONTEXT_H
2#define __ASM_CPU_SH3_SIGCONTEXT_H
3
4struct sigcontext {
5 unsigned long oldmask;
6
7 /* CPU registers */
8 unsigned long sc_regs[16];
9 unsigned long sc_pc;
10 unsigned long sc_pr;
11 unsigned long sc_sr;
12 unsigned long sc_gbr;
13 unsigned long sc_mach;
14 unsigned long sc_macl;
15};
16
17#endif /* __ASM_CPU_SH3_SIGCONTEXT_H */
diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h
new file mode 100644
index 000000000000..3d8e95e8d10c
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/timer.h
@@ -0,0 +1,64 @@
1/*
2 * include/asm-sh/cpu-sh3/timer.h
3 *
4 * Copyright (C) 2004 Lineo Solutions, Inc.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_TIMER_H
11#define __ASM_CPU_SH3_TIMER_H
12
13/*
14 * ---------------------------------------------------------------------------
15 * TMU Common definitions for SH3 processors
16 * SH7706
17 * SH7709S
18 * SH7727
19 * SH7729R
20 * SH7710
21 * SH7720
22 * SH7300
23 * ---------------------------------------------------------------------------
24 */
25
26#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710)
27#define TMU_TSTR 0xa412fe92 /* Byte access */
28
29#define TMU0_TCOR 0xa412fe94 /* Long access */
30#define TMU0_TCNT 0xa412fe98 /* Long access */
31#define TMU0_TCR 0xa412fe9c /* Word access */
32
33#define TMU1_TCOR 0xa412fea0 /* Long access */
34#define TMU1_TCNT 0xa412fea4 /* Long access */
35#define TMU1_TCR 0xa412fea8 /* Word access */
36
37#define TMU2_TCOR 0xa412feac /* Long access */
38#define TMU2_TCNT 0xa412feb0 /* Long access */
39#define TMU2_TCR 0xa412feb4 /* Word access */
40
41#else
42#if !defined(CONFIG_CPU_SUBTYPE_SH7727)
43#define TMU_TOCR 0xfffffe90 /* Byte access */
44#endif
45#define TMU_TSTR 0xfffffe92 /* Byte access */
46
47#define TMU0_TCOR 0xfffffe94 /* Long access */
48#define TMU0_TCNT 0xfffffe98 /* Long access */
49#define TMU0_TCR 0xfffffe9c /* Word access */
50
51#define TMU1_TCOR 0xfffffea0 /* Long access */
52#define TMU1_TCNT 0xfffffea4 /* Long access */
53#define TMU1_TCR 0xfffffea8 /* Word access */
54
55#define TMU2_TCOR 0xfffffeac /* Long access */
56#define TMU2_TCNT 0xfffffeb0 /* Long access */
57#define TMU2_TCR 0xfffffeb4 /* Word access */
58#if !defined(CONFIG_CPU_SUBTYPE_SH7727)
59#define TMU2_TCPR2 0xfffffeb8 /* Long access */
60#endif
61#endif
62
63#endif /* __ASM_CPU_SH3_TIMER_H */
64
diff --git a/include/asm-sh/cpu-sh3/ubc.h b/include/asm-sh/cpu-sh3/ubc.h
new file mode 100644
index 000000000000..0f809dec4e17
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/ubc.h
@@ -0,0 +1,27 @@
1/*
2 * include/asm-sh/cpu-sh3/ubc.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_CPU_SH3_UBC_H
12#define __ASM_CPU_SH3_UBC_H
13
14#define UBC_BARA 0xffffffb0
15#define UBC_BAMRA 0xffffffb4
16#define UBC_BBRA 0xffffffb8
17#define UBC_BASRA 0xffffffe4
18#define UBC_BARB 0xffffffa0
19#define UBC_BAMRB 0xffffffa4
20#define UBC_BBRB 0xffffffa8
21#define UBC_BASRB 0xffffffe8
22#define UBC_BDRB 0xffffff90
23#define UBC_BDMRB 0xffffff94
24#define UBC_BRCR 0xffffff98
25
26#endif /* __ASM_CPU_SH3_UBC_H */
27
diff --git a/include/asm-sh/cpu-sh3/watchdog.h b/include/asm-sh/cpu-sh3/watchdog.h
new file mode 100644
index 000000000000..4ee0347298d8
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/watchdog.h
@@ -0,0 +1,25 @@
1/*
2 * include/asm-sh/cpu-sh3/watchdog.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_WATCHDOG_H
11#define __ASM_CPU_SH3_WATCHDOG_H
12
13/* Register definitions */
14#define WTCNT 0xffffff84
15#define WTCSR 0xffffff86
16
17/* Bit definitions */
18#define WTCSR_TME 0x80
19#define WTCSR_WT 0x40
20#define WTCSR_RSTS 0x20
21#define WTCSR_WOVF 0x10
22#define WTCSR_IOVF 0x08
23
24#endif /* __ASM_CPU_SH3_WATCHDOG_H */
25
diff --git a/include/asm-sh/cpu-sh4/addrspace.h b/include/asm-sh/cpu-sh4/addrspace.h
new file mode 100644
index 000000000000..727634d886ce
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/addrspace.h
@@ -0,0 +1,26 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999 by Kaz Kojima
7 *
8 * Defitions for the address spaces of the SH-4 CPUs.
9 */
10#ifndef __ASM_CPU_SH4_ADDRSPACE_H
11#define __ASM_CPU_SH4_ADDRSPACE_H
12
13/* Detailed P4SEG */
14#define P4SEG_STORE_QUE (P4SEG)
15#define P4SEG_IC_ADDR 0xf0000000
16#define P4SEG_IC_DATA 0xf1000000
17#define P4SEG_ITLB_ADDR 0xf2000000
18#define P4SEG_ITLB_DATA 0xf3000000
19#define P4SEG_OC_ADDR 0xf4000000
20#define P4SEG_OC_DATA 0xf5000000
21#define P4SEG_TLB_ADDR 0xf6000000
22#define P4SEG_TLB_DATA 0xf7000000
23#define P4SEG_REG_BASE 0xff000000
24
25#endif /* __ASM_CPU_SH4_ADDRSPACE_H */
26
diff --git a/include/asm-sh/cpu-sh4/cache.h b/include/asm-sh/cpu-sh4/cache.h
new file mode 100644
index 000000000000..1fe20359312c
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/cache.h
@@ -0,0 +1,35 @@
1/*
2 * include/asm-sh/cpu-sh4/cache.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_CACHE_H
11#define __ASM_CPU_SH4_CACHE_H
12
13#define L1_CACHE_SHIFT 5
14
15#define CCR 0xff00001c /* Address of Cache Control Register */
16#define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */
17#define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/
18#define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */
19#define CCR_CACHE_OCI 0x0008 /* OC Invalidate */
20#define CCR_CACHE_ORA 0x0020 /* OC RAM Mode */
21#define CCR_CACHE_OIX 0x0080 /* OC Index Enable */
22#define CCR_CACHE_ICE 0x0100 /* Instruction Cache Enable */
23#define CCR_CACHE_ICI 0x0800 /* IC Invalidate */
24#define CCR_CACHE_IIX 0x8000 /* IC Index Enable */
25#define CCR_CACHE_EMODE 0x80000000 /* EMODE Enable */
26
27/* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */
28#define CCR_CACHE_ENABLE (CCR_CACHE_OCE|CCR_CACHE_ICE)
29#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI|CCR_CACHE_ICI)
30
31#define CACHE_IC_ADDRESS_ARRAY 0xf0000000
32#define CACHE_OC_ADDRESS_ARRAY 0xf4000000
33
34#endif /* __ASM_CPU_SH4_CACHE_H */
35
diff --git a/include/asm-sh/cpu-sh4/cacheflush.h b/include/asm-sh/cpu-sh4/cacheflush.h
new file mode 100644
index 000000000000..f323567e085f
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/cacheflush.h
@@ -0,0 +1,64 @@
1/*
2 * include/asm-sh/cpu-sh4/cacheflush.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_CPU_SH4_CACHEFLUSH_H
12#define __ASM_CPU_SH4_CACHEFLUSH_H
13
14/*
15 * Caches are broken on SH-4 (unless we use write-through
16 * caching; in which case they're only semi-broken),
17 * so we need them.
18 */
19
20/* Page is 4K, OC size is 16K, there are four lines. */
21#define CACHE_ALIAS 0x00003000
22
23struct page;
24struct mm_struct;
25struct vm_area_struct;
26
27extern void flush_cache_all(void);
28extern void flush_cache_mm(struct mm_struct *mm);
29extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
30 unsigned long end);
31extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
32extern void flush_dcache_page(struct page *pg);
33
34#define flush_dcache_mmap_lock(mapping) do { } while (0)
35#define flush_dcache_mmap_unlock(mapping) do { } while (0)
36
37extern void flush_icache_range(unsigned long start, unsigned long end);
38extern void flush_cache_sigtramp(unsigned long addr);
39extern void flush_icache_user_range(struct vm_area_struct *vma,
40 struct page *page, unsigned long addr,
41 int len);
42
43#define flush_icache_page(vma,pg) do { } while (0)
44
45/* Initialization of P3 area for copy_user_page */
46extern void p3_cache_init(void);
47
48#define PG_mapped PG_arch_1
49
50/* We provide our own get_unmapped_area to avoid cache alias issue */
51#define HAVE_ARCH_UNMAPPED_AREA
52
53#ifdef CONFIG_MMU
54extern int remap_area_pages(unsigned long addr, unsigned long phys_addr,
55 unsigned long size, unsigned long flags);
56#else /* CONFIG_MMU */
57static inline int remap_area_pages(unsigned long addr, unsigned long phys_addr,
58 unsigned long size, unsigned long flags)
59{
60 return 0;
61}
62#endif /* CONFIG_MMU */
63#endif /* __ASM_CPU_SH4_CACHEFLUSH_H */
64
diff --git a/include/asm-sh/cpu-sh4/dma.h b/include/asm-sh/cpu-sh4/dma.h
new file mode 100644
index 000000000000..e2b91adf821a
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/dma.h
@@ -0,0 +1,17 @@
1#ifndef __ASM_CPU_SH4_DMA_H
2#define __ASM_CPU_SH4_DMA_H
3
4#define SH_DMAC_BASE 0xffa00000
5
6#define SAR ((unsigned long[]){SH_DMAC_BASE + 0x00, SH_DMAC_BASE + 0x10, \
7 SH_DMAC_BASE + 0x20, SH_DMAC_BASE + 0x30})
8#define DAR ((unsigned long[]){SH_DMAC_BASE + 0x04, SH_DMAC_BASE + 0x14, \
9 SH_DMAC_BASE + 0x24, SH_DMAC_BASE + 0x34})
10#define DMATCR ((unsigned long[]){SH_DMAC_BASE + 0x08, SH_DMAC_BASE + 0x18, \
11 SH_DMAC_BASE + 0x28, SH_DMAC_BASE + 0x38})
12#define CHCR ((unsigned long[]){SH_DMAC_BASE + 0x0c, SH_DMAC_BASE + 0x1c, \
13 SH_DMAC_BASE + 0x2c, SH_DMAC_BASE + 0x3c})
14#define DMAOR (SH_DMAC_BASE + 0x40)
15
16#endif /* __ASM_CPU_SH4_DMA_H */
17
diff --git a/include/asm-sh/cpu-sh4/freq.h b/include/asm-sh/cpu-sh4/freq.h
new file mode 100644
index 000000000000..201d94fd214f
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/freq.h
@@ -0,0 +1,22 @@
1/*
2 * include/asm-sh/cpu-sh4/freq.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_FREQ_H
11#define __ASM_CPU_SH4_FREQ_H
12
13#if defined(CONFIG_CPU_SUBTYPE_SH73180)
14#define FRQCR 0xa4150000
15#else
16#define FRQCR 0xffc00000
17#endif
18#define MIN_DIVISOR_NR 0
19#define MAX_DIVISOR_NR 3
20
21#endif /* __ASM_CPU_SH4_FREQ_H */
22
diff --git a/include/asm-sh/cpu-sh4/mmu_context.h b/include/asm-sh/cpu-sh4/mmu_context.h
new file mode 100644
index 000000000000..5b64d041f0b9
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/mmu_context.h
@@ -0,0 +1,39 @@
1/*
2 * include/asm-sh/cpu-sh4/mmu_context.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_MMU_CONTEXT_H
11#define __ASM_CPU_SH4_MMU_CONTEXT_H
12
13#define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
14#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
15#define MMU_TTB 0xFF000008 /* Translation table base register */
16#define MMU_TEA 0xFF00000C /* TLB Exception Address */
17#define MMU_PTEA 0xFF000034 /* Page table entry assistance register */
18
19#define MMUCR 0xFF000010 /* MMU Control Register */
20
21#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
22#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
23#define MMU_PAGE_ASSOC_BIT 0x80
24
25#define MMU_NTLB_ENTRIES 64 /* for 7750 */
26#define MMU_CONTROL_INIT 0x205 /* SQMD=1, SV=0, TI=1, AT=1 */
27
28#define MMU_ITLB_DATA_ARRAY 0xF3000000
29#define MMU_UTLB_DATA_ARRAY 0xF7000000
30
31#define MMU_UTLB_ENTRIES 64
32#define MMU_U_ENTRY_SHIFT 8
33#define MMU_UTLB_VALID 0x100
34#define MMU_ITLB_ENTRIES 4
35#define MMU_I_ENTRY_SHIFT 8
36#define MMU_ITLB_VALID 0x100
37
38#endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */
39
diff --git a/include/asm-sh/cpu-sh4/rtc.h b/include/asm-sh/cpu-sh4/rtc.h
new file mode 100644
index 000000000000..e091e32a67b7
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/rtc.h
@@ -0,0 +1,25 @@
1#ifndef __ASM_CPU_SH4_RTC_H
2#define __ASM_CPU_SH4_RTC_H
3
4/* SH-4 RTC */
5#define R64CNT 0xffc80000
6#define RSECCNT 0xffc80004
7#define RMINCNT 0xffc80008
8#define RHRCNT 0xffc8000c
9#define RWKCNT 0xffc80010
10#define RDAYCNT 0xffc80014
11#define RMONCNT 0xffc80018
12#define RYRCNT 0xffc8001c /* 16bit */
13#define RSECAR 0xffc80020
14#define RMINAR 0xffc80024
15#define RHRAR 0xffc80028
16#define RWKAR 0xffc8002c
17#define RDAYAR 0xffc80030
18#define RMONAR 0xffc80034
19#define RCR1 0xffc80038
20#define RCR2 0xffc8003c
21
22#define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */
23
24#endif /* __ASM_CPU_SH4_RTC_H */
25
diff --git a/include/asm-sh/cpu-sh4/shmparam.h b/include/asm-sh/cpu-sh4/shmparam.h
new file mode 100644
index 000000000000..a5a0aa9425fe
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/shmparam.h
@@ -0,0 +1,19 @@
1/*
2 * include/asm-sh/cpu-sh4/shmparam.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_SHMPARAM_H
11#define __ASM_CPU_SH4_SHMPARAM_H
12
13/*
14 * SH-4 has D-cache alias issue
15 */
16#define SHMLBA (PAGE_SIZE*4) /* attach addr a multiple of this */
17
18#endif /* __ASM_CPU_SH4_SHMPARAM_H */
19
diff --git a/include/asm-sh/cpu-sh4/sigcontext.h b/include/asm-sh/cpu-sh4/sigcontext.h
new file mode 100644
index 000000000000..ab392f120e06
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/sigcontext.h
@@ -0,0 +1,24 @@
1#ifndef __ASM_CPU_SH4_SIGCONTEXT_H
2#define __ASM_CPU_SH4_SIGCONTEXT_H
3
4struct sigcontext {
5 unsigned long oldmask;
6
7 /* CPU registers */
8 unsigned long sc_regs[16];
9 unsigned long sc_pc;
10 unsigned long sc_pr;
11 unsigned long sc_sr;
12 unsigned long sc_gbr;
13 unsigned long sc_mach;
14 unsigned long sc_macl;
15
16 /* FPU registers */
17 unsigned long sc_fpregs[16];
18 unsigned long sc_xfpregs[16];
19 unsigned int sc_fpscr;
20 unsigned int sc_fpul;
21 unsigned int sc_ownedfp;
22};
23
24#endif /* __ASM_CPU_SH4_SIGCONTEXT_H */
diff --git a/include/asm-sh/cpu-sh4/sq.h b/include/asm-sh/cpu-sh4/sq.h
new file mode 100644
index 000000000000..366b09166d3b
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/sq.h
@@ -0,0 +1,48 @@
1/*
2 * include/asm-sh/cpu-sh4/sq.h
3 *
4 * Copyright (C) 2001, 2002, 2003 Paul Mundt
5 * Copyright (C) 2001, 2002 M. R. Brown
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_CPU_SH4_SQ_H
12#define __ASM_CPU_SH4_SQ_H
13
14#include <asm/addrspace.h>
15
16/*
17 * Store queues range from e0000000-e3fffffc, allowing approx. 64MB to be
18 * mapped to any physical address space. Since data is written (and aligned)
19 * to 32-byte boundaries, we need to be sure that all allocations are aligned.
20 */
21#define SQ_SIZE 32
22#define SQ_ALIGN_MASK (~(SQ_SIZE - 1))
23#define SQ_ALIGN(addr) (((addr)+SQ_SIZE-1) & SQ_ALIGN_MASK)
24
25#define SQ_QACR0 (P4SEG_REG_BASE + 0x38)
26#define SQ_QACR1 (P4SEG_REG_BASE + 0x3c)
27#define SQ_ADDRMAX (P4SEG_STORE_QUE + 0x04000000)
28
29struct sq_mapping {
30 const char *name;
31
32 unsigned long sq_addr;
33 unsigned long addr;
34 unsigned int size;
35
36 struct list_head list;
37};
38
39/* arch/sh/kernel/cpu/sh4/sq.c */
40extern struct sq_mapping *sq_remap(unsigned long phys, unsigned int size, const char *name);
41extern void sq_unmap(struct sq_mapping *map);
42
43extern void sq_clear(unsigned long addr, unsigned int len);
44extern void sq_flush(void *addr);
45extern void sq_flush_range(unsigned long start, unsigned int len);
46
47#endif /* __ASM_CPU_SH4_SQ_H */
48
diff --git a/include/asm-sh/cpu-sh4/timer.h b/include/asm-sh/cpu-sh4/timer.h
new file mode 100644
index 000000000000..8a4af126c890
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/timer.h
@@ -0,0 +1,51 @@
1/*
2 * include/asm-sh/cpu-sh4/timer.h
3 *
4 * Copyright (C) 2004 Lineo Solutions, Inc.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_TIMER_H
11#define __ASM_CPU_SH4_TIMER_H
12
13/*
14 * ---------------------------------------------------------------------------
15 * TMU Common definitions for SH4 processors
16 * SH7750S/SH7750R
17 * SH7751/SH7751R
18 * SH7760
19 * ---------------------------------------------------------------------------
20 */
21
22#if !defined(CONFIG_CPU_SUBTYPE_SH7760)
23#define TMU_TOCR 0xffd80000 /* Byte access */
24#endif
25#define TMU_TSTR 0xffd80004 /* Byte access */
26
27#define TMU0_TCOR 0xffd80008 /* Long access */
28#define TMU0_TCNT 0xffd8000c /* Long access */
29#define TMU0_TCR 0xffd80010 /* Word access */
30
31#define TMU1_TCOR 0xffd80014 /* Long access */
32#define TMU1_TCNT 0xffd80018 /* Long access */
33#define TMU1_TCR 0xffd8001c /* Word access */
34
35#define TMU2_TCOR 0xffd80020 /* Long access */
36#define TMU2_TCNT 0xffd80024 /* Long access */
37#define TMU2_TCR 0xffd80028 /* Word access */
38#define TMU2_TCPR 0xffd8002c /* Long access */
39
40#if !defined(CONFIG_CPU_SUBTYPE_SH7760)
41#define TMU3_TCOR 0xfe100008 /* Long access */
42#define TMU3_TCNT 0xfe10000c /* Long access */
43#define TMU3_TCR 0xfe100010 /* Word access */
44
45#define TMU4_TCOR 0xfe100014 /* Long access */
46#define TMU4_TCNT 0xfe100018 /* Long access */
47#define TMU4_TCR 0xfe10001c /* Word access */
48#endif
49
50#endif /* __ASM_CPU_SH4_TIMER_H */
51
diff --git a/include/asm-sh/cpu-sh4/ubc.h b/include/asm-sh/cpu-sh4/ubc.h
new file mode 100644
index 000000000000..3d0943167659
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/ubc.h
@@ -0,0 +1,27 @@
1/*
2 * include/asm-sh/cpu-sh4/ubc.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_CPU_SH4_UBC_H
12#define __ASM_CPU_SH4_UBC_H
13
14#define UBC_BARA 0xff200000
15#define UBC_BAMRA 0xff200004
16#define UBC_BBRA 0xff200008
17#define UBC_BASRA 0xff000014
18#define UBC_BARB 0xff20000c
19#define UBC_BAMRB 0xff200010
20#define UBC_BBRB 0xff200014
21#define UBC_BASRB 0xff000018
22#define UBC_BDRB 0xff200018
23#define UBC_BDMRB 0xff20001c
24#define UBC_BRCR 0xff200020
25
26#endif /* __ASM_CPU_SH4_UBC_H */
27
diff --git a/include/asm-sh/cpu-sh4/watchdog.h b/include/asm-sh/cpu-sh4/watchdog.h
new file mode 100644
index 000000000000..259f6a0ce23d
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/watchdog.h
@@ -0,0 +1,25 @@
1/*
2 * include/asm-sh/cpu-sh4/watchdog.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_WATCHDOG_H
11#define __ASM_CPU_SH4_WATCHDOG_H
12
13/* Register definitions */
14#define WTCNT 0xffc00008
15#define WTCSR 0xffc0000c
16
17/* Bit definitions */
18#define WTCSR_TME 0x80
19#define WTCSR_WT 0x40
20#define WTCSR_RSTS 0x20
21#define WTCSR_WOVF 0x10
22#define WTCSR_IOVF 0x08
23
24#endif /* __ASM_CPU_SH4_WATCHDOG_H */
25
diff --git a/include/asm-sh/cputime.h b/include/asm-sh/cputime.h
new file mode 100644
index 000000000000..6ca395d1393e
--- /dev/null
+++ b/include/asm-sh/cputime.h
@@ -0,0 +1,6 @@
1#ifndef __SH_CPUTIME_H
2#define __SH_CPUTIME_H
3
4#include <asm-generic/cputime.h>
5
6#endif /* __SH_CPUTIME_H */
diff --git a/include/asm-sh/cqreek/cqreek.h b/include/asm-sh/cqreek/cqreek.h
new file mode 100644
index 000000000000..09aecc06693e
--- /dev/null
+++ b/include/asm-sh/cqreek/cqreek.h
@@ -0,0 +1,27 @@
1#ifndef __ASM_SH_CQREEK_CQREEK_H
2#define __ASM_SH_CQREEK_CQREEK_H
3
4#define BRIDGE_FEATURE 0x0002
5
6#define BRIDGE_IDE_CTRL 0x0018
7#define BRIDGE_IDE_INTR_LVL 0x001A
8#define BRIDGE_IDE_INTR_MASK 0x001C
9#define BRIDGE_IDE_INTR_STAT 0x001E
10
11#define BRIDGE_ISA_CTRL 0x0028
12#define BRIDGE_ISA_INTR_LVL 0x002A
13#define BRIDGE_ISA_INTR_MASK 0x002C
14#define BRIDGE_ISA_INTR_STAT 0x002E
15
16/* arch/sh/boards/cqreek/setup.c */
17extern void setup_cqreek(void);
18
19/* arch/sh/boards/cqreek/irq.c */
20extern int cqreek_has_ide, cqreek_has_isa;
21extern void init_cqreek_IRQ(void);
22
23/* arch/sh/boards/cqreek/io.c */
24extern unsigned long cqreek_port2addr(unsigned long port);
25
26#endif /* __ASM_SH_CQREEK_CQREEK_H */
27
diff --git a/include/asm-sh/current.h b/include/asm-sh/current.h
new file mode 100644
index 000000000000..62b63880b333
--- /dev/null
+++ b/include/asm-sh/current.h
@@ -0,0 +1,20 @@
1#ifndef __ASM_SH_CURRENT_H
2#define __ASM_SH_CURRENT_H
3
4/*
5 * Copyright (C) 1999 Niibe Yutaka
6 *
7 */
8
9#include <linux/thread_info.h>
10
11struct task_struct;
12
13static __inline__ struct task_struct * get_current(void)
14{
15 return current_thread_info()->task;
16}
17
18#define current get_current()
19
20#endif /* __ASM_SH_CURRENT_H */
diff --git a/include/asm-sh/delay.h b/include/asm-sh/delay.h
new file mode 100644
index 000000000000..db599b2a5a9c
--- /dev/null
+++ b/include/asm-sh/delay.h
@@ -0,0 +1,27 @@
1#ifndef __ASM_SH_DELAY_H
2#define __ASM_SH_DELAY_H
3
4/*
5 * Copyright (C) 1993 Linus Torvalds
6 *
7 * Delay routines calling functions in arch/sh/lib/delay.c
8 */
9
10extern void __bad_udelay(void);
11extern void __bad_ndelay(void);
12
13extern void __udelay(unsigned long usecs);
14extern void __ndelay(unsigned long nsecs);
15extern void __const_udelay(unsigned long usecs);
16extern void __delay(unsigned long loops);
17
18#define udelay(n) (__builtin_constant_p(n) ? \
19 ((n) > 20000 ? __bad_udelay() : __const_udelay((n) * 0x10c6ul)) : \
20 __udelay(n))
21
22
23#define ndelay(n) (__builtin_constant_p(n) ? \
24 ((n) > 20000 ? __bad_ndelay() : __const_udelay((n) * 5ul)) : \
25 __ndelay(n))
26
27#endif /* __ASM_SH_DELAY_H */
diff --git a/include/asm-sh/div64.h b/include/asm-sh/div64.h
new file mode 100644
index 000000000000..6cd978cefb28
--- /dev/null
+++ b/include/asm-sh/div64.h
@@ -0,0 +1 @@
#include <asm-generic/div64.h>
diff --git a/include/asm-sh/dma-mapping.h b/include/asm-sh/dma-mapping.h
new file mode 100644
index 000000000000..80d164c1529e
--- /dev/null
+++ b/include/asm-sh/dma-mapping.h
@@ -0,0 +1,179 @@
1#ifndef __ASM_SH_DMA_MAPPING_H
2#define __ASM_SH_DMA_MAPPING_H
3
4#include <linux/config.h>
5#include <linux/mm.h>
6#include <asm/scatterlist.h>
7#include <asm/io.h>
8
9extern struct bus_type pci_bus_type;
10
11/* arch/sh/mm/consistent.c */
12extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
13extern void consistent_free(void *vaddr, size_t size);
14extern void consistent_sync(void *vaddr, size_t size, int direction);
15
16#define dma_supported(dev, mask) (1)
17
18static inline int dma_set_mask(struct device *dev, u64 mask)
19{
20 if (!dev->dma_mask || !dma_supported(dev, mask))
21 return -EIO;
22
23 *dev->dma_mask = mask;
24
25 return 0;
26}
27
28static inline void *dma_alloc_coherent(struct device *dev, size_t size,
29 dma_addr_t *dma_handle, int flag)
30{
31 if (sh_mv.mv_consistent_alloc) {
32 void *ret;
33
34 ret = sh_mv.mv_consistent_alloc(dev, size, dma_handle, flag);
35 if (ret != NULL)
36 return ret;
37 }
38
39 return consistent_alloc(flag, size, dma_handle);
40}
41
42static inline void dma_free_coherent(struct device *dev, size_t size,
43 void *vaddr, dma_addr_t dma_handle)
44{
45 if (sh_mv.mv_consistent_free) {
46 int ret;
47
48 ret = sh_mv.mv_consistent_free(dev, size, vaddr, dma_handle);
49 if (ret == 0)
50 return;
51 }
52
53 consistent_free(vaddr, size);
54}
55
56static inline void dma_cache_sync(void *vaddr, size_t size,
57 enum dma_data_direction dir)
58{
59 consistent_sync(vaddr, size, (int)dir);
60}
61
62static inline dma_addr_t dma_map_single(struct device *dev,
63 void *ptr, size_t size,
64 enum dma_data_direction dir)
65{
66#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
67 if (dev->bus == &pci_bus_type)
68 return virt_to_bus(ptr);
69#endif
70 dma_cache_sync(ptr, size, dir);
71
72 return virt_to_bus(ptr);
73}
74
75#define dma_unmap_single(dev, addr, size, dir) do { } while (0)
76
77static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
78 int nents, enum dma_data_direction dir)
79{
80 int i;
81
82 for (i = 0; i < nents; i++) {
83#if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT)
84 dma_cache_sync(page_address(sg[i].page) + sg[i].offset,
85 sg[i].length, dir);
86#endif
87 sg[i].dma_address = page_to_phys(sg[i].page) + sg[i].offset;
88 }
89
90 return nents;
91}
92
93#define dma_unmap_sg(dev, sg, nents, dir) do { } while (0)
94
95static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
96 unsigned long offset, size_t size,
97 enum dma_data_direction dir)
98{
99 return dma_map_single(dev, page_address(page) + offset, size, dir);
100}
101
102static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
103 size_t size, enum dma_data_direction dir)
104{
105 dma_unmap_single(dev, dma_address, size, dir);
106}
107
108static inline void dma_sync_single(struct device *dev, dma_addr_t dma_handle,
109 size_t size, enum dma_data_direction dir)
110{
111#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
112 if (dev->bus == &pci_bus_type)
113 return;
114#endif
115 dma_cache_sync(bus_to_virt(dma_handle), size, dir);
116}
117
118static inline void dma_sync_single_range(struct device *dev,
119 dma_addr_t dma_handle,
120 unsigned long offset, size_t size,
121 enum dma_data_direction dir)
122{
123#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
124 if (dev->bus == &pci_bus_type)
125 return;
126#endif
127 dma_cache_sync(bus_to_virt(dma_handle) + offset, size, dir);
128}
129
130static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg,
131 int nelems, enum dma_data_direction dir)
132{
133 int i;
134
135 for (i = 0; i < nelems; i++) {
136#if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT)
137 dma_cache_sync(page_address(sg[i].page) + sg[i].offset,
138 sg[i].length, dir);
139#endif
140 sg[i].dma_address = page_to_phys(sg[i].page) + sg[i].offset;
141 }
142}
143
144static inline void dma_sync_single_for_cpu(struct device *dev,
145 dma_addr_t dma_handle, size_t size,
146 enum dma_data_direction dir)
147 __attribute__ ((alias("dma_sync_single")));
148
149static inline void dma_sync_single_for_device(struct device *dev,
150 dma_addr_t dma_handle, size_t size,
151 enum dma_data_direction dir)
152 __attribute__ ((alias("dma_sync_single")));
153
154static inline void dma_sync_sg_for_cpu(struct device *dev,
155 struct scatterlist *sg, int nelems,
156 enum dma_data_direction dir)
157 __attribute__ ((alias("dma_sync_sg")));
158
159static inline void dma_sync_sg_for_device(struct device *dev,
160 struct scatterlist *sg, int nelems,
161 enum dma_data_direction dir)
162 __attribute__ ((alias("dma_sync_sg")));
163
164static inline int dma_get_cache_alignment(void)
165{
166 /*
167 * Each processor family will define its own L1_CACHE_SHIFT,
168 * L1_CACHE_BYTES wraps to this, so this is always safe.
169 */
170 return L1_CACHE_BYTES;
171}
172
173static inline int dma_mapping_error(dma_addr_t dma_addr)
174{
175 return dma_addr == 0;
176}
177
178#endif /* __ASM_SH_DMA_MAPPING_H */
179
diff --git a/include/asm-sh/dma.h b/include/asm-sh/dma.h
new file mode 100644
index 000000000000..8e9436093ca8
--- /dev/null
+++ b/include/asm-sh/dma.h
@@ -0,0 +1,143 @@
1/*
2 * include/asm-sh/dma.h
3 *
4 * Copyright (C) 2003, 2004 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_SH_DMA_H
11#define __ASM_SH_DMA_H
12#ifdef __KERNEL__
13
14#include <linux/config.h>
15#include <linux/spinlock.h>
16#include <linux/wait.h>
17#include <linux/sysdev.h>
18#include <asm/cpu/dma.h>
19#include <asm/semaphore.h>
20
21/* The maximum address that we can perform a DMA transfer to on this platform */
22/* Don't define MAX_DMA_ADDRESS; it's useless on the SuperH and any
23 occurrence should be flagged as an error. */
24/* But... */
25/* XXX: This is not applicable to SuperH, just needed for alloc_bootmem */
26#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
27
28#ifdef CONFIG_NR_DMA_CHANNELS
29# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS)
30#else
31# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
32#endif
33
34/*
35 * Read and write modes can mean drastically different things depending on the
36 * channel configuration. Consult your DMAC documentation and module
37 * implementation for further clues.
38 */
39#define DMA_MODE_READ 0x00
40#define DMA_MODE_WRITE 0x01
41#define DMA_MODE_MASK 0x01
42
43#define DMA_AUTOINIT 0x10
44
45/*
46 * DMAC (dma_info) flags
47 */
48enum {
49 DMAC_CHANNELS_CONFIGURED = 0x00,
50 DMAC_CHANNELS_TEI_CAPABLE = 0x01,
51};
52
53/*
54 * DMA channel capabilities / flags
55 */
56enum {
57 DMA_CONFIGURED = 0x00,
58 DMA_TEI_CAPABLE = 0x01,
59};
60
61extern spinlock_t dma_spin_lock;
62
63struct dma_channel;
64
65struct dma_ops {
66 int (*request)(struct dma_channel *chan);
67 void (*free)(struct dma_channel *chan);
68
69 int (*get_residue)(struct dma_channel *chan);
70 int (*xfer)(struct dma_channel *chan);
71 void (*configure)(struct dma_channel *chan, unsigned long flags);
72};
73
74struct dma_channel {
75 char dev_id[16];
76
77 unsigned int chan;
78 unsigned int mode;
79 unsigned int count;
80
81 unsigned long sar;
82 unsigned long dar;
83
84 unsigned long flags;
85 atomic_t busy;
86
87 struct semaphore sem;
88 wait_queue_head_t wait_queue;
89
90 struct sys_device dev;
91};
92
93struct dma_info {
94 const char *name;
95 unsigned int nr_channels;
96 unsigned long flags;
97
98 struct dma_ops *ops;
99 struct dma_channel *channels;
100
101 struct list_head list;
102};
103
104#define to_dma_channel(channel) container_of(channel, struct dma_channel, dev)
105
106/* arch/sh/drivers/dma/dma-api.c */
107extern int dma_xfer(unsigned int chan, unsigned long from,
108 unsigned long to, size_t size, unsigned int mode);
109
110#define dma_write(chan, from, to, size) \
111 dma_xfer(chan, from, to, size, DMA_MODE_WRITE)
112#define dma_write_page(chan, from, to) \
113 dma_write(chan, from, to, PAGE_SIZE)
114
115#define dma_read(chan, from, to, size) \
116 dma_xfer(chan, from, to, size, DMA_MODE_READ)
117#define dma_read_page(chan, from, to) \
118 dma_read(chan, from, to, PAGE_SIZE)
119
120extern int request_dma(unsigned int chan, const char *dev_id);
121extern void free_dma(unsigned int chan);
122extern int get_dma_residue(unsigned int chan);
123extern struct dma_info *get_dma_info(unsigned int chan);
124extern struct dma_channel *get_dma_channel(unsigned int chan);
125extern void dma_wait_for_completion(unsigned int chan);
126extern void dma_configure_channel(unsigned int chan, unsigned long flags);
127
128extern int register_dmac(struct dma_info *info);
129extern void unregister_dmac(struct dma_info *info);
130
131#ifdef CONFIG_SYSFS
132/* arch/sh/drivers/dma/dma-sysfs.c */
133extern int dma_create_sysfs_files(struct dma_channel *);
134#endif
135
136#ifdef CONFIG_PCI
137extern int isa_dma_bridge_buggy;
138#else
139#define isa_dma_bridge_buggy (0)
140#endif
141
142#endif /* __KERNEL__ */
143#endif /* __ASM_SH_DMA_H */
diff --git a/include/asm-sh/dmida/io.h b/include/asm-sh/dmida/io.h
new file mode 100644
index 000000000000..21bd416c01c3
--- /dev/null
+++ b/include/asm-sh/dmida/io.h
@@ -0,0 +1,10 @@
1#ifndef __ASM_SH_DMIDA_IO_H
2#define __ASM_SH_DMIDA_IO_H
3
4/*
5 * Nothing special here.. just use the generic cchip io routines.
6 */
7#include <asm/hd64465/io.h>
8
9#endif /* __ASM_SH_DMIDA_IO_H */
10
diff --git a/include/asm-sh/dreamcast/dma.h b/include/asm-sh/dreamcast/dma.h
new file mode 100644
index 000000000000..ddd68e788705
--- /dev/null
+++ b/include/asm-sh/dreamcast/dma.h
@@ -0,0 +1,34 @@
1/*
2 * include/asm-sh/dreamcast/dma.h
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_SH_DREAMCAST_DMA_H
11#define __ASM_SH_DREAMCAST_DMA_H
12
13/* Number of DMA channels */
14#define ONCHIP_NR_DMA_CHANNELS 4
15#define G2_NR_DMA_CHANNELS 4
16#define PVR2_NR_DMA_CHANNELS 1
17
18/* Channels for cascading */
19#define PVR2_CASCADE_CHAN 2
20#define G2_CASCADE_CHAN 3
21
22/* PVR2 DMA Registers */
23#define PVR2_DMA_BASE 0xa05f6800
24#define PVR2_DMA_ADDR (PVR2_DMA_BASE + 0)
25#define PVR2_DMA_COUNT (PVR2_DMA_BASE + 4)
26#define PVR2_DMA_MODE (PVR2_DMA_BASE + 8)
27#define PVR2_DMA_LMMODE0 (PVR2_DMA_BASE + 132)
28#define PVR2_DMA_LMMODE1 (PVR2_DMA_BASE + 136)
29
30/* G2 DMA Register */
31#define G2_DMA_BASE 0xa05f7800
32
33#endif /* __ASM_SH_DREAMCAST_DMA_H */
34
diff --git a/include/asm-sh/dreamcast/pci.h b/include/asm-sh/dreamcast/pci.h
new file mode 100644
index 000000000000..e401b24b0d8e
--- /dev/null
+++ b/include/asm-sh/dreamcast/pci.h
@@ -0,0 +1,25 @@
1/*
2 * include/asm-sh/dreamcast/pci.h
3 *
4 * Copyright (C) 2001, 2002 M. R. Brown
5 * Copyright (C) 2002, 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_SH_DREAMCAST_PCI_H
12#define __ASM_SH_DREAMCAST_PCI_H
13
14#include <asm/mach/sysasic.h>
15
16#define GAPSPCI_REGS 0x01001400
17#define GAPSPCI_DMA_BASE 0x01840000
18#define GAPSPCI_DMA_SIZE 32768
19#define GAPSPCI_BBA_CONFIG 0x01001600
20#define GAPSPCI_BBA_CONFIG_SIZE 0x2000
21
22#define GAPSPCI_IRQ HW_EVENT_EXTERNAL
23
24#endif /* __ASM_SH_DREAMCAST_PCI_H */
25
diff --git a/include/asm-sh/dreamcast/sysasic.h b/include/asm-sh/dreamcast/sysasic.h
new file mode 100644
index 000000000000..c8858537803c
--- /dev/null
+++ b/include/asm-sh/dreamcast/sysasic.h
@@ -0,0 +1,43 @@
1/* include/asm-sh/dc_sysasic.h
2 *
3 * Definitions for the Dreamcast System ASIC and related peripherals.
4 *
5 * Copyright (c) 2001 M. R. Brown <mrbrown@linuxdc.org>
6 * Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org>
7 *
8 * This file is part of the LinuxDC project (www.linuxdc.org)
9 *
10 * Released under the terms of the GNU GPL v2.0.
11 *
12 */
13#ifndef __ASM_SH_DREAMCAST_SYSASIC_H
14#define __ASM_SH_DREAMCAST_SYSASIC_H
15
16#include <asm/irq.h>
17
18/* Hardware events -
19
20 Each of these events correspond to a bit within the Event Mask Registers/
21 Event Status Registers. Because of the virtual IRQ numbering scheme, a
22 base offset must be used when calculating the virtual IRQ that each event
23 takes.
24*/
25
26#define HW_EVENT_IRQ_BASE OFFCHIP_IRQ_BASE /* 48 */
27
28/* IRQ 13 */
29#define HW_EVENT_VSYNC (HW_EVENT_IRQ_BASE + 5) /* VSync */
30#define HW_EVENT_MAPLE_DMA (HW_EVENT_IRQ_BASE + 12) /* Maple DMA complete */
31#define HW_EVENT_GDROM_DMA (HW_EVENT_IRQ_BASE + 14) /* GD-ROM DMA complete */
32#define HW_EVENT_G2_DMA (HW_EVENT_IRQ_BASE + 15) /* G2 DMA complete */
33#define HW_EVENT_PVR2_DMA (HW_EVENT_IRQ_BASE + 19) /* PVR2 DMA complete */
34
35/* IRQ 11 */
36#define HW_EVENT_GDROM_CMD (HW_EVENT_IRQ_BASE + 32) /* GD-ROM cmd. complete */
37#define HW_EVENT_AICA_SYS (HW_EVENT_IRQ_BASE + 33) /* AICA-related */
38#define HW_EVENT_EXTERNAL (HW_EVENT_IRQ_BASE + 35) /* Ext. (expansion) */
39
40#define HW_EVENT_IRQ_MAX (HW_EVENT_IRQ_BASE + 95)
41
42#endif /* __ASM_SH_DREAMCAST_SYSASIC_H */
43
diff --git a/include/asm-sh/ec3104/ec3104.h b/include/asm-sh/ec3104/ec3104.h
new file mode 100644
index 000000000000..639cfa489c8f
--- /dev/null
+++ b/include/asm-sh/ec3104/ec3104.h
@@ -0,0 +1,43 @@
1#ifndef __ASM_EC3104_H
2#define __ASM_EC3104_H
3
4
5/*
6 * Most of the register set is at 0xb0ec0000 - 0xb0ecffff.
7 *
8 * as far as I've figured it out the register map is:
9 * 0xb0ec0000 - id string
10 * 0xb0ec0XXX - power management
11 * 0xb0ec1XXX - interrupt control
12 * 0xb0ec3XXX - ps2 port (touch pad on aero 8000)
13 * 0xb0ec6XXX - i2c
14 * 0xb0ec7000 - first serial port (proprietary connector on aero 8000)
15 * 0xb0ec8000 - second serial port
16 * 0xb0ec9000 - third serial port
17 * 0xb0eca000 - fourth serial port (keyboard controller on aero 8000)
18 * 0xb0eccXXX - GPIO
19 * 0xb0ecdXXX - GPIO
20 */
21
22#define EC3104_BASE 0xb0ec0000
23
24#define EC3104_SER4_DATA (EC3104_BASE+0xa000)
25#define EC3104_SER4_IIR (EC3104_BASE+0xa008)
26#define EC3104_SER4_MCR (EC3104_BASE+0xa010)
27#define EC3104_SER4_LSR (EC3104_BASE+0xa014)
28#define EC3104_SER4_MSR (EC3104_BASE+0xa018)
29
30/*
31 * our ISA bus. this seems to be real ISA.
32 */
33#define EC3104_ISA_BASE 0xa5000000
34
35#define EC3104_IRQ 11
36#define EC3104_IRQBASE 64
37
38#define EC3104_IRQ_SER1 EC3104_IRQBASE + 7
39#define EC3104_IRQ_SER2 EC3104_IRQBASE + 8
40#define EC3104_IRQ_SER3 EC3104_IRQBASE + 9
41#define EC3104_IRQ_SER4 EC3104_IRQBASE + 10
42
43#endif /* __ASM_EC3104_H */
diff --git a/include/asm-sh/ec3104/io.h b/include/asm-sh/ec3104/io.h
new file mode 100644
index 000000000000..ea5c8e65ac11
--- /dev/null
+++ b/include/asm-sh/ec3104/io.h
@@ -0,0 +1,16 @@
1#ifndef _ASM_SH_IO_EC3104_H
2#define _ASM_SH_IO_EC3104_H
3
4#include <linux/types.h>
5
6extern unsigned char ec3104_inb(unsigned long port);
7extern unsigned short ec3104_inw(unsigned long port);
8extern unsigned long ec3104_inl(unsigned long port);
9
10extern void ec3104_outb(unsigned char value, unsigned long port);
11extern void ec3104_outw(unsigned short value, unsigned long port);
12extern void ec3104_outl(unsigned long value, unsigned long port);
13
14extern int ec3104_irq_demux(int irq);
15
16#endif /* _ASM_SH_IO_EC3104_H */
diff --git a/include/asm-sh/ec3104/keyboard.h b/include/asm-sh/ec3104/keyboard.h
new file mode 100644
index 000000000000..0dee7b05b49d
--- /dev/null
+++ b/include/asm-sh/ec3104/keyboard.h
@@ -0,0 +1,17 @@
1extern unsigned char ec3104_kbd_sysrq_xlate[];
2extern int ec3104_kbd_setkeycode(unsigned int scancode, unsigned int keycode);
3extern int ec3104_kbd_getkeycode(unsigned int scancode);
4extern int ec3104_kbd_translate(unsigned char, unsigned char *, char);
5extern char ec3104_kbd_unexpected_up(unsigned char);
6extern void ec3104_kbd_leds(unsigned char);
7extern void ec3104_kbd_init_hw(void);
8
9#define SYSRQ_KEY 0x54
10
11#define kbd_sysrq_xlate ec3104_kbd_sysrq_xlate
12#define kbd_setkeycode ec3104_kbd_setkeycode
13#define kbd_getkeycode ec3104_kbd_getkeycode
14#define kbd_translate ec3104_kbd_translate
15#define kbd_unexpected_up ec3104_kbd_unexpected_up
16#define kbd_leds ec3104_kbd_leds
17#define kbd_init_hw ec3104_kbd_init_hw
diff --git a/include/asm-sh/ec3104/serial.h b/include/asm-sh/ec3104/serial.h
new file mode 100644
index 000000000000..f8eb16312ed9
--- /dev/null
+++ b/include/asm-sh/ec3104/serial.h
@@ -0,0 +1,22 @@
1#include <asm/ec3104.h>
2/* Naturally we don't know the exact value but 115200 baud has a divisor
3 * of 9 and 19200 baud has a divisor of 52, so this seems like a good
4 * guess. */
5#define BASE_BAUD (16800000 / 16)
6
7#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
8
9/* there is a fourth serial port with the expected values as well, but
10 * it's got the keyboard controller behind it so we can't really use it
11 * (without moving the keyboard driver to userspace, which doesn't sound
12 * like a very good idea) */
13#define STD_SERIAL_PORT_DEFNS \
14 /* UART CLK PORT IRQ FLAGS */ \
15 { 0, BASE_BAUD, 0x11C00, EC3104_IRQBASE+7, STD_COM_FLAGS }, /* ttyS0 */ \
16 { 0, BASE_BAUD, 0x12000, EC3104_IRQBASE+8, STD_COM_FLAGS }, /* ttyS1 */ \
17 { 0, BASE_BAUD, 0x12400, EC3104_IRQBASE+9, STD_COM_FLAGS }, /* ttyS2 */
18
19#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS
20
21/* XXX: This should be moved ino irq.h */
22#define irq_cannonicalize(x) (x)
diff --git a/include/asm-sh/edosk7705/io.h b/include/asm-sh/edosk7705/io.h
new file mode 100644
index 000000000000..a1089a65bc36
--- /dev/null
+++ b/include/asm-sh/edosk7705/io.h
@@ -0,0 +1,30 @@
1/*
2 * include/asm-sh/edosk7705/io.h
3 *
4 * Modified version of io_se.h for the EDOSK7705 specific functions.
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * IO functions for an Hitachi EDOSK7705 development board
10 */
11
12#ifndef __ASM_SH_EDOSK7705_IO_H
13#define __ASM_SH_EDOSK7705_IO_H
14
15#include <asm/io_generic.h>
16
17extern unsigned char sh_edosk7705_inb(unsigned long port);
18extern unsigned int sh_edosk7705_inl(unsigned long port);
19
20extern void sh_edosk7705_outb(unsigned char value, unsigned long port);
21extern void sh_edosk7705_outl(unsigned int value, unsigned long port);
22
23extern void sh_edosk7705_insb(unsigned long port, void *addr, unsigned long count);
24extern void sh_edosk7705_insl(unsigned long port, void *addr, unsigned long count);
25extern void sh_edosk7705_outsb(unsigned long port, const void *addr, unsigned long count);
26extern void sh_edosk7705_outsl(unsigned long port, const void *addr, unsigned long count);
27
28extern unsigned long sh_edosk7705_isa_port2addr(unsigned long offset);
29
30#endif /* __ASM_SH_EDOSK7705_IO_H */
diff --git a/include/asm-sh/elf.h b/include/asm-sh/elf.h
new file mode 100644
index 000000000000..8fe00a1981ce
--- /dev/null
+++ b/include/asm-sh/elf.h
@@ -0,0 +1,121 @@
1#ifndef __ASM_SH_ELF_H
2#define __ASM_SH_ELF_H
3
4/* SH relocation types */
5#define R_SH_NONE 0
6#define R_SH_DIR32 1
7#define R_SH_REL32 2
8#define R_SH_DIR8WPN 3
9#define R_SH_IND12W 4
10#define R_SH_DIR8WPL 5
11#define R_SH_DIR8WPZ 6
12#define R_SH_DIR8BP 7
13#define R_SH_DIR8W 8
14#define R_SH_DIR8L 9
15#define R_SH_SWITCH16 25
16#define R_SH_SWITCH32 26
17#define R_SH_USES 27
18#define R_SH_COUNT 28
19#define R_SH_ALIGN 29
20#define R_SH_CODE 30
21#define R_SH_DATA 31
22#define R_SH_LABEL 32
23#define R_SH_SWITCH8 33
24#define R_SH_GNU_VTINHERIT 34
25#define R_SH_GNU_VTENTRY 35
26#define R_SH_TLS_GD_32 144
27#define R_SH_TLS_LD_32 145
28#define R_SH_TLS_LDO_32 146
29#define R_SH_TLS_IE_32 147
30#define R_SH_TLS_LE_32 148
31#define R_SH_TLS_DTPMOD32 149
32#define R_SH_TLS_DTPOFF32 150
33#define R_SH_TLS_TPOFF32 151
34#define R_SH_GOT32 160
35#define R_SH_PLT32 161
36#define R_SH_COPY 162
37#define R_SH_GLOB_DAT 163
38#define R_SH_JMP_SLOT 164
39#define R_SH_RELATIVE 165
40#define R_SH_GOTOFF 166
41#define R_SH_GOTPC 167
42/* Keep this the last entry. */
43#define R_SH_NUM 256
44
45/*
46 * ELF register definitions..
47 */
48
49#include <asm/ptrace.h>
50#include <asm/user.h>
51
52typedef unsigned long elf_greg_t;
53
54#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
55typedef elf_greg_t elf_gregset_t[ELF_NGREG];
56
57typedef struct user_fpu_struct elf_fpregset_t;
58
59/*
60 * This is used to ensure we don't load something for the wrong architecture.
61 */
62#define elf_check_arch(x) ( (x)->e_machine == EM_SH )
63
64/*
65 * These are used to set parameters in the core dumps.
66 */
67#define ELF_CLASS ELFCLASS32
68#ifdef __LITTLE_ENDIAN__
69#define ELF_DATA ELFDATA2LSB
70#else
71#define ELF_DATA ELFDATA2MSB
72#endif
73#define ELF_ARCH EM_SH
74
75#define USE_ELF_CORE_DUMP
76#define ELF_EXEC_PAGESIZE 4096
77
78/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
79 use of this is to invoke "./ld.so someprog" to test out a new version of
80 the loader. We need to make sure that it is out of the way of the program
81 that it will "exec", and that there is sufficient room for the brk. */
82
83#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
84
85
86#define ELF_CORE_COPY_REGS(_dest,_regs) \
87 memcpy((char *) &_dest, (char *) _regs, \
88 sizeof(struct pt_regs));
89
90/* This yields a mask that user programs can use to figure out what
91 instruction set this CPU supports. This could be done in user space,
92 but it's not easy, and we've already done it here. */
93
94#define ELF_HWCAP (0)
95
96/* This yields a string that ld.so will use to load implementation
97 specific libraries for optimization. This is more specific in
98 intent than poking at uname or /proc/cpuinfo.
99
100 For the moment, we have only optimizations for the Intel generations,
101 but that could change... */
102
103#define ELF_PLATFORM (NULL)
104
105#define ELF_PLAT_INIT(_r, load_addr) \
106 do { _r->regs[0]=0; _r->regs[1]=0; _r->regs[2]=0; _r->regs[3]=0; \
107 _r->regs[4]=0; _r->regs[5]=0; _r->regs[6]=0; _r->regs[7]=0; \
108 _r->regs[8]=0; _r->regs[9]=0; _r->regs[10]=0; _r->regs[11]=0; \
109 _r->regs[12]=0; _r->regs[13]=0; _r->regs[14]=0; \
110 _r->sr = SR_FD; } while (0)
111
112#ifdef __KERNEL__
113#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT)
114extern int dump_task_regs (struct task_struct *, elf_gregset_t *);
115extern int dump_task_fpu (struct task_struct *, elf_fpregset_t *);
116
117#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
118#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
119#endif
120
121#endif /* __ASM_SH_ELF_H */
diff --git a/include/asm-sh/errno.h b/include/asm-sh/errno.h
new file mode 100644
index 000000000000..51cf6f9cebb8
--- /dev/null
+++ b/include/asm-sh/errno.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_SH_ERRNO_H
2#define __ASM_SH_ERRNO_H
3
4#include <asm-generic/errno.h>
5
6#endif /* __ASM_SH_ERRNO_H */
diff --git a/include/asm-sh/fcntl.h b/include/asm-sh/fcntl.h
new file mode 100644
index 000000000000..0b3ae524e34c
--- /dev/null
+++ b/include/asm-sh/fcntl.h
@@ -0,0 +1,88 @@
1#ifndef __ASM_SH_FCNTL_H
2#define __ASM_SH_FCNTL_H
3
4/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
5 located on an ext2 file system */
6#define O_ACCMODE 0003
7#define O_RDONLY 00
8#define O_WRONLY 01
9#define O_RDWR 02
10#define O_CREAT 0100 /* not fcntl */
11#define O_EXCL 0200 /* not fcntl */
12#define O_NOCTTY 0400 /* not fcntl */
13#define O_TRUNC 01000 /* not fcntl */
14#define O_APPEND 02000
15#define O_NONBLOCK 04000
16#define O_NDELAY O_NONBLOCK
17#define O_SYNC 010000
18#define FASYNC 020000 /* fcntl, for BSD compatibility */
19#define O_DIRECT 040000 /* direct disk access hint - currently ignored */
20#define O_LARGEFILE 0100000
21#define O_DIRECTORY 0200000 /* must be a directory */
22#define O_NOFOLLOW 0400000 /* don't follow links */
23#define O_NOATIME 01000000
24
25#define F_DUPFD 0 /* dup */
26#define F_GETFD 1 /* get close_on_exec */
27#define F_SETFD 2 /* set/clear close_on_exec */
28#define F_GETFL 3 /* get file->f_flags */
29#define F_SETFL 4 /* set file->f_flags */
30#define F_GETLK 5
31#define F_SETLK 6
32#define F_SETLKW 7
33
34#define F_SETOWN 8 /* for sockets. */
35#define F_GETOWN 9 /* for sockets. */
36#define F_SETSIG 10 /* for sockets. */
37#define F_GETSIG 11 /* for sockets. */
38
39#define F_GETLK64 12 /* using 'struct flock64' */
40#define F_SETLK64 13
41#define F_SETLKW64 14
42
43/* for F_[GET|SET]FL */
44#define FD_CLOEXEC 1 /* actually anything with low bit set goes */
45
46/* for posix fcntl() and lockf() */
47#define F_RDLCK 0
48#define F_WRLCK 1
49#define F_UNLCK 2
50
51/* for old implementation of bsd flock () */
52#define F_EXLCK 4 /* or 3 */
53#define F_SHLCK 8 /* or 4 */
54
55/* for leases */
56#define F_INPROGRESS 16
57
58/* operations for bsd flock(), also used by the kernel implementation */
59#define LOCK_SH 1 /* shared lock */
60#define LOCK_EX 2 /* exclusive lock */
61#define LOCK_NB 4 /* or'd with one of the above to prevent
62 blocking */
63#define LOCK_UN 8 /* remove lock */
64
65#define LOCK_MAND 32 /* This is a mandatory flock */
66#define LOCK_READ 64 /* ... Which allows concurrent read operations */
67#define LOCK_WRITE 128 /* ... Which allows concurrent write operations */
68#define LOCK_RW 192 /* ... Which allows concurrent read & write ops */
69
70struct flock {
71 short l_type;
72 short l_whence;
73 off_t l_start;
74 off_t l_len;
75 pid_t l_pid;
76};
77
78struct flock64 {
79 short l_type;
80 short l_whence;
81 loff_t l_start;
82 loff_t l_len;
83 pid_t l_pid;
84};
85
86#define F_LINUX_SPECIFIC_BASE 1024
87#endif /* __ASM_SH_FCNTL_H */
88
diff --git a/include/asm-sh/fixmap.h b/include/asm-sh/fixmap.h
new file mode 100644
index 000000000000..509224bdba28
--- /dev/null
+++ b/include/asm-sh/fixmap.h
@@ -0,0 +1,111 @@
1/*
2 * fixmap.h: compile-time virtual memory allocation
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1998 Ingo Molnar
9 *
10 * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
11 */
12
13#ifndef _ASM_FIXMAP_H
14#define _ASM_FIXMAP_H
15
16#include <linux/config.h>
17#include <linux/kernel.h>
18#include <asm/page.h>
19#ifdef CONFIG_HIGHMEM
20#include <linux/threads.h>
21#include <asm/kmap_types.h>
22#endif
23
24/*
25 * Here we define all the compile-time 'special' virtual
26 * addresses. The point is to have a constant address at
27 * compile time, but to set the physical address only
28 * in the boot process. We allocate these special addresses
29 * from the end of virtual memory (0xfffff000) backwards.
30 * Also this lets us do fail-safe vmalloc(), we
31 * can guarantee that these special addresses and
32 * vmalloc()-ed addresses never overlap.
33 *
34 * these 'compile-time allocated' memory buffers are
35 * fixed-size 4k pages. (or larger if used with an increment
36 * highger than 1) use fixmap_set(idx,phys) to associate
37 * physical memory with fixmap indices.
38 *
39 * TLB entries of such buffers will not be flushed across
40 * task switches.
41 */
42
43/*
44 * on UP currently we will have no trace of the fixmap mechanizm,
45 * no page table allocations, etc. This might change in the
46 * future, say framebuffers for the console driver(s) could be
47 * fix-mapped?
48 */
49enum fixed_addresses {
50#ifdef CONFIG_HIGHMEM
51 FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
52 FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
53#endif
54 __end_of_fixed_addresses
55};
56
57extern void __set_fixmap (enum fixed_addresses idx,
58 unsigned long phys, pgprot_t flags);
59
60#define set_fixmap(idx, phys) \
61 __set_fixmap(idx, phys, PAGE_KERNEL)
62/*
63 * Some hardware wants to get fixmapped without caching.
64 */
65#define set_fixmap_nocache(idx, phys) \
66 __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
67/*
68 * used by vmalloc.c.
69 *
70 * Leave one empty page between vmalloc'ed areas and
71 * the start of the fixmap, and leave one page empty
72 * at the top of mem..
73 */
74#define FIXADDR_TOP (P4SEG - PAGE_SIZE)
75#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
76#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
77
78#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
79#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
80
81extern void __this_fixmap_does_not_exist(void);
82
83/*
84 * 'index to address' translation. If anyone tries to use the idx
85 * directly without tranlation, we catch the bug with a NULL-deference
86 * kernel oops. Illegal ranges of incoming indices are caught too.
87 */
88static inline unsigned long fix_to_virt(const unsigned int idx)
89{
90 /*
91 * this branch gets completely eliminated after inlining,
92 * except when someone tries to use fixaddr indices in an
93 * illegal way. (such as mixing up address types or using
94 * out-of-range indices).
95 *
96 * If it doesn't get removed, the linker will complain
97 * loudly with a reasonably clear error message..
98 */
99 if (idx >= __end_of_fixed_addresses)
100 __this_fixmap_does_not_exist();
101
102 return __fix_to_virt(idx);
103}
104
105static inline unsigned long virt_to_fix(const unsigned long vaddr)
106{
107 BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
108 return __virt_to_fix(vaddr);
109}
110
111#endif
diff --git a/include/asm-sh/flat.h b/include/asm-sh/flat.h
new file mode 100644
index 000000000000..f29072e1c87e
--- /dev/null
+++ b/include/asm-sh/flat.h
@@ -0,0 +1,23 @@
1/*
2 * include/asm-sh/flat.h
3 *
4 * uClinux flat-format executables
5 *
6 * Copyright (C) 2003 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive for
10 * more details.
11 */
12#ifndef __ASM_SH_FLAT_H
13#define __ASM_SH_FLAT_H
14
15#define flat_stack_align(sp) /* nothing needed */
16#define flat_argvp_envp_on_stack() 1
17#define flat_old_ram_flag(flags) (flags)
18#define flat_reloc_valid(reloc, size) ((reloc) <= (size))
19#define flat_get_addr_from_rp(rp, relval, flags) get_unaligned(rp)
20#define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp)
21#define flat_get_relocate_addr(rel) (rel)
22
23#endif /* __ASM_SH_FLAT_H */
diff --git a/include/asm-sh/floppy.h b/include/asm-sh/floppy.h
new file mode 100644
index 000000000000..f030ca08052b
--- /dev/null
+++ b/include/asm-sh/floppy.h
@@ -0,0 +1,274 @@
1/*
2 * Architecture specific parts of the Floppy driver
3 * include/asm-i386/floppy.h
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * Copyright (C) 1995
10 */
11#ifndef __ASM_SH_FLOPPY_H
12#define __ASM_SH_FLOPPY_H
13
14#include <linux/vmalloc.h>
15
16
17/*
18 * The DMA channel used by the floppy controller cannot access data at
19 * addresses >= 16MB
20 *
21 * Went back to the 1MB limit, as some people had problems with the floppy
22 * driver otherwise. It doesn't matter much for performance anyway, as most
23 * floppy accesses go through the track buffer.
24 */
25#define _CROSS_64KB(a,s,vdma) \
26(!vdma && ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64))
27
28#define CROSS_64KB(a,s) _CROSS_64KB(a,s,use_virtual_dma & 1)
29
30
31#define SW fd_routine[use_virtual_dma&1]
32#define CSW fd_routine[can_use_virtual_dma & 1]
33
34
35#define fd_inb(port) inb_p(port)
36#define fd_outb(value,port) outb_p(value,port)
37
38#define fd_request_dma() CSW._request_dma(FLOPPY_DMA,"floppy")
39#define fd_free_dma() CSW._free_dma(FLOPPY_DMA)
40#define fd_enable_irq() enable_irq(FLOPPY_IRQ)
41#define fd_disable_irq() disable_irq(FLOPPY_IRQ)
42#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL)
43#define fd_get_dma_residue() SW._get_dma_residue(FLOPPY_DMA)
44#define fd_dma_mem_alloc(size) SW._dma_mem_alloc(size)
45#define fd_dma_setup(addr, size, mode, io) SW._dma_setup(addr, size, mode, io)
46
47#define FLOPPY_CAN_FALLBACK_ON_NODMA
48
49static int virtual_dma_count;
50static int virtual_dma_residue;
51static char *virtual_dma_addr;
52static int virtual_dma_mode;
53static int doing_pdma;
54
55static void floppy_hardint(int irq, void *dev_id, struct pt_regs * regs)
56{
57 register unsigned char st;
58
59#undef TRACE_FLPY_INT
60
61#ifdef TRACE_FLPY_INT
62 static int calls=0;
63 static int bytes=0;
64 static int dma_wait=0;
65#endif
66 if(!doing_pdma) {
67 floppy_interrupt(irq, dev_id, regs);
68 return;
69 }
70
71#ifdef TRACE_FLPY_INT
72 if(!calls)
73 bytes = virtual_dma_count;
74#endif
75
76 {
77 register int lcount;
78 register char *lptr;
79
80 st = 1;
81 for(lcount=virtual_dma_count, lptr=virtual_dma_addr;
82 lcount; lcount--, lptr++) {
83 st=inb(virtual_dma_port+4) & 0xa0 ;
84 if(st != 0xa0)
85 break;
86 if(virtual_dma_mode)
87 outb_p(*lptr, virtual_dma_port+5);
88 else
89 *lptr = inb_p(virtual_dma_port+5);
90 }
91 virtual_dma_count = lcount;
92 virtual_dma_addr = lptr;
93 st = inb(virtual_dma_port+4);
94 }
95
96#ifdef TRACE_FLPY_INT
97 calls++;
98#endif
99 if(st == 0x20)
100 return;
101 if(!(st & 0x20)) {
102 virtual_dma_residue += virtual_dma_count;
103 virtual_dma_count=0;
104#ifdef TRACE_FLPY_INT
105 printk("count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n",
106 virtual_dma_count, virtual_dma_residue, calls, bytes,
107 dma_wait);
108 calls = 0;
109 dma_wait=0;
110#endif
111 doing_pdma = 0;
112 floppy_interrupt(irq, dev_id, regs);
113 return;
114 }
115#ifdef TRACE_FLPY_INT
116 if(!virtual_dma_count)
117 dma_wait++;
118#endif
119}
120
121static void fd_disable_dma(void)
122{
123 if(! (can_use_virtual_dma & 1))
124 disable_dma(FLOPPY_DMA);
125 doing_pdma = 0;
126 virtual_dma_residue += virtual_dma_count;
127 virtual_dma_count=0;
128}
129
130static int vdma_request_dma(unsigned int dmanr, const char * device_id)
131{
132 return 0;
133}
134
135static void vdma_nop(unsigned int dummy)
136{
137}
138
139
140static int vdma_get_dma_residue(unsigned int dummy)
141{
142 return virtual_dma_count + virtual_dma_residue;
143}
144
145
146static int fd_request_irq(void)
147{
148 if(can_use_virtual_dma)
149 return request_irq(FLOPPY_IRQ, floppy_hardint,SA_INTERRUPT,
150 "floppy", NULL);
151 else
152 return request_irq(FLOPPY_IRQ, floppy_interrupt,
153 SA_INTERRUPT|SA_SAMPLE_RANDOM,
154 "floppy", NULL);
155
156}
157
158static unsigned long dma_mem_alloc(unsigned long size)
159{
160 return __get_dma_pages(GFP_KERNEL,get_order(size));
161}
162
163
164static unsigned long vdma_mem_alloc(unsigned long size)
165{
166 return (unsigned long) vmalloc(size);
167
168}
169
170#define nodma_mem_alloc(size) vdma_mem_alloc(size)
171
172static void _fd_dma_mem_free(unsigned long addr, unsigned long size)
173{
174 if((unsigned int) addr >= (unsigned int) high_memory)
175 return vfree((void *)addr);
176 else
177 free_pages(addr, get_order(size));
178}
179
180#define fd_dma_mem_free(addr, size) _fd_dma_mem_free(addr, size)
181
182static void _fd_chose_dma_mode(char *addr, unsigned long size)
183{
184 if(can_use_virtual_dma == 2) {
185 if((unsigned int) addr >= (unsigned int) high_memory ||
186 virt_to_bus(addr) >= 0x10000000)
187 use_virtual_dma = 1;
188 else
189 use_virtual_dma = 0;
190 } else {
191 use_virtual_dma = can_use_virtual_dma & 1;
192 }
193}
194
195#define fd_chose_dma_mode(addr, size) _fd_chose_dma_mode(addr, size)
196
197
198static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io)
199{
200 doing_pdma = 1;
201 virtual_dma_port = io;
202 virtual_dma_mode = (mode == DMA_MODE_WRITE);
203 virtual_dma_addr = addr;
204 virtual_dma_count = size;
205 virtual_dma_residue = 0;
206 return 0;
207}
208
209static int hard_dma_setup(char *addr, unsigned long size, int mode, int io)
210{
211#ifdef FLOPPY_SANITY_CHECK
212 if (CROSS_64KB(addr, size)) {
213 printk("DMA crossing 64-K boundary %p-%p\n", addr, addr+size);
214 return -1;
215 }
216#endif
217
218 dma_cache_wback_inv(addr, size);
219
220 /* actual, physical DMA */
221 doing_pdma = 0;
222 clear_dma_ff(FLOPPY_DMA);
223 set_dma_mode(FLOPPY_DMA,mode);
224 set_dma_addr(FLOPPY_DMA,virt_to_bus(addr));
225 set_dma_count(FLOPPY_DMA,size);
226 enable_dma(FLOPPY_DMA);
227 return 0;
228}
229
230struct fd_routine_l {
231 int (*_request_dma)(unsigned int dmanr, const char * device_id);
232 void (*_free_dma)(unsigned int dmanr);
233 int (*_get_dma_residue)(unsigned int dummy);
234 unsigned long (*_dma_mem_alloc) (unsigned long size);
235 int (*_dma_setup)(char *addr, unsigned long size, int mode, int io);
236} fd_routine[] = {
237 {
238 request_dma,
239 free_dma,
240 get_dma_residue,
241 dma_mem_alloc,
242 hard_dma_setup
243 },
244 {
245 vdma_request_dma,
246 vdma_nop,
247 vdma_get_dma_residue,
248 vdma_mem_alloc,
249 vdma_dma_setup
250 }
251};
252
253
254static int FDC1 = 0x3f0;
255static int FDC2 = -1;
256
257/*
258 * Floppy types are stored in the rtc's CMOS RAM and so rtc_lock
259 * is needed to prevent corrupted CMOS RAM in case "insmod floppy"
260 * coincides with another rtc CMOS user. Paul G.
261 */
262#define FLOPPY0_TYPE (4)
263#define FLOPPY1_TYPE (0)
264
265#define N_FDC 2
266#define N_DRIVE 8
267
268#define FLOPPY_MOTOR_MASK 0xf0
269
270#define AUTO_DMA
271
272#define EXTRA_FLOPPY_PARAMS
273
274#endif /* __ASM_SH_FLOPPY_H */
diff --git a/include/asm-sh/freq.h b/include/asm-sh/freq.h
new file mode 100644
index 000000000000..2c0fde46a0ed
--- /dev/null
+++ b/include/asm-sh/freq.h
@@ -0,0 +1,29 @@
1/*
2 * include/asm-sh/freq.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11#ifndef __ASM_SH_FREQ_H
12#define __ASM_SH_FREQ_H
13#ifdef __KERNEL__
14
15#include <asm/cpu/freq.h>
16
17/* arch/sh/kernel/time.c */
18extern void get_current_frequency_divisors(unsigned int *ifc, unsigned int *pfc, unsigned int *bfc);
19
20extern unsigned int get_ifc_divisor(unsigned int value);
21extern unsigned int get_ifc_divisor(unsigned int value);
22extern unsigned int get_ifc_divisor(unsigned int value);
23
24extern unsigned int get_ifc_value(unsigned int divisor);
25extern unsigned int get_pfc_value(unsigned int divisor);
26extern unsigned int get_bfc_value(unsigned int divisor);
27
28#endif /* __KERNEL__ */
29#endif /* __ASM_SH_FREQ_H */
diff --git a/include/asm-sh/hardirq.h b/include/asm-sh/hardirq.h
new file mode 100644
index 000000000000..f2fdf0f760e5
--- /dev/null
+++ b/include/asm-sh/hardirq.h
@@ -0,0 +1,17 @@
1#ifndef __ASM_SH_HARDIRQ_H
2#define __ASM_SH_HARDIRQ_H
3
4#include <linux/config.h>
5#include <linux/threads.h>
6#include <linux/irq.h>
7
8/* entry.S is sensitive to the offsets of these fields */
9typedef struct {
10 unsigned int __softirq_pending;
11} ____cacheline_aligned irq_cpustat_t;
12
13#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
14
15extern void ack_bad_irq(unsigned int irq);
16
17#endif /* __ASM_SH_HARDIRQ_H */
diff --git a/include/asm-sh/harp/harp.h b/include/asm-sh/harp/harp.h
new file mode 100644
index 000000000000..b2fbcfae9940
--- /dev/null
+++ b/include/asm-sh/harp/harp.h
@@ -0,0 +1,43 @@
1/*
2 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
3 *
4 * May be copied or modified under the terms of the GNU General Public
5 * License. See linux/COPYING for more information.
6 *
7 * Defintions applicable to the STMicroelectronics ST40STB1 HARP and
8 * compatible boards.
9 */
10
11#if defined(CONFIG_SH_STB1_HARP)
12
13#define EPLD_BASE 0xa0800000
14
15#define EPLD_LED (EPLD_BASE+0x000c0000)
16#define EPLD_INTSTAT0 (EPLD_BASE+0x00200000)
17#define EPLD_INTSTAT1 (EPLD_BASE+0x00240000)
18#define EPLD_INTMASK0 (EPLD_BASE+0x00280000)
19#define EPLD_INTMASK1 (EPLD_BASE+0x002c0000)
20#define EPLD_PAGEADDR (EPLD_BASE+0x00300000)
21#define EPLD_REVID1 (EPLD_BASE+0x00380000)
22#define EPLD_REVID2 (EPLD_BASE+0x003c0000)
23
24#define EPLD_LED_ON 1
25#define EPLD_LED_OFF 0
26
27#elif defined(CONFIG_SH_STB1_OVERDRIVE)
28
29#define EPLD_BASE 0xa7000000
30
31#define EPLD_REVID (EPLD_BASE+0x00000000)
32#define EPLD_LED (EPLD_BASE+0x00040000)
33#define EPLD_INTMASK0 (EPLD_BASE+0x001c0000)
34#define EPLD_INTMASK1 (EPLD_BASE+0x00200000)
35#define EPLD_INTSTAT0 (EPLD_BASE+0x00240000)
36#define EPLD_INTSTAT1 (EPLD_BASE+0x00280000)
37
38#define EPLD_LED_ON 0
39#define EPLD_LED_OFF 1
40
41#else
42#error Unknown board
43#endif
diff --git a/include/asm-sh/harp/io.h b/include/asm-sh/harp/io.h
new file mode 100644
index 000000000000..68f39e0b39de
--- /dev/null
+++ b/include/asm-sh/harp/io.h
@@ -0,0 +1,10 @@
1#ifndef __ASM_SH_HARP_IO_H
2#define __ASM_SH_HARP_IO_H
3
4/*
5 * Nothing special here.. just use the generic cchip io routines.
6 */
7#include <asm/hd64465/io.h>
8
9#endif /* __ASM_SH_HARP_IO_H */
10
diff --git a/include/asm-sh/hd64461/hd64461.h b/include/asm-sh/hd64461/hd64461.h
new file mode 100644
index 000000000000..c457ca277a42
--- /dev/null
+++ b/include/asm-sh/hd64461/hd64461.h
@@ -0,0 +1,203 @@
1#ifndef __ASM_SH_HD64461
2#define __ASM_SH_HD64461
3/*
4 * $Id: hd64461.h,v 1.5 2004/03/16 00:07:51 lethal Exp $
5 * Copyright (C) 2000 YAEGASHI Takeshi
6 * Hitachi HD64461 companion chip support
7 */
8#include <linux/config.h>
9
10/* Constants for PCMCIA mappings */
11#define HD64461_PCC_WINDOW 0x01000000
12
13#define HD64461_PCC0_BASE 0xb8000000 /* area 6 */
14#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE)
15#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW)
16#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW)
17
18#define HD64461_PCC1_BASE 0xb4000000 /* area 5 */
19#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE)
20#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW)
21
22#define HD64461_STBCR 0x10000
23#define HD64461_STBCR_CKIO_STBY 0x2000
24#define HD64461_STBCR_SAFECKE_IST 0x1000
25#define HD64461_STBCR_SLCKE_IST 0x0800
26#define HD64461_STBCR_SAFECKE_OST 0x0400
27#define HD64461_STBCR_SLCKE_OST 0x0200
28#define HD64461_STBCR_SMIAST 0x0100
29#define HD64461_STBCR_SLCDST 0x0080
30#define HD64461_STBCR_SPC0ST 0x0040
31#define HD64461_STBCR_SPC1ST 0x0020
32#define HD64461_STBCR_SAFEST 0x0010
33#define HD64461_STBCR_STM0ST 0x0008
34#define HD64461_STBCR_STM1ST 0x0004
35#define HD64461_STBCR_SIRST 0x0002
36#define HD64461_STBCR_SURTST 0x0001
37
38#define HD64461_SYSCR 0x10002
39#define HD64461_SCPUCR 0x10004
40
41#define HD64461_LCDCBAR 0x11000
42#define HD64461_LCDCLOR 0x11002
43#define HD64461_LCDCCR 0x11004
44#define HD64461_LCDCCR_MOFF 0x80
45
46#define HD64461_LDR1 0x11010
47#define HD64461_LDR1_DON 0x01
48#define HD64461_LDR1_DINV 0x80
49
50#define HD64461_LDR2 0x11012
51#define HD64461_LDHNCR 0x11014
52#define HD64461_LDHNSR 0x11016
53#define HD64461_LDVNTR 0x11018
54#define HD64461_LDVNDR 0x1101a
55#define HD64461_LDVSPR 0x1101c
56#define HD64461_LDR3 0x1101e
57
58#define HD64461_CPTWAR 0x11030
59#define HD64461_CPTWDR 0x11032
60#define HD64461_CPTRAR 0x11034
61#define HD64461_CPTRDR 0x11036
62
63#define HD64461_GRDOR 0x11040
64#define HD64461_GRSCR 0x11042
65#define HD64461_GRCFGR 0x11044
66#define HD64461_GRCFGR_ACCSTATUS 0x10
67#define HD64461_GRCFGR_ACCRESET 0x08
68#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06
69#define HD64461_GRCFGR_ACCSTART_LINE 0x04
70#define HD64461_GRCFGR_COLORDEPTH16 0x01
71
72#define HD64461_LNSARH 0x11046
73#define HD64461_LNSARL 0x11048
74#define HD64461_LNAXLR 0x1104a
75#define HD64461_LNDGR 0x1104c
76#define HD64461_LNAXR 0x1104e
77#define HD64461_LNERTR 0x11050
78#define HD64461_LNMDR 0x11052
79#define HD64461_BBTSSARH 0x11054
80#define HD64461_BBTSSARL 0x11056
81#define HD64461_BBTDSARH 0x11058
82#define HD64461_BBTDSARL 0x1105a
83#define HD64461_BBTDWR 0x1105c
84#define HD64461_BBTDHR 0x1105e
85#define HD64461_BBTPARH 0x11060
86#define HD64461_BBTPARL 0x11062
87#define HD64461_BBTMARH 0x11064
88#define HD64461_BBTMARL 0x11066
89#define HD64461_BBTROPR 0x11068
90#define HD64461_BBTMDR 0x1106a
91
92/* PC Card Controller Registers */
93#define HD64461_PCC0ISR 0x12000 /* socket 0 interface status */
94#define HD64461_PCC0GCR 0x12002 /* socket 0 general control */
95#define HD64461_PCC0CSCR 0x12004 /* socket 0 card status change */
96#define HD64461_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */
97#define HD64461_PCC0SCR 0x12008 /* socket 0 software control */
98#define HD64461_PCC1ISR 0x12010 /* socket 1 interface status */
99#define HD64461_PCC1GCR 0x12012 /* socket 1 general control */
100#define HD64461_PCC1CSCR 0x12014 /* socket 1 card status change */
101#define HD64461_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */
102#define HD64461_PCC1SCR 0x12018 /* socket 1 software control */
103
104/* PCC Interface Status Register */
105#define HD64461_PCCISR_READY 0x80 /* card ready */
106#define HD64461_PCCISR_MWP 0x40 /* card write-protected */
107#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */
108#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */
109#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */
110#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */
111#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */
112#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */
113
114#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */
115#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */
116#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */
117#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */
118#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */
119#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */
120
121/* PCC General Control Register */
122#define HD64461_PCCGCR_DRVE 0x80 /* output drive */
123#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */
124#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */
125#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */
126#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */
127#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */
128#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */
129#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */
130
131/* PCC Card Status Change Register */
132#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */
133#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */
134#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */
135#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */
136#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */
137#define HD64461_PCCCSCR_RC 0x04 /* READY change */
138#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */
139#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */
140
141/* PCC Card Status Change Interrupt Enable Register */
142#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */
143#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */
144#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */
145#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */
146#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */
147#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */
148
149#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */
150#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */
151#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */
152#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */
153#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/
154
155/* PCC Software Control Register */
156#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */
157#define HD64461_PCCSCR_SWP 0x01 /* write protect */
158
159
160#define HD64461_P0OCR 0x1202a
161#define HD64461_P1OCR 0x1202c
162#define HD64461_PGCR 0x1202e
163
164#define HD64461_GPACR 0x14000
165#define HD64461_GPBCR 0x14002
166#define HD64461_GPCCR 0x14004
167#define HD64461_GPDCR 0x14006
168#define HD64461_GPADR 0x14010
169#define HD64461_GPBDR 0x14012
170#define HD64461_GPCDR 0x14014
171#define HD64461_GPDDR 0x14016
172#define HD64461_GPAICR 0x14020
173#define HD64461_GPBICR 0x14022
174#define HD64461_GPCICR 0x14024
175#define HD64461_GPDICR 0x14026
176#define HD64461_GPAISR 0x14040
177#define HD64461_GPBISR 0x14042
178#define HD64461_GPCISR 0x14044
179#define HD64461_GPDISR 0x14046
180
181#define HD64461_NIRR 0x15000
182#define HD64461_NIMR 0x15002
183
184#ifndef CONFIG_HD64461_IOBASE
185#define CONFIG_HD64461_IOBASE 0xb0000000
186#endif
187#ifndef CONFIG_HD64461_IRQ
188#define CONFIG_HD64461_IRQ 36
189#endif
190
191#define HD64461_IRQBASE OFFCHIP_IRQ_BASE
192#define HD64461_IRQ_NUM 16
193
194#define HD64461_IRQ_UART (HD64461_IRQBASE+5)
195#define HD64461_IRQ_IRDA (HD64461_IRQBASE+6)
196#define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9)
197#define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10)
198#define HD64461_IRQ_GPIO (HD64461_IRQBASE+11)
199#define HD64461_IRQ_AFE (HD64461_IRQBASE+12)
200#define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13)
201#define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14)
202
203#endif
diff --git a/include/asm-sh/hd64461/io.h b/include/asm-sh/hd64461/io.h
new file mode 100644
index 000000000000..67f2489088d9
--- /dev/null
+++ b/include/asm-sh/hd64461/io.h
@@ -0,0 +1,43 @@
1/*
2 * include/asm-sh/io_hd64461.h
3 *
4 * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * IO functions for an HD64461
10 */
11
12#ifndef _ASM_SH_IO_HD64461_H
13#define _ASM_SH_IO_HD64461_H
14
15extern unsigned char hd64461_inb(unsigned long port);
16extern unsigned short hd64461_inw(unsigned long port);
17extern unsigned int hd64461_inl(unsigned long port);
18
19extern void hd64461_outb(unsigned char value, unsigned long port);
20extern void hd64461_outw(unsigned short value, unsigned long port);
21extern void hd64461_outl(unsigned int value, unsigned long port);
22
23extern unsigned char hd64461_inb_p(unsigned long port);
24extern void hd64461_outb_p(unsigned char value, unsigned long port);
25
26extern void hd64461_insb(unsigned long port, void *addr, unsigned long count);
27extern void hd64461_insw(unsigned long port, void *addr, unsigned long count);
28extern void hd64461_insl(unsigned long port, void *addr, unsigned long count);
29
30extern void hd64461_outsb(unsigned long port, const void *buffer, unsigned long count);
31extern void hd64461_outsw(unsigned long port, const void *buffer, unsigned long count);
32extern void hd64461_outsl(unsigned long port, const void *buffer, unsigned long count);
33
34extern unsigned short hd64461_readw(unsigned long addr);
35extern void hd64461_writew(unsigned short b, unsigned long addr);
36
37
38extern int hd64461_irq_demux(int irq);
39extern void hd64461_register_irq_demux(int irq,
40 int (*demux)(int irq, void *dev), void *dev);
41extern void hd64461_unregister_irq_demux(int irq);
42
43#endif /* _ASM_SH_IO_HD64461_H */
diff --git a/include/asm-sh/hd64465/gpio.h b/include/asm-sh/hd64465/gpio.h
new file mode 100644
index 000000000000..a3cdca2713dd
--- /dev/null
+++ b/include/asm-sh/hd64465/gpio.h
@@ -0,0 +1,46 @@
1#ifndef _ASM_SH_HD64465_GPIO_
2#define _ASM_SH_HD64465_GPIO_ 1
3/*
4 * $Id: gpio.h,v 1.3 2003/05/04 19:30:14 lethal Exp $
5 *
6 * Hitachi HD64465 companion chip: General Purpose IO pins support.
7 * This layer enables other device drivers to configure GPIO
8 * pins, get and set their values, and register an interrupt
9 * routine for when input pins change in hardware.
10 *
11 * by Greg Banks <gbanks@pocketpenguins.com>
12 * (c) 2000 PocketPenguins Inc.
13 */
14#include <asm/hd64465.h>
15
16/* Macro to construct a portpin number (used in all
17 * subsequent functions) from a port letter and a pin
18 * number, e.g. HD64465_GPIO_PORTPIN('A', 5).
19 */
20#define HD64465_GPIO_PORTPIN(port,pin) (((port)-'A')<<3|(pin))
21
22/* Pin configuration constants for _configure() */
23#define HD64465_GPIO_FUNCTION2 0 /* use the pin's *other* function */
24#define HD64465_GPIO_OUT 1 /* output */
25#define HD64465_GPIO_IN_PULLUP 2 /* input, pull-up MOS on */
26#define HD64465_GPIO_IN 3 /* input */
27
28/* Configure a pin's direction */
29extern void hd64465_gpio_configure(int portpin, int direction);
30
31/* Get, set value */
32extern void hd64465_gpio_set_pin(int portpin, unsigned int value);
33extern unsigned int hd64465_gpio_get_pin(int portpin);
34extern void hd64465_gpio_set_port(int port, unsigned int value);
35extern unsigned int hd64465_gpio_get_port(int port);
36
37/* mode constants for _register_irq() */
38#define HD64465_GPIO_FALLING 0
39#define HD64465_GPIO_RISING 1
40
41/* Interrupt on external value change */
42extern void hd64465_gpio_register_irq(int portpin, int mode,
43 void (*handler)(int portpin, void *dev), void *dev);
44extern void hd64465_gpio_unregister_irq(int portpin);
45
46#endif /* _ASM_SH_HD64465_GPIO_ */
diff --git a/include/asm-sh/hd64465/hd64465.h b/include/asm-sh/hd64465/hd64465.h
new file mode 100644
index 000000000000..c672032b72c9
--- /dev/null
+++ b/include/asm-sh/hd64465/hd64465.h
@@ -0,0 +1,257 @@
1#ifndef _ASM_SH_HD64465_
2#define _ASM_SH_HD64465_ 1
3/*
4 * $Id: hd64465.h,v 1.3 2003/05/04 19:30:15 lethal Exp $
5 *
6 * Hitachi HD64465 companion chip support
7 *
8 * by Greg Banks <gbanks@pocketpenguins.com>
9 * (c) 2000 PocketPenguins Inc.
10 *
11 * Derived from <asm/hd64461.h> which bore the message:
12 * Copyright (C) 2000 YAEGASHI Takeshi
13 */
14#include <linux/config.h>
15#include <asm/io.h>
16#include <asm/irq.h>
17
18/*
19 * Note that registers are defined here as virtual port numbers,
20 * which have no meaning except to get translated by hd64465_isa_port2addr()
21 * to an address in the range 0xb0000000-0xb3ffffff. Note that
22 * this translation happens to consist of adding the lower 16 bits
23 * of the virtual port number to 0xb0000000. Note also that the manual
24 * shows addresses as absolute physical addresses starting at 0x10000000,
25 * so e.g. the NIRR register is listed as 0x15000 here, 0x10005000 in the
26 * manual, and accessed using address 0xb0005000 - Greg.
27 */
28
29/* System registers */
30#define HD64465_REG_SRR 0x1000c /* System Revision Register */
31#define HD64465_REG_SDID 0x10010 /* System Device ID Reg */
32#define HD64465_SDID 0x8122 /* 64465 device ID */
33
34/* Power Management registers */
35#define HD64465_REG_SMSCR 0x10000 /* System Module Standby Control Reg */
36#define HD64465_SMSCR_PS2ST 0x4000 /* PS/2 Standby */
37#define HD64465_SMSCR_ADCST 0x1000 /* ADC Standby */
38#define HD64465_SMSCR_UARTST 0x0800 /* UART Standby */
39#define HD64465_SMSCR_SCDIST 0x0200 /* Serial Codec Standby */
40#define HD64465_SMSCR_PPST 0x0100 /* Parallel Port Standby */
41#define HD64465_SMSCR_PC0ST 0x0040 /* PCMCIA0 Standby */
42#define HD64465_SMSCR_PC1ST 0x0020 /* PCMCIA1 Standby */
43#define HD64465_SMSCR_AFEST 0x0010 /* AFE Standby */
44#define HD64465_SMSCR_TM0ST 0x0008 /* Timer0 Standby */
45#define HD64465_SMSCR_TM1ST 0x0004 /* Timer1 Standby */
46#define HD64465_SMSCR_IRDAST 0x0002 /* IRDA Standby */
47#define HD64465_SMSCR_KBCST 0x0001 /* Keyboard Controller Standby */
48
49/* Interrupt Controller registers */
50#define HD64465_REG_NIRR 0x15000 /* Interrupt Request Register */
51#define HD64465_REG_NIMR 0x15002 /* Interrupt Mask Register */
52#define HD64465_REG_NITR 0x15004 /* Interrupt Trigger Mode Register */
53
54/* Timer registers */
55#define HD64465_REG_TCVR1 0x16000 /* Timer 1 constant value register */
56#define HD64465_REG_TCVR0 0x16002 /* Timer 0 constant value register */
57#define HD64465_REG_TRVR1 0x16004 /* Timer 1 read value register */
58#define HD64465_REG_TRVR0 0x16006 /* Timer 0 read value register */
59#define HD64465_REG_TCR1 0x16008 /* Timer 1 control register */
60#define HD64465_REG_TCR0 0x1600A /* Timer 0 control register */
61#define HD64465_TCR_EADT 0x10 /* Enable ADTRIG# signal */
62#define HD64465_TCR_ETMO 0x08 /* Enable TMO signal */
63#define HD64465_TCR_PST_MASK 0x06 /* Clock Prescale */
64#define HD64465_TCR_PST_1 0x06 /* 1:1 */
65#define HD64465_TCR_PST_4 0x04 /* 1:4 */
66#define HD64465_TCR_PST_8 0x02 /* 1:8 */
67#define HD64465_TCR_PST_16 0x00 /* 1:16 */
68#define HD64465_TCR_TSTP 0x01 /* Start/Stop timer */
69#define HD64465_REG_TIRR 0x1600C /* Timer interrupt request register */
70#define HD64465_REG_TIDR 0x1600E /* Timer interrupt disable register */
71#define HD64465_REG_PWM1CS 0x16010 /* PWM 1 clock scale register */
72#define HD64465_REG_PWM1LPC 0x16012 /* PWM 1 low pulse width counter register */
73#define HD64465_REG_PWM1HPC 0x16014 /* PWM 1 high pulse width counter register */
74#define HD64465_REG_PWM0CS 0x16018 /* PWM 0 clock scale register */
75#define HD64465_REG_PWM0LPC 0x1601A /* PWM 0 low pulse width counter register */
76#define HD64465_REG_PWM0HPC 0x1601C /* PWM 0 high pulse width counter register */
77
78/* Analog/Digital Converter registers */
79#define HD64465_REG_ADDRA 0x1E000 /* A/D data register A */
80#define HD64465_REG_ADDRB 0x1E002 /* A/D data register B */
81#define HD64465_REG_ADDRC 0x1E004 /* A/D data register C */
82#define HD64465_REG_ADDRD 0x1E006 /* A/D data register D */
83#define HD64465_REG_ADCSR 0x1E008 /* A/D control/status register */
84#define HD64465_ADCSR_ADF 0x80 /* A/D End Flag */
85#define HD64465_ADCSR_ADST 0x40 /* A/D Start Flag */
86#define HD64465_ADCSR_ADIS 0x20 /* A/D Interrupt Status */
87#define HD64465_ADCSR_TRGE 0x10 /* A/D Trigger Enable */
88#define HD64465_ADCSR_ADIE 0x08 /* A/D Interrupt Enable */
89#define HD64465_ADCSR_SCAN 0x04 /* A/D Scan Mode */
90#define HD64465_ADCSR_CH_MASK 0x03 /* A/D Channel */
91#define HD64465_REG_ADCALCR 0x1E00A /* A/D calibration sample control */
92#define HD64465_REG_ADCAL 0x1E00C /* A/D calibration data register */
93
94
95/* General Purpose I/O ports registers */
96#define HD64465_REG_GPACR 0x14000 /* Port A Control Register */
97#define HD64465_REG_GPBCR 0x14002 /* Port B Control Register */
98#define HD64465_REG_GPCCR 0x14004 /* Port C Control Register */
99#define HD64465_REG_GPDCR 0x14006 /* Port D Control Register */
100#define HD64465_REG_GPECR 0x14008 /* Port E Control Register */
101#define HD64465_REG_GPADR 0x14010 /* Port A Data Register */
102#define HD64465_REG_GPBDR 0x14012 /* Port B Data Register */
103#define HD64465_REG_GPCDR 0x14014 /* Port C Data Register */
104#define HD64465_REG_GPDDR 0x14016 /* Port D Data Register */
105#define HD64465_REG_GPEDR 0x14018 /* Port E Data Register */
106#define HD64465_REG_GPAICR 0x14020 /* Port A Interrupt Control Register */
107#define HD64465_REG_GPBICR 0x14022 /* Port B Interrupt Control Register */
108#define HD64465_REG_GPCICR 0x14024 /* Port C Interrupt Control Register */
109#define HD64465_REG_GPDICR 0x14026 /* Port D Interrupt Control Register */
110#define HD64465_REG_GPEICR 0x14028 /* Port E Interrupt Control Register */
111#define HD64465_REG_GPAISR 0x14040 /* Port A Interrupt Status Register */
112#define HD64465_REG_GPBISR 0x14042 /* Port B Interrupt Status Register */
113#define HD64465_REG_GPCISR 0x14044 /* Port C Interrupt Status Register */
114#define HD64465_REG_GPDISR 0x14046 /* Port D Interrupt Status Register */
115#define HD64465_REG_GPEISR 0x14048 /* Port E Interrupt Status Register */
116
117/* PCMCIA bridge interface */
118#define HD64465_REG_PCC0ISR 0x12000 /* socket 0 interface status */
119#define HD64465_PCCISR_PREADY 0x80 /* mem card ready / io card IREQ */
120#define HD64465_PCCISR_PIREQ 0x80
121#define HD64465_PCCISR_PMWP 0x40 /* mem card write-protected */
122#define HD64465_PCCISR_PVS2 0x20 /* voltage select pin 2 */
123#define HD64465_PCCISR_PVS1 0x10 /* voltage select pin 1 */
124#define HD64465_PCCISR_PCD_MASK 0x0c /* card detect */
125#define HD64465_PCCISR_PBVD_MASK 0x03 /* battery voltage */
126#define HD64465_PCCISR_PBVD_BATGOOD 0x03 /* battery good */
127#define HD64465_PCCISR_PBVD_BATWARN 0x01 /* battery low warning */
128#define HD64465_PCCISR_PBVD_BATDEAD1 0x02 /* battery dead */
129#define HD64465_PCCISR_PBVD_BATDEAD2 0x00 /* battery dead */
130#define HD64465_REG_PCC0GCR 0x12002 /* socket 0 general control */
131#define HD64465_PCCGCR_PDRV 0x80 /* output drive */
132#define HD64465_PCCGCR_PCCR 0x40 /* PC card reset */
133#define HD64465_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */
134#define HD64465_PCCGCR_PVCC0 0x10 /* voltage control pin VCC0SEL0 */
135#define HD64465_PCCGCR_PMMOD 0x08 /* memory mode */
136#define HD64465_PCCGCR_PPA25 0x04 /* pin A25 */
137#define HD64465_PCCGCR_PPA24 0x02 /* pin A24 */
138#define HD64465_PCCGCR_PREG 0x01 /* ping PCC0REG# */
139#define HD64465_REG_PCC0CSCR 0x12004 /* socket 0 card status change */
140#define HD64465_PCCCSCR_PSCDI 0x80 /* sw card detect intr */
141#define HD64465_PCCCSCR_PSWSEL 0x40 /* power select */
142#define HD64465_PCCCSCR_PIREQ 0x20 /* IREQ intr req */
143#define HD64465_PCCCSCR_PSC 0x10 /* STSCHG (status change) pin */
144#define HD64465_PCCCSCR_PCDC 0x08 /* CD (card detect) change */
145#define HD64465_PCCCSCR_PRC 0x04 /* ready change */
146#define HD64465_PCCCSCR_PBW 0x02 /* battery warning change */
147#define HD64465_PCCCSCR_PBD 0x01 /* battery dead change */
148#define HD64465_REG_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */
149#define HD64465_PCCCSCIER_PCRE 0x80 /* change reset enable */
150#define HD64465_PCCCSCIER_PIREQE_MASK 0x60 /* IREQ enable */
151#define HD64465_PCCCSCIER_PIREQE_DISABLED 0x00 /* IREQ disabled */
152#define HD64465_PCCCSCIER_PIREQE_LEVEL 0x20 /* IREQ level-triggered */
153#define HD64465_PCCCSCIER_PIREQE_FALLING 0x40 /* IREQ falling-edge-trig */
154#define HD64465_PCCCSCIER_PIREQE_RISING 0x60 /* IREQ rising-edge-trig */
155#define HD64465_PCCCSCIER_PSCE 0x10 /* status change enable */
156#define HD64465_PCCCSCIER_PCDE 0x08 /* card detect change enable */
157#define HD64465_PCCCSCIER_PRE 0x04 /* ready change enable */
158#define HD64465_PCCCSCIER_PBWE 0x02 /* battery warn change enable */
159#define HD64465_PCCCSCIER_PBDE 0x01 /* battery dead change enable*/
160#define HD64465_REG_PCC0SCR 0x12008 /* socket 0 software control */
161#define HD64465_PCCSCR_SHDN 0x10 /* TPS2206 SHutDowN pin */
162#define HD64465_PCCSCR_SWP 0x01 /* write protect */
163#define HD64465_REG_PCCPSR 0x1200A /* serial power switch control */
164#define HD64465_REG_PCC1ISR 0x12010 /* socket 1 interface status */
165#define HD64465_REG_PCC1GCR 0x12012 /* socket 1 general control */
166#define HD64465_REG_PCC1CSCR 0x12014 /* socket 1 card status change */
167#define HD64465_REG_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */
168#define HD64465_REG_PCC1SCR 0x12018 /* socket 1 software control */
169
170
171/* PS/2 Keyboard and mouse controller -- *not* register compatible */
172#define HD64465_REG_KBCSR 0x1dc00 /* Keyboard Control/Status reg */
173#define HD64465_KBCSR_KBCIE 0x8000 /* KBCK Input Enable */
174#define HD64465_KBCSR_KBCOE 0x4000 /* KBCK Output Enable */
175#define HD64465_KBCSR_KBDOE 0x2000 /* KB DATA Output Enable */
176#define HD64465_KBCSR_KBCD 0x1000 /* KBCK Driven */
177#define HD64465_KBCSR_KBDD 0x0800 /* KB DATA Driven */
178#define HD64465_KBCSR_KBCS 0x0400 /* KBCK pin Status */
179#define HD64465_KBCSR_KBDS 0x0200 /* KB DATA pin Status */
180#define HD64465_KBCSR_KBDP 0x0100 /* KB DATA Parity bit */
181#define HD64465_KBCSR_KBD_MASK 0x00ff /* KD DATA shift reg */
182#define HD64465_REG_KBISR 0x1dc04 /* Keyboard Interrupt Status reg */
183#define HD64465_KBISR_KBRDF 0x0001 /* KB Received Data Full */
184#define HD64465_REG_MSCSR 0x1dc10 /* Mouse Control/Status reg */
185#define HD64465_REG_MSISR 0x1dc14 /* Mouse Interrupt Status reg */
186
187
188/*
189 * Logical address at which the HD64465 is mapped. Note that this
190 * should always be in the P2 segment (uncached and untranslated).
191 */
192#ifndef CONFIG_HD64465_IOBASE
193#define CONFIG_HD64465_IOBASE 0xb0000000
194#endif
195/*
196 * The HD64465 multiplexes all its modules' interrupts onto
197 * this single interrupt.
198 */
199#ifndef CONFIG_HD64465_IRQ
200#define CONFIG_HD64465_IRQ 5
201#endif
202
203
204#define _HD64465_IO_MASK 0xf8000000
205#define is_hd64465_addr(addr) \
206 ((addr & _HD64465_IO_MASK) == (CONFIG_HD64465_IOBASE & _HD64465_IO_MASK))
207
208/*
209 * A range of 16 virtual interrupts generated by
210 * demuxing the HD64465 muxed interrupt.
211 */
212#define HD64465_IRQ_BASE OFFCHIP_IRQ_BASE
213#define HD64465_IRQ_NUM 16
214#define HD64465_IRQ_ADC (HD64465_IRQ_BASE+0)
215#define HD64465_IRQ_USB (HD64465_IRQ_BASE+1)
216#define HD64465_IRQ_SCDI (HD64465_IRQ_BASE+2)
217#define HD64465_IRQ_PARALLEL (HD64465_IRQ_BASE+3)
218/* bit 4 is reserved */
219#define HD64465_IRQ_UART (HD64465_IRQ_BASE+5)
220#define HD64465_IRQ_IRDA (HD64465_IRQ_BASE+6)
221#define HD64465_IRQ_PS2MOUSE (HD64465_IRQ_BASE+7)
222#define HD64465_IRQ_KBC (HD64465_IRQ_BASE+8)
223#define HD64465_IRQ_TIMER1 (HD64465_IRQ_BASE+9)
224#define HD64465_IRQ_TIMER0 (HD64465_IRQ_BASE+10)
225#define HD64465_IRQ_GPIO (HD64465_IRQ_BASE+11)
226#define HD64465_IRQ_AFE (HD64465_IRQ_BASE+12)
227#define HD64465_IRQ_PCMCIA1 (HD64465_IRQ_BASE+13)
228#define HD64465_IRQ_PCMCIA0 (HD64465_IRQ_BASE+14)
229#define HD64465_IRQ_PS2KBD (HD64465_IRQ_BASE+15)
230
231/* Constants for PCMCIA mappings */
232#define HD64465_PCC_WINDOW 0x01000000
233
234#define HD64465_PCC0_BASE 0xb8000000 /* area 6 */
235#define HD64465_PCC0_ATTR (HD64465_PCC0_BASE)
236#define HD64465_PCC0_COMM (HD64465_PCC0_BASE+HD64465_PCC_WINDOW)
237#define HD64465_PCC0_IO (HD64465_PCC0_BASE+2*HD64465_PCC_WINDOW)
238
239#define HD64465_PCC1_BASE 0xb4000000 /* area 5 */
240#define HD64465_PCC1_ATTR (HD64465_PCC1_BASE)
241#define HD64465_PCC1_COMM (HD64465_PCC1_BASE+HD64465_PCC_WINDOW)
242#define HD64465_PCC1_IO (HD64465_PCC1_BASE+2*HD64465_PCC_WINDOW)
243
244/*
245 * Base of USB controller interface (as memory)
246 */
247#define HD64465_USB_BASE (CONFIG_HD64465_IOBASE+0xb000)
248#define HD64465_USB_LEN 0x1000
249/*
250 * Base of embedded SRAM, used for USB controller.
251 */
252#define HD64465_SRAM_BASE (CONFIG_HD64465_IOBASE+0x9000)
253#define HD64465_SRAM_LEN 0x1000
254
255
256
257#endif /* _ASM_SH_HD64465_ */
diff --git a/include/asm-sh/hd64465/io.h b/include/asm-sh/hd64465/io.h
new file mode 100644
index 000000000000..1100bcf4968e
--- /dev/null
+++ b/include/asm-sh/hd64465/io.h
@@ -0,0 +1,44 @@
1/*
2 * include/asm-sh/io_hd64465.h
3 *
4 * By Greg Banks <gbanks@pocketpenguins.com>
5 * (c) 2000 PocketPenguins Inc.
6 *
7 * Derived from io_hd64461.h, which bore the message:
8 * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
9 *
10 * May be copied or modified under the terms of the GNU General Public
11 * License. See linux/COPYING for more information.
12 *
13 * IO functions for an HD64465 "Windows CE Intelligent Peripheral Controller".
14 */
15
16#ifndef _ASM_SH_IO_HD64465_H
17#define _ASM_SH_IO_HD64465_H
18
19extern unsigned char hd64465_inb(unsigned long port);
20extern unsigned short hd64465_inw(unsigned long port);
21extern unsigned int hd64465_inl(unsigned long port);
22
23extern void hd64465_outb(unsigned char value, unsigned long port);
24extern void hd64465_outw(unsigned short value, unsigned long port);
25extern void hd64465_outl(unsigned int value, unsigned long port);
26
27extern unsigned char hd64465_inb_p(unsigned long port);
28extern void hd64465_outb_p(unsigned char value, unsigned long port);
29
30extern unsigned long hd64465_isa_port2addr(unsigned long offset);
31extern int hd64465_irq_demux(int irq);
32/* Provision for generic secondary demux step -- used by PCMCIA code */
33extern void hd64465_register_irq_demux(int irq,
34 int (*demux)(int irq, void *dev), void *dev);
35extern void hd64465_unregister_irq_demux(int irq);
36/* Set this variable to 1 to see port traffic */
37extern int hd64465_io_debug;
38/* Map a range of ports to a range of kernel virtual memory.
39 */
40extern void hd64465_port_map(unsigned short baseport, unsigned int nports,
41 unsigned long addr, unsigned char shift);
42extern void hd64465_port_unmap(unsigned short baseport, unsigned int nports);
43
44#endif /* _ASM_SH_IO_HD64465_H */
diff --git a/include/asm-sh/hdreg.h b/include/asm-sh/hdreg.h
new file mode 100644
index 000000000000..7f7fd1af0af3
--- /dev/null
+++ b/include/asm-sh/hdreg.h
@@ -0,0 +1 @@
#include <asm-generic/hdreg.h>
diff --git a/include/asm-sh/hp6xx/hp6xx.h b/include/asm-sh/hp6xx/hp6xx.h
new file mode 100644
index 000000000000..a26247fd3d87
--- /dev/null
+++ b/include/asm-sh/hp6xx/hp6xx.h
@@ -0,0 +1,31 @@
1#ifndef __ASM_SH_HP6XX_H
2#define __ASM_SH_HP6XX_H
3
4/*
5 * Copyright (C) 2003 Andriy Skulysh
6 */
7
8#define HP680_TS_IRQ IRQ3_IRQ
9
10#define DAC_LCD_BRIGHTNESS 0
11#define DAC_SPEAKER_VOLUME 1
12
13#define PHDR_TS_PEN_DOWN 0x08
14
15#define SCPDR_TS_SCAN_ENABLE 0x20
16#define SCPDR_TS_SCAN_Y 0x02
17#define SCPDR_TS_SCAN_X 0x01
18
19#define SCPCR_TS_ENABLE 0x405
20#define SCPCR_TS_MASK 0xc0f
21
22#define ADC_CHANNEL_TS_Y 1
23#define ADC_CHANNEL_TS_X 2
24
25#define HD64461_GPADR_SPEAKER 0x01
26#define HD64461_GPADR_PCMCIA0 (0x02|0x08)
27#define HD64461_GPBDR_LCDOFF 0x01
28#define HD64461_GPBDR_LED_RED 0x80
29
30
31#endif /* __ASM_SH_HP6XX_H */
diff --git a/include/asm-sh/hp6xx/ide.h b/include/asm-sh/hp6xx/ide.h
new file mode 100644
index 000000000000..570395a5ebe5
--- /dev/null
+++ b/include/asm-sh/hp6xx/ide.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_SH_HP6XX_IDE_H
2#define __ASM_SH_HP6XX_IDE_H
3
4#define IRQ_CFCARD 93
5#define IRQ_PCMCIA 94
6
7#endif /* __ASM_SH_HP6XX_IDE_H */
8
diff --git a/include/asm-sh/hp6xx/io.h b/include/asm-sh/hp6xx/io.h
new file mode 100644
index 000000000000..731798003550
--- /dev/null
+++ b/include/asm-sh/hp6xx/io.h
@@ -0,0 +1,10 @@
1#ifndef __ASM_SH_HP6XX_IO_H
2#define __ASM_SH_HP6XX_IO_H
3
4/*
5 * Nothing special here.. just use the generic cchip io routines.
6 */
7#include <asm/hd64461/io.h>
8
9#endif /* __ASM_SH_HP6XX_IO_H */
10
diff --git a/include/asm-sh/hs7751rvoip/hs7751rvoip.h b/include/asm-sh/hs7751rvoip/hs7751rvoip.h
new file mode 100644
index 000000000000..5f995f937a44
--- /dev/null
+++ b/include/asm-sh/hs7751rvoip/hs7751rvoip.h
@@ -0,0 +1,47 @@
1#ifndef __ASM_SH_RENESAS_HS7751RVOIP_H
2#define __ASM_SH_RENESAS_HS7751RVOIP_H
3
4/*
5 * linux/include/asm-sh/hs7751rvoip/hs7751rvoip.h
6 *
7 * Copyright (C) 2000 Atom Create Engineering Co., Ltd.
8 *
9 * Renesas Technology Sales HS7751RVoIP support
10 */
11
12/* Box specific addresses. */
13
14#define PA_BCR 0xa4000000 /* FPGA */
15#define PA_SLICCNTR1 0xa4000006 /* SLIC PIO Control 1 */
16#define PA_SLICCNTR2 0xa4000008 /* SLIC PIO Control 2 */
17#define PA_DMACNTR 0xa400000a /* USB DMA Control */
18#define PA_INPORTR 0xa400000c /* Input Port Register */
19#define PA_OUTPORTR 0xa400000e /* Output Port Reguster */
20#define PA_VERREG 0xa4000014 /* FPGA Version Register */
21
22#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
23#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
24#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
25
26#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
27#define IRLCNTR2 (PA_BCR + 2) /* Interrupt Control Register2 */
28#define IRLCNTR3 (PA_BCR + 4) /* Interrupt Control Register3 */
29#define IRLCNTR4 (PA_BCR + 16) /* Interrupt Control Register4 */
30#define IRLCNTR5 (PA_BCR + 18) /* Interrupt Control Register5 */
31
32#define IRQ_PCIETH 6 /* PCI Ethernet IRQ */
33#define IRQ_PCIHUB 7 /* PCI Ethernet Hub IRQ */
34#define IRQ_USBCOM 8 /* USB Comunication IRQ */
35#define IRQ_USBCON 9 /* USB Connect IRQ */
36#define IRQ_USBDMA 10 /* USB DMA IRQ */
37#define IRQ_CFCARD 11 /* CF Card IRQ */
38#define IRQ_PCMCIA 12 /* PCMCIA IRQ */
39#define IRQ_PCISLOT 13 /* PCI Slot #1 IRQ */
40#define IRQ_ONHOOK1 0 /* ON HOOK1 IRQ */
41#define IRQ_OFFHOOK1 1 /* OFF HOOK1 IRQ */
42#define IRQ_ONHOOK2 2 /* ON HOOK2 IRQ */
43#define IRQ_OFFHOOK2 3 /* OFF HOOK2 IRQ */
44#define IRQ_RINGING 4 /* Ringing IRQ */
45#define IRQ_CODEC 5 /* CODEC IRQ */
46
47#endif /* __ASM_SH_RENESAS_HS7751RVOIP */
diff --git a/include/asm-sh/hs7751rvoip/ide.h b/include/asm-sh/hs7751rvoip/ide.h
new file mode 100644
index 000000000000..65ad1d0f763b
--- /dev/null
+++ b/include/asm-sh/hs7751rvoip/ide.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_SH_HS7751RVOIP_IDE_H
2#define __ASM_SH_HS7751RVOIP_IDE_H
3
4/* Nothing to see here.. */
5#include <asm/hs7751rvoip/hs7751rvoip.h>
6
7#endif /* __ASM_SH_HS7751RVOIP_IDE_H */
8
diff --git a/include/asm-sh/hs7751rvoip/io.h b/include/asm-sh/hs7751rvoip/io.h
new file mode 100644
index 000000000000..513c8514001b
--- /dev/null
+++ b/include/asm-sh/hs7751rvoip/io.h
@@ -0,0 +1,39 @@
1/*
2 * include/asm-sh/hs7751rvoip/hs7751rvoip.h
3 *
4 * Modified version of io_se.h for the hs7751rvoip-specific functions.
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * IO functions for an Renesas Technology sales HS7751RVOIP
10 */
11
12#ifndef _ASM_SH_IO_HS7751RVOIP_H
13#define _ASM_SH_IO_HS7751RVOIP_H
14
15#include <asm/io_generic.h>
16
17extern unsigned char hs7751rvoip_inb(unsigned long port);
18extern unsigned short hs7751rvoip_inw(unsigned long port);
19extern unsigned int hs7751rvoip_inl(unsigned long port);
20
21extern void hs7751rvoip_outb(unsigned char value, unsigned long port);
22extern void hs7751rvoip_outw(unsigned short value, unsigned long port);
23extern void hs7751rvoip_outl(unsigned int value, unsigned long port);
24
25extern unsigned char hs7751rvoip_inb_p(unsigned long port);
26extern void hs7751rvoip_outb_p(unsigned char value, unsigned long port);
27
28extern void hs7751rvoip_insb(unsigned long port, void *addr, unsigned long count);
29extern void hs7751rvoip_insw(unsigned long port, void *addr, unsigned long count);
30extern void hs7751rvoip_insl(unsigned long port, void *addr, unsigned long count);
31extern void hs7751rvoip_outsb(unsigned long port, const void *addr, unsigned long count);
32extern void hs7751rvoip_outsw(unsigned long port, const void *addr, unsigned long count);
33extern void hs7751rvoip_outsl(unsigned long port, const void *addr, unsigned long count);
34
35extern void *hs7751rvoip_ioremap(unsigned long offset, unsigned long size);
36
37extern unsigned long hs7751rvoip_isa_port2addr(unsigned long offset);
38
39#endif /* _ASM_SH_IO_HS7751RVOIP_H */
diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
new file mode 100644
index 000000000000..1d934fb2c581
--- /dev/null
+++ b/include/asm-sh/hw_irq.h
@@ -0,0 +1,9 @@
1#ifndef __ASM_SH_HW_IRQ_H
2#define __ASM_SH_HW_IRQ_H
3
4static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i)
5{
6 /* Nothing to do */
7}
8
9#endif /* __ASM_SH_HW_IRQ_H */
diff --git a/include/asm-sh/ide.h b/include/asm-sh/ide.h
new file mode 100644
index 000000000000..f42cf3977a57
--- /dev/null
+++ b/include/asm-sh/ide.h
@@ -0,0 +1,29 @@
1/*
2 * linux/include/asm-sh/ide.h
3 *
4 * Copyright (C) 1994-1996 Linus Torvalds & authors
5 */
6
7/*
8 * This file contains the i386 architecture specific IDE code.
9 * In future, SuperH code.
10 */
11
12#ifndef __ASM_SH_IDE_H
13#define __ASM_SH_IDE_H
14
15#ifdef __KERNEL__
16
17#include <linux/config.h>
18
19#ifndef MAX_HWIFS
20#define MAX_HWIFS CONFIG_IDE_MAX_HWIFS
21#endif
22
23#define ide_default_io_ctl(base) (0)
24
25#include <asm-generic/ide_iops.h>
26
27#endif /* __KERNEL__ */
28
29#endif /* __ASM_SH_IDE_H */
diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h
new file mode 100644
index 000000000000..6bc343fee7a0
--- /dev/null
+++ b/include/asm-sh/io.h
@@ -0,0 +1,311 @@
1#ifndef __ASM_SH_IO_H
2#define __ASM_SH_IO_H
3
4/*
5 * Convention:
6 * read{b,w,l}/write{b,w,l} are for PCI,
7 * while in{b,w,l}/out{b,w,l} are for ISA
8 * These may (will) be platform specific function.
9 * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
10 * and 'string' versions: ins{b,w,l}/outs{b,w,l}
11 * For read{b,w,l} and write{b,w,l} there are also __raw versions, which
12 * do not have a memory barrier after them.
13 *
14 * In addition, we have
15 * ctrl_in{b,w,l}/ctrl_out{b,w,l} for SuperH specific I/O.
16 * which are processor specific.
17 */
18
19/*
20 * We follow the Alpha convention here:
21 * __inb expands to an inline function call (which calls via the mv)
22 * _inb is a real function call (note ___raw fns are _ version of __raw)
23 * inb by default expands to _inb, but the machine specific code may
24 * define it to __inb if it chooses.
25 */
26
27#include <asm/cache.h>
28#include <asm/system.h>
29#include <asm/addrspace.h>
30#include <asm/machvec.h>
31#include <linux/config.h>
32
33/*
34 * Depending on which platform we are running on, we need different
35 * I/O functions.
36 */
37
38#ifdef __KERNEL__
39/*
40 * Since boards are able to define their own set of I/O routines through
41 * their respective machine vector, we always wrap through the mv.
42 *
43 * Also, in the event that a board hasn't provided its own definition for
44 * a given routine, it will be wrapped to generic code at run-time.
45 */
46
47# define __inb(p) sh_mv.mv_inb((p))
48# define __inw(p) sh_mv.mv_inw((p))
49# define __inl(p) sh_mv.mv_inl((p))
50# define __outb(x,p) sh_mv.mv_outb((x),(p))
51# define __outw(x,p) sh_mv.mv_outw((x),(p))
52# define __outl(x,p) sh_mv.mv_outl((x),(p))
53
54# define __inb_p(p) sh_mv.mv_inb_p((p))
55# define __inw_p(p) sh_mv.mv_inw_p((p))
56# define __inl_p(p) sh_mv.mv_inl_p((p))
57# define __outb_p(x,p) sh_mv.mv_outb_p((x),(p))
58# define __outw_p(x,p) sh_mv.mv_outw_p((x),(p))
59# define __outl_p(x,p) sh_mv.mv_outl_p((x),(p))
60
61# define __insb(p,b,c) sh_mv.mv_insb((p), (b), (c))
62# define __insw(p,b,c) sh_mv.mv_insw((p), (b), (c))
63# define __insl(p,b,c) sh_mv.mv_insl((p), (b), (c))
64# define __outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c))
65# define __outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c))
66# define __outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c))
67
68# define __readb(a) sh_mv.mv_readb((a))
69# define __readw(a) sh_mv.mv_readw((a))
70# define __readl(a) sh_mv.mv_readl((a))
71# define __writeb(v,a) sh_mv.mv_writeb((v),(a))
72# define __writew(v,a) sh_mv.mv_writew((v),(a))
73# define __writel(v,a) sh_mv.mv_writel((v),(a))
74
75# define __ioremap(a,s) sh_mv.mv_ioremap((a), (s))
76# define __iounmap(a) sh_mv.mv_iounmap((a))
77
78# define __isa_port2addr(a) sh_mv.mv_isa_port2addr(a)
79
80# define inb __inb
81# define inw __inw
82# define inl __inl
83# define outb __outb
84# define outw __outw
85# define outl __outl
86
87# define inb_p __inb_p
88# define inw_p __inw_p
89# define inl_p __inl_p
90# define outb_p __outb_p
91# define outw_p __outw_p
92# define outl_p __outl_p
93
94# define insb __insb
95# define insw __insw
96# define insl __insl
97# define outsb __outsb
98# define outsw __outsw
99# define outsl __outsl
100
101# define __raw_readb __readb
102# define __raw_readw __readw
103# define __raw_readl __readl
104# define __raw_writeb __writeb
105# define __raw_writew __writew
106# define __raw_writel __writel
107
108/*
109 * The platform header files may define some of these macros to use
110 * the inlined versions where appropriate. These macros may also be
111 * redefined by userlevel programs.
112 */
113#ifdef __raw_readb
114# define readb(a) ({ unsigned long r_ = __raw_readb((unsigned long)a); mb(); r_; })
115#endif
116#ifdef __raw_readw
117# define readw(a) ({ unsigned long r_ = __raw_readw((unsigned long)a); mb(); r_; })
118#endif
119#ifdef __raw_readl
120# define readl(a) ({ unsigned long r_ = __raw_readl((unsigned long)a); mb(); r_; })
121#endif
122
123#ifdef __raw_writeb
124# define writeb(v,a) ({ __raw_writeb((v),(unsigned long)(a)); mb(); })
125#endif
126#ifdef __raw_writew
127# define writew(v,a) ({ __raw_writew((v),(unsigned long)(a)); mb(); })
128#endif
129#ifdef __raw_writel
130# define writel(v,a) ({ __raw_writel((v),(unsigned long)(a)); mb(); })
131#endif
132
133#define readb_relaxed(a) readb(a)
134#define readw_relaxed(a) readw(a)
135#define readl_relaxed(a) readl(a)
136
137#define mmiowb()
138
139/*
140 * If the platform has PC-like I/O, this function converts the offset into
141 * an address.
142 */
143static __inline__ unsigned long isa_port2addr(unsigned long offset)
144{
145 return __isa_port2addr(offset);
146}
147
148/*
149 * This function provides a method for the generic case where a board-specific
150 * isa_port2addr simply needs to return the port + some arbitrary port base.
151 *
152 * We use this at board setup time to implicitly set the port base, and
153 * as a result, we can use the generic isa_port2addr.
154 */
155static inline void __set_io_port_base(unsigned long pbase)
156{
157 extern unsigned long generic_io_base;
158
159 generic_io_base = pbase;
160}
161
162#define isa_readb(a) readb(isa_port2addr(a))
163#define isa_readw(a) readw(isa_port2addr(a))
164#define isa_readl(a) readl(isa_port2addr(a))
165#define isa_writeb(b,a) writeb(b,isa_port2addr(a))
166#define isa_writew(w,a) writew(w,isa_port2addr(a))
167#define isa_writel(l,a) writel(l,isa_port2addr(a))
168#define isa_memset_io(a,b,c) \
169 memset((void *)(isa_port2addr((unsigned long)a)),(b),(c))
170#define isa_memcpy_fromio(a,b,c) \
171 memcpy((a),(void *)(isa_port2addr((unsigned long)(b))),(c))
172#define isa_memcpy_toio(a,b,c) \
173 memcpy((void *)(isa_port2addr((unsigned long)(a))),(b),(c))
174
175/* We really want to try and get these to memcpy etc */
176extern void memcpy_fromio(void *, unsigned long, unsigned long);
177extern void memcpy_toio(unsigned long, const void *, unsigned long);
178extern void memset_io(unsigned long, int, unsigned long);
179
180/* SuperH on-chip I/O functions */
181static __inline__ unsigned char ctrl_inb(unsigned long addr)
182{
183 return *(volatile unsigned char*)addr;
184}
185
186static __inline__ unsigned short ctrl_inw(unsigned long addr)
187{
188 return *(volatile unsigned short*)addr;
189}
190
191static __inline__ unsigned int ctrl_inl(unsigned long addr)
192{
193 return *(volatile unsigned long*)addr;
194}
195
196static __inline__ void ctrl_outb(unsigned char b, unsigned long addr)
197{
198 *(volatile unsigned char*)addr = b;
199}
200
201static __inline__ void ctrl_outw(unsigned short b, unsigned long addr)
202{
203 *(volatile unsigned short*)addr = b;
204}
205
206static __inline__ void ctrl_outl(unsigned int b, unsigned long addr)
207{
208 *(volatile unsigned long*)addr = b;
209}
210
211#define IO_SPACE_LIMIT 0xffffffff
212
213/*
214 * Change virtual addresses to physical addresses and vv.
215 * These are trivial on the 1:1 Linux/SuperH mapping
216 */
217static __inline__ unsigned long virt_to_phys(volatile void * address)
218{
219 return PHYSADDR(address);
220}
221
222static __inline__ void * phys_to_virt(unsigned long address)
223{
224 return (void *)P1SEGADDR(address);
225}
226
227#define virt_to_bus virt_to_phys
228#define bus_to_virt phys_to_virt
229#define page_to_bus page_to_phys
230
231/*
232 * readX/writeX() are used to access memory mapped devices. On some
233 * architectures the memory mapped IO stuff needs to be accessed
234 * differently. On the x86 architecture, we just read/write the
235 * memory location directly.
236 *
237 * On SH, we have the whole physical address space mapped at all times
238 * (as MIPS does), so "ioremap()" and "iounmap()" do not need to do
239 * anything. (This isn't true for all machines but we still handle
240 * these cases with wired TLB entries anyway ...)
241 *
242 * We cheat a bit and always return uncachable areas until we've fixed
243 * the drivers to handle caching properly.
244 */
245static __inline__ void * ioremap(unsigned long offset, unsigned long size)
246{
247 return __ioremap(offset, size);
248}
249
250static __inline__ void iounmap(void *addr)
251{
252 return __iounmap(addr);
253}
254
255#define ioremap_nocache(off,size) ioremap(off,size)
256
257static __inline__ int check_signature(unsigned long io_addr,
258 const unsigned char *signature, int length)
259{
260 int retval = 0;
261 do {
262 if (readb(io_addr) != *signature)
263 goto out;
264 io_addr++;
265 signature++;
266 length--;
267 } while (length);
268 retval = 1;
269out:
270 return retval;
271}
272
273/*
274 * The caches on some architectures aren't dma-coherent and have need to
275 * handle this in software. There are three types of operations that
276 * can be applied to dma buffers.
277 *
278 * - dma_cache_wback_inv(start, size) makes caches and RAM coherent by
279 * writing the content of the caches back to memory, if necessary.
280 * The function also invalidates the affected part of the caches as
281 * necessary before DMA transfers from outside to memory.
282 * - dma_cache_inv(start, size) invalidates the affected parts of the
283 * caches. Dirty lines of the caches may be written back or simply
284 * be discarded. This operation is necessary before dma operations
285 * to the memory.
286 * - dma_cache_wback(start, size) writes back any dirty lines but does
287 * not invalidate the cache. This can be used before DMA reads from
288 * memory,
289 */
290
291#define dma_cache_wback_inv(_start,_size) \
292 __flush_purge_region(_start,_size)
293#define dma_cache_inv(_start,_size) \
294 __flush_invalidate_region(_start,_size)
295#define dma_cache_wback(_start,_size) \
296 __flush_wback_region(_start,_size)
297
298/*
299 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
300 * access
301 */
302#define xlate_dev_mem_ptr(p) __va(p)
303
304/*
305 * Convert a virtual cached pointer to an uncached pointer
306 */
307#define xlate_dev_kmem_ptr(p) p
308
309#endif /* __KERNEL__ */
310
311#endif /* __ASM_SH_IO_H */
diff --git a/include/asm-sh/io_generic.h b/include/asm-sh/io_generic.h
new file mode 100644
index 000000000000..be14587342f7
--- /dev/null
+++ b/include/asm-sh/io_generic.h
@@ -0,0 +1,51 @@
1/*
2 * include/asm-sh/io_generic.h
3 *
4 * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * Generic IO functions
10 */
11
12#ifndef _ASM_SH_IO_GENERIC_H
13#define _ASM_SH_IO_GENERIC_H
14
15extern unsigned long generic_io_base;
16
17extern unsigned char generic_inb(unsigned long port);
18extern unsigned short generic_inw(unsigned long port);
19extern unsigned int generic_inl(unsigned long port);
20
21extern void generic_outb(unsigned char value, unsigned long port);
22extern void generic_outw(unsigned short value, unsigned long port);
23extern void generic_outl(unsigned int value, unsigned long port);
24
25extern unsigned char generic_inb_p(unsigned long port);
26extern unsigned short generic_inw_p(unsigned long port);
27extern unsigned int generic_inl_p(unsigned long port);
28extern void generic_outb_p(unsigned char value, unsigned long port);
29extern void generic_outw_p(unsigned short value, unsigned long port);
30extern void generic_outl_p(unsigned int value, unsigned long port);
31
32extern void generic_insb(unsigned long port, void *addr, unsigned long count);
33extern void generic_insw(unsigned long port, void *addr, unsigned long count);
34extern void generic_insl(unsigned long port, void *addr, unsigned long count);
35extern void generic_outsb(unsigned long port, const void *addr, unsigned long count);
36extern void generic_outsw(unsigned long port, const void *addr, unsigned long count);
37extern void generic_outsl(unsigned long port, const void *addr, unsigned long count);
38
39extern unsigned char generic_readb(unsigned long addr);
40extern unsigned short generic_readw(unsigned long addr);
41extern unsigned int generic_readl(unsigned long addr);
42extern void generic_writeb(unsigned char b, unsigned long addr);
43extern void generic_writew(unsigned short b, unsigned long addr);
44extern void generic_writel(unsigned int b, unsigned long addr);
45
46extern void *generic_ioremap(unsigned long offset, unsigned long size);
47extern void generic_iounmap(void *addr);
48
49extern unsigned long generic_isa_port2addr(unsigned long offset);
50
51#endif /* _ASM_SH_IO_GENERIC_H */
diff --git a/include/asm-sh/ioctl.h b/include/asm-sh/ioctl.h
new file mode 100644
index 000000000000..524700e84acd
--- /dev/null
+++ b/include/asm-sh/ioctl.h
@@ -0,0 +1,75 @@
1/* $Id: ioctl.h,v 1.1.1.1 2001/10/15 20:45:09 mrbrown Exp $
2 *
3 * linux/ioctl.h for Linux by H.H. Bergman.
4 */
5
6#ifndef __ASM_SH_IOCTL_H
7#define __ASM_SH_IOCTL_H
8
9/* ioctl command encoding: 32 bits total, command in lower 16 bits,
10 * size of the parameter structure in the lower 14 bits of the
11 * upper 16 bits.
12 * Encoding the size of the parameter structure in the ioctl request
13 * is useful for catching programs compiled with old versions
14 * and to avoid overwriting user space outside the user buffer area.
15 * The highest 2 bits are reserved for indicating the ``access mode''.
16 * NOTE: This limits the max parameter size to 16kB -1 !
17 */
18
19/*
20 * The following is for compatibility across the various Linux
21 * platforms. The i386 ioctl numbering scheme doesn't really enforce
22 * a type field. De facto, however, the top 8 bits of the lower 16
23 * bits are indeed used as a type field, so we might just as well make
24 * this explicit here. Please be sure to use the decoding macros
25 * below from now on.
26 */
27#define _IOC_NRBITS 8
28#define _IOC_TYPEBITS 8
29#define _IOC_SIZEBITS 14
30#define _IOC_DIRBITS 2
31
32#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
33#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)
34#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)
35#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)
36
37#define _IOC_NRSHIFT 0
38#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS)
39#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS)
40#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS)
41
42/*
43 * Direction bits.
44 */
45#define _IOC_NONE 0U
46#define _IOC_WRITE 1U
47#define _IOC_READ 2U
48
49#define _IOC(dir,type,nr,size) \
50 (((dir) << _IOC_DIRSHIFT) | \
51 ((type) << _IOC_TYPESHIFT) | \
52 ((nr) << _IOC_NRSHIFT) | \
53 ((size) << _IOC_SIZESHIFT))
54
55/* used to create numbers */
56#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0)
57#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size))
58#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
59#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
60
61/* used to decode ioctl numbers.. */
62#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
63#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
64#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
65#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
66
67/* ...and for the drivers/sound files... */
68
69#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
70#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
71#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
72#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT)
73#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
74
75#endif /* __ASM_SH_IOCTL_H */
diff --git a/include/asm-sh/ioctls.h b/include/asm-sh/ioctls.h
new file mode 100644
index 000000000000..1866f3f90028
--- /dev/null
+++ b/include/asm-sh/ioctls.h
@@ -0,0 +1,99 @@
1#ifndef __ASM_SH_IOCTLS_H
2#define __ASM_SH_IOCTLS_H
3
4#include <asm/ioctl.h>
5
6#define FIOCLEX _IO('f', 1)
7#define FIONCLEX _IO('f', 2)
8#define FIOASYNC _IOW('f', 125, int)
9#define FIONBIO _IOW('f', 126, int)
10#define FIONREAD _IOR('f', 127, int)
11#define TIOCINQ FIONREAD
12#define FIOQSIZE _IOR('f', 128, loff_t)
13
14#define TCGETS 0x5401
15#define TCSETS 0x5402
16#define TCSETSW 0x5403
17#define TCSETSF 0x5404
18
19#define TCGETA _IOR('t', 23, struct termio)
20#define TCSETA _IOW('t', 24, struct termio)
21#define TCSETAW _IOW('t', 25, struct termio)
22#define TCSETAF _IOW('t', 28, struct termio)
23
24#define TCSBRK _IO('t', 29)
25#define TCXONC _IO('t', 30)
26#define TCFLSH _IO('t', 31)
27
28#define TIOCSWINSZ _IOW('t', 103, struct winsize)
29#define TIOCGWINSZ _IOR('t', 104, struct winsize)
30#define TIOCSTART _IO('t', 110) /* start output, like ^Q */
31#define TIOCSTOP _IO('t', 111) /* stop output, like ^S */
32#define TIOCOUTQ _IOR('t', 115, int) /* output queue size */
33
34#define TIOCSPGRP _IOW('t', 118, int)
35#define TIOCGPGRP _IOR('t', 119, int)
36
37#define TIOCEXCL _IO('T', 12) /* 0x540C */
38#define TIOCNXCL _IO('T', 13) /* 0x540D */
39#define TIOCSCTTY _IO('T', 14) /* 0x540E */
40
41#define TIOCSTI _IOW('T', 18, char) /* 0x5412 */
42#define TIOCMGET _IOR('T', 21, unsigned int) /* 0x5415 */
43#define TIOCMBIS _IOW('T', 22, unsigned int) /* 0x5416 */
44#define TIOCMBIC _IOW('T', 23, unsigned int) /* 0x5417 */
45#define TIOCMSET _IOW('T', 24, unsigned int) /* 0x5418 */
46# define TIOCM_LE 0x001
47# define TIOCM_DTR 0x002
48# define TIOCM_RTS 0x004
49# define TIOCM_ST 0x008
50# define TIOCM_SR 0x010
51# define TIOCM_CTS 0x020
52# define TIOCM_CAR 0x040
53# define TIOCM_RNG 0x080
54# define TIOCM_DSR 0x100
55# define TIOCM_CD TIOCM_CAR
56# define TIOCM_RI TIOCM_RNG
57
58#define TIOCGSOFTCAR _IOR('T', 25, unsigned int) /* 0x5419 */
59#define TIOCSSOFTCAR _IOW('T', 26, unsigned int) /* 0x541A */
60#define TIOCLINUX _IOW('T', 28, char) /* 0x541C */
61#define TIOCCONS _IO('T', 29) /* 0x541D */
62#define TIOCGSERIAL _IOR('T', 30, struct serial_struct) /* 0x541E */
63#define TIOCSSERIAL _IOW('T', 31, struct serial_struct) /* 0x541F */
64#define TIOCPKT _IOW('T', 32, int) /* 0x5420 */
65# define TIOCPKT_DATA 0
66# define TIOCPKT_FLUSHREAD 1
67# define TIOCPKT_FLUSHWRITE 2
68# define TIOCPKT_STOP 4
69# define TIOCPKT_START 8
70# define TIOCPKT_NOSTOP 16
71# define TIOCPKT_DOSTOP 32
72
73
74#define TIOCNOTTY _IO('T', 34) /* 0x5422 */
75#define TIOCSETD _IOW('T', 35, int) /* 0x5423 */
76#define TIOCGETD _IOR('T', 36, int) /* 0x5424 */
77#define TCSBRKP _IOW('T', 37, int) /* 0x5425 */ /* Needed for POSIX tcsendbreak() */
78#define TIOCSBRK _IO('T', 39) /* 0x5427 */ /* BSD compatibility */
79#define TIOCCBRK _IO('T', 40) /* 0x5428 */ /* BSD compatibility */
80#define TIOCGSID _IOR('T', 41, pid_t) /* 0x5429 */ /* Return the session ID of FD */
81#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
82#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
83
84#define TIOCSERCONFIG _IO('T', 83) /* 0x5453 */
85#define TIOCSERGWILD _IOR('T', 84, int) /* 0x5454 */
86#define TIOCSERSWILD _IOW('T', 85, int) /* 0x5455 */
87#define TIOCGLCKTRMIOS 0x5456
88#define TIOCSLCKTRMIOS 0x5457
89#define TIOCSERGSTRUCT _IOR('T', 88, struct async_struct) /* 0x5458 */ /* For debugging only */
90#define TIOCSERGETLSR _IOR('T', 89, unsigned int) /* 0x5459 */ /* Get line status register */
91 /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
92# define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
93#define TIOCSERGETMULTI _IOR('T', 90, struct serial_multiport_struct) /* 0x545A */ /* Get multiport config */
94#define TIOCSERSETMULTI _IOW('T', 91, struct serial_multiport_struct) /* 0x545B */ /* Set multiport config */
95
96#define TIOCMIWAIT _IO('T', 92) /* 0x545C */ /* wait for a change on serial input line(s) */
97#define TIOCGICOUNT _IOR('T', 93, struct async_icount) /* 0x545D */ /* read serial port inline interrupt counts */
98
99#endif /* __ASM_SH_IOCTLS_H */
diff --git a/include/asm-sh/ipc.h b/include/asm-sh/ipc.h
new file mode 100644
index 000000000000..a46e3d9c2a3f
--- /dev/null
+++ b/include/asm-sh/ipc.h
@@ -0,0 +1 @@
#include <asm-generic/ipc.h>
diff --git a/include/asm-sh/ipcbuf.h b/include/asm-sh/ipcbuf.h
new file mode 100644
index 000000000000..5ffc9972a7ea
--- /dev/null
+++ b/include/asm-sh/ipcbuf.h
@@ -0,0 +1,29 @@
1#ifndef __ASM_SH_IPCBUF_H__
2#define __ASM_SH_IPCBUF_H__
3
4/*
5 * The ipc64_perm structure for i386 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 32-bit mode_t and seq
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct ipc64_perm
15{
16 __kernel_key_t key;
17 __kernel_uid32_t uid;
18 __kernel_gid32_t gid;
19 __kernel_uid32_t cuid;
20 __kernel_gid32_t cgid;
21 __kernel_mode_t mode;
22 unsigned short __pad1;
23 unsigned short seq;
24 unsigned short __pad2;
25 unsigned long __unused1;
26 unsigned long __unused2;
27};
28
29#endif /* __ASM_SH_IPCBUF_H__ */
diff --git a/include/asm-sh/irq-sh73180.h b/include/asm-sh/irq-sh73180.h
new file mode 100644
index 000000000000..bf2e4310ffac
--- /dev/null
+++ b/include/asm-sh/irq-sh73180.h
@@ -0,0 +1,350 @@
1#ifndef __ASM_SH_IRQ_SH73180_H
2#define __ASM_SH_IRQ_SH73180_H
3
4/*
5 * linux/include/asm-sh/irq-sh73180.h
6 *
7 * Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp>
8 */
9
10#undef INTC_IPRA
11#undef INTC_IPRB
12#undef INTC_IPRC
13#undef INTC_IPRD
14
15#undef DMTE0_IRQ
16#undef DMTE1_IRQ
17#undef DMTE2_IRQ
18#undef DMTE3_IRQ
19#undef DMTE4_IRQ
20#undef DMTE5_IRQ
21#undef DMTE6_IRQ
22#undef DMTE7_IRQ
23#undef DMAE_IRQ
24#undef DMA_IPR_ADDR
25#undef DMA_IPR_POS
26#undef DMA_PRIORITY
27
28#undef NR_IRQS
29
30#undef __irq_demux
31#undef irq_demux
32
33#undef INTC_IMCR0
34#undef INTC_IMCR1
35#undef INTC_IMCR2
36#undef INTC_IMCR3
37#undef INTC_IMCR4
38#undef INTC_IMCR5
39#undef INTC_IMCR6
40#undef INTC_IMCR7
41#undef INTC_IMCR8
42#undef INTC_IMCR9
43#undef INTC_IMCR10
44
45
46#define INTC_IPRA 0xA4080000UL
47#define INTC_IPRB 0xA4080004UL
48#define INTC_IPRC 0xA4080008UL
49#define INTC_IPRD 0xA408000CUL
50#define INTC_IPRE 0xA4080010UL
51#define INTC_IPRF 0xA4080014UL
52#define INTC_IPRG 0xA4080018UL
53#define INTC_IPRH 0xA408001CUL
54#define INTC_IPRI 0xA4080020UL
55#define INTC_IPRJ 0xA4080024UL
56#define INTC_IPRK 0xA4080028UL
57
58#define INTC_IMR0 0xA4080080UL
59#define INTC_IMR1 0xA4080084UL
60#define INTC_IMR2 0xA4080088UL
61#define INTC_IMR3 0xA408008CUL
62#define INTC_IMR4 0xA4080090UL
63#define INTC_IMR5 0xA4080094UL
64#define INTC_IMR6 0xA4080098UL
65#define INTC_IMR7 0xA408009CUL
66#define INTC_IMR8 0xA40800A0UL
67#define INTC_IMR9 0xA40800A4UL
68#define INTC_IMR10 0xA40800A8UL
69#define INTC_IMR11 0xA40800ACUL
70
71#define INTC_IMCR0 0xA40800C0UL
72#define INTC_IMCR1 0xA40800C4UL
73#define INTC_IMCR2 0xA40800C8UL
74#define INTC_IMCR3 0xA40800CCUL
75#define INTC_IMCR4 0xA40800D0UL
76#define INTC_IMCR5 0xA40800D4UL
77#define INTC_IMCR6 0xA40800D8UL
78#define INTC_IMCR7 0xA40800DCUL
79#define INTC_IMCR8 0xA40800E0UL
80#define INTC_IMCR9 0xA40800E4UL
81#define INTC_IMCR10 0xA40800E8UL
82#define INTC_IMCR11 0xA40800ECUL
83
84#define INTC_ICR0 0xA4140000UL
85#define INTC_ICR1 0xA414001CUL
86
87#define INTMSK0 0xa4140044
88#define INTMSKCLR0 0xa4140064
89#define INTC_INTPRI0 0xa4140010
90
91/*
92 NOTE:
93
94 *_IRQ = (INTEVT2 - 0x200)/0x20
95*/
96
97/* TMU0 */
98#define TMU0_IRQ 16
99#define TMU0_IPR_ADDR INTC_IPRA
100#define TMU0_IPR_POS 3
101#define TMU0_PRIORITY 2
102
103#define TIMER_IRQ 16
104#define TIMER_IPR_ADDR INTC_IPRA
105#define TIMER_IPR_POS 3
106#define TIMER_PRIORITY 2
107
108/* TMU1 */
109#define TMU1_IRQ 17
110#define TMU1_IPR_ADDR INTC_IPRA
111#define TMU1_IPR_POS 2
112#define TMU1_PRIORITY 2
113
114/* TMU2 */
115#define TMU2_IRQ 18
116#define TMU2_IPR_ADDR INTC_IPRA
117#define TMU2_IPR_POS 1
118#define TMU2_PRIORITY 2
119
120/* LCDC */
121#define LCDC_IRQ 28
122#define LCDC_IPR_ADDR INTC_IPRB
123#define LCDC_IPR_POS 2
124#define LCDC_PRIORITY 2
125
126/* VIO (Video I/O) */
127#define CEU_IRQ 52
128#define BEU_IRQ 53
129#define VEU_IRQ 54
130#define VOU_IRQ 55
131#define VIO_IPR_ADDR INTC_IPRE
132#define VIO_IPR_POS 2
133#define VIO_PRIORITY 2
134
135/* MFI (Multi Functional Interface) */
136#define MFI_IRQ 56
137#define MFI_IPR_ADDR INTC_IPRE
138#define MFI_IPR_POS 1
139#define MFI_PRIORITY 2
140
141/* VPU (Video Processing Unit) */
142#define VPU_IRQ 60
143#define VPU_IPR_ADDR INTC_IPRE
144#define VPU_IPR_POS 0
145#define VPU_PRIORITY 2
146
147/* 3DG */
148#define TDG_IRQ 63
149#define TDG_IPR_ADDR INTC_IPRJ
150#define TDG_IPR_POS 2
151#define TDG_PRIORITY 2
152
153/* DMAC(1) */
154#define DMTE0_IRQ 48
155#define DMTE1_IRQ 49
156#define DMTE2_IRQ 50
157#define DMTE3_IRQ 51
158#define DMA1_IPR_ADDR INTC_IPRE
159#define DMA1_IPR_POS 3
160#define DMA1_PRIORITY 7
161
162/* DMAC(2) */
163#define DMTE4_IRQ 76
164#define DMTE5_IRQ 77
165#define DMA2_IPR_ADDR INTC_IPRF
166#define DMA2_IPR_POS 2
167#define DMA2_PRIORITY 7
168
169/* SCIF0 */
170#define SCIF_ERI_IRQ 80
171#define SCIF_RXI_IRQ 81
172#define SCIF_BRI_IRQ 82
173#define SCIF_TXI_IRQ 83
174#define SCIF_IPR_ADDR INTC_IPRG
175#define SCIF_IPR_POS 3
176#define SCIF_PRIORITY 3
177
178/* SIOF0 */
179#define SIOF0_IRQ 84
180#define SIOF0_IPR_ADDR INTC_IPRH
181#define SIOF0_IPR_POS 3
182#define SIOF0_PRIORITY 3
183
184/* FLCTL (Flash Memory Controller) */
185#define FLSTE_IRQ 92
186#define FLTEND_IRQ 93
187#define FLTRQ0_IRQ 94
188#define FLTRQ1_IRQ 95
189#define FLCTL_IPR_ADDR INTC_IPRH
190#define FLCTL_IPR_POS 1
191#define FLCTL_PRIORITY 3
192
193/* IIC(0) (IIC Bus Interface) */
194#define IIC0_ALI_IRQ 96
195#define IIC0_TACKI_IRQ 97
196#define IIC0_WAITI_IRQ 98
197#define IIC0_DTEI_IRQ 99
198#define IIC0_IPR_ADDR INTC_IPRH
199#define IIC0_IPR_POS 0
200#define IIC0_PRIORITY 3
201
202/* IIC(1) (IIC Bus Interface) */
203#define IIC1_ALI_IRQ 44
204#define IIC1_TACKI_IRQ 45
205#define IIC1_WAITI_IRQ 46
206#define IIC1_DTEI_IRQ 47
207#define IIC1_IPR_ADDR INTC_IPRG
208#define IIC1_IPR_POS 0
209#define IIC1_PRIORITY 3
210
211/* SIO0 */
212#define SIO0_IRQ 88
213#define SIO0_IPR_ADDR INTC_IPRI
214#define SIO0_IPR_POS 3
215#define SIO0_PRIORITY 3
216
217/* SDHI */
218#define SDHI_SDHII0_IRQ 100
219#define SDHI_SDHII1_IRQ 101
220#define SDHI_SDHII2_IRQ 102
221#define SDHI_SDHII3_IRQ 103
222#define SDHI_IPR_ADDR INTC_IPRK
223#define SDHI_IPR_POS 0
224#define SDHI_PRIORITY 3
225
226/* SIU (Sound Interface Unit) */
227#define SIU_IRQ 108
228#define SIU_IPR_ADDR INTC_IPRJ
229#define SIU_IPR_POS 1
230#define SIU_PRIORITY 3
231
232
233/* ONCHIP_NR_IRQS */
234#define NR_IRQS 109
235
236/* In a generic kernel, NR_IRQS is an upper bound, and we should use
237 * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
238 */
239#define ACTUAL_NR_IRQS NR_IRQS
240
241
242extern void disable_irq(unsigned int);
243extern void disable_irq_nosync(unsigned int);
244extern void enable_irq(unsigned int);
245
246/*
247 * Simple Mask Register Support
248 */
249extern void make_maskreg_irq(unsigned int irq);
250extern unsigned short *irq_mask_register;
251
252/*
253 * Function for "on chip support modules".
254 */
255extern void make_ipr_irq(unsigned int irq, unsigned int addr,
256 int pos, int priority);
257extern void make_imask_irq(unsigned int irq);
258
259#define PORT_PACR 0xA4050100UL
260#define PORT_PBCR 0xA4050102UL
261#define PORT_PCCR 0xA4050104UL
262#define PORT_PDCR 0xA4050106UL
263#define PORT_PECR 0xA4050108UL
264#define PORT_PFCR 0xA405010AUL
265#define PORT_PGCR 0xA405010CUL
266#define PORT_PHCR 0xA405010EUL
267#define PORT_PJCR 0xA4050110UL
268#define PORT_PKCR 0xA4050112UL
269#define PORT_PLCR 0xA4050114UL
270#define PORT_SCPCR 0xA4050116UL
271#define PORT_PMCR 0xA4050118UL
272#define PORT_PNCR 0xA405011AUL
273#define PORT_PQCR 0xA405011CUL
274#define PORT_PRCR 0xA405011EUL
275#define PORT_PTCR 0xA405014CUL
276#define PORT_PUCR 0xA405014EUL
277#define PORT_PVCR 0xA4050150UL
278
279#define PORT_PSELA 0xA4050140UL
280#define PORT_PSELB 0xA4050142UL
281#define PORT_PSELC 0xA4050144UL
282#define PORT_PSELE 0xA4050158UL
283
284#define PORT_HIZCRA 0xA4050146UL
285#define PORT_HIZCRB 0xA4050148UL
286#define PORT_DRVCR 0xA405014AUL
287
288#define PORT_PADR 0xA4050120UL
289#define PORT_PBDR 0xA4050122UL
290#define PORT_PCDR 0xA4050124UL
291#define PORT_PDDR 0xA4050126UL
292#define PORT_PEDR 0xA4050128UL
293#define PORT_PFDR 0xA405012AUL
294#define PORT_PGDR 0xA405012CUL
295#define PORT_PHDR 0xA405012EUL
296#define PORT_PJDR 0xA4050130UL
297#define PORT_PKDR 0xA4050132UL
298#define PORT_PLDR 0xA4050134UL
299#define PORT_SCPDR 0xA4050136UL
300#define PORT_PMDR 0xA4050138UL
301#define PORT_PNDR 0xA405013AUL
302#define PORT_PQDR 0xA405013CUL
303#define PORT_PRDR 0xA405013EUL
304#define PORT_PTDR 0xA405016CUL
305#define PORT_PUDR 0xA405016EUL
306#define PORT_PVDR 0xA4050170UL
307
308#define IRQ0_IRQ 32
309#define IRQ1_IRQ 33
310#define IRQ2_IRQ 34
311#define IRQ3_IRQ 35
312#define IRQ4_IRQ 36
313#define IRQ5_IRQ 37
314#define IRQ6_IRQ 38
315#define IRQ7_IRQ 39
316
317#define INTPRI00 0xA4140010UL
318
319#define IRQ0_IPR_ADDR INTPRI00
320#define IRQ1_IPR_ADDR INTPRI00
321#define IRQ2_IPR_ADDR INTPRI00
322#define IRQ3_IPR_ADDR INTPRI00
323#define IRQ4_IPR_ADDR INTPRI00
324#define IRQ5_IPR_ADDR INTPRI00
325#define IRQ6_IPR_ADDR INTPRI00
326#define IRQ7_IPR_ADDR INTPRI00
327
328#define IRQ0_IPR_POS 7
329#define IRQ1_IPR_POS 6
330#define IRQ2_IPR_POS 5
331#define IRQ3_IPR_POS 4
332#define IRQ4_IPR_POS 3
333#define IRQ5_IPR_POS 2
334#define IRQ6_IPR_POS 1
335#define IRQ7_IPR_POS 0
336
337#define IRQ0_PRIORITY 1
338#define IRQ1_PRIORITY 1
339#define IRQ2_PRIORITY 1
340#define IRQ3_PRIORITY 1
341#define IRQ4_PRIORITY 1
342#define IRQ5_PRIORITY 1
343#define IRQ6_PRIORITY 1
344#define IRQ7_PRIORITY 1
345
346extern int shmse_irq_demux(int irq);
347#define __irq_demux(irq) shmse_irq_demux(irq)
348#define irq_demux(irq) __irq_demux(irq)
349
350#endif /* __ASM_SH_IRQ_SH73180_H */
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
new file mode 100644
index 000000000000..831e52ee45b5
--- /dev/null
+++ b/include/asm-sh/irq.h
@@ -0,0 +1,598 @@
1#ifndef __ASM_SH_IRQ_H
2#define __ASM_SH_IRQ_H
3
4/*
5 *
6 * linux/include/asm-sh/irq.h
7 *
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2003 Paul Mundt
11 *
12 */
13
14#include <linux/config.h>
15#include <asm/machvec.h>
16#include <asm/ptrace.h> /* for pt_regs */
17
18#if defined(CONFIG_SH_HP600) || \
19 defined(CONFIG_SH_RTS7751R2D) || \
20 defined(CONFIG_SH_HS7751RVOIP) || \
21 defined(CONFIG_SH_SH03)
22#include <asm/mach/ide.h>
23#endif
24
25#if defined(CONFIG_CPU_SH3)
26#define INTC_IPRA 0xfffffee2UL
27#define INTC_IPRB 0xfffffee4UL
28#elif defined(CONFIG_CPU_SH4)
29#define INTC_IPRA 0xffd00004UL
30#define INTC_IPRB 0xffd00008UL
31#define INTC_IPRC 0xffd0000cUL
32#define INTC_IPRD 0xffd00010UL
33#endif
34
35#ifdef CONFIG_IDE
36# ifndef IRQ_CFCARD
37# define IRQ_CFCARD 14
38# endif
39# ifndef IRQ_PCMCIA
40# define IRQ_PCMCIA 15
41# endif
42#endif
43
44#define TIMER_IRQ 16
45#define TIMER_IPR_ADDR INTC_IPRA
46#define TIMER_IPR_POS 3
47#define TIMER_PRIORITY 2
48
49#define TIMER1_IRQ 17
50#define TIMER1_IPR_ADDR INTC_IPRA
51#define TIMER1_IPR_POS 2
52#define TIMER1_PRIORITY 4
53
54#define RTC_IRQ 22
55#define RTC_IPR_ADDR INTC_IPRA
56#define RTC_IPR_POS 0
57#define RTC_PRIORITY TIMER_PRIORITY
58
59#if defined(CONFIG_CPU_SH3)
60#define DMTE0_IRQ 48
61#define DMTE1_IRQ 49
62#define DMTE2_IRQ 50
63#define DMTE3_IRQ 51
64#define DMA_IPR_ADDR INTC_IPRE
65#define DMA_IPR_POS 3
66#define DMA_PRIORITY 7
67#if defined(CONFIG_CPU_SUBTYPE_SH7300)
68/* TMU2 */
69#define TIMER2_IRQ 18
70#define TIMER2_IPR_ADDR INTC_IPRA
71#define TIMER2_IPR_POS 1
72#define TIMER2_PRIORITY 2
73
74/* WDT */
75#define WDT_IRQ 27
76#define WDT_IPR_ADDR INTC_IPRB
77#define WDT_IPR_POS 3
78#define WDT_PRIORITY 2
79
80/* SIM (SIM Card Module) */
81#define SIM_ERI_IRQ 23
82#define SIM_RXI_IRQ 24
83#define SIM_TXI_IRQ 25
84#define SIM_TEND_IRQ 26
85#define SIM_IPR_ADDR INTC_IPRB
86#define SIM_IPR_POS 1
87#define SIM_PRIORITY 2
88
89/* VIO (Video I/O) */
90#define VIO_IRQ 52
91#define VIO_IPR_ADDR INTC_IPRE
92#define VIO_IPR_POS 2
93#define VIO_PRIORITY 2
94
95/* MFI (Multi Functional Interface) */
96#define MFI_IRQ 56
97#define MFI_IPR_ADDR INTC_IPRE
98#define MFI_IPR_POS 1
99#define MFI_PRIORITY 2
100
101/* VPU (Video Processing Unit) */
102#define VPU_IRQ 60
103#define VPU_IPR_ADDR INTC_IPRE
104#define VPU_IPR_POS 0
105#define VPU_PRIORITY 2
106
107/* KEY (Key Scan Interface) */
108#define KEY_IRQ 79
109#define KEY_IPR_ADDR INTC_IPRF
110#define KEY_IPR_POS 3
111#define KEY_PRIORITY 2
112
113/* CMT (Compare Match Timer) */
114#define CMT_IRQ 104
115#define CMT_IPR_ADDR INTC_IPRF
116#define CMT_IPR_POS 0
117#define CMT_PRIORITY 2
118
119/* DMAC(1) */
120#define DMTE0_IRQ 48
121#define DMTE1_IRQ 49
122#define DMTE2_IRQ 50
123#define DMTE3_IRQ 51
124#define DMA1_IPR_ADDR INTC_IPRE
125#define DMA1_IPR_POS 3
126#define DMA1_PRIORITY 7
127
128/* DMAC(2) */
129#define DMTE4_IRQ 76
130#define DMTE5_IRQ 77
131#define DMA2_IPR_ADDR INTC_IPRF
132#define DMA2_IPR_POS 2
133#define DMA2_PRIORITY 7
134
135/* SIOF0 */
136#define SIOF0_IRQ 84
137#define SIOF0_IPR_ADDR INTC_IPRH
138#define SIOF0_IPR_POS 3
139#define SIOF0_PRIORITY 3
140
141/* FLCTL (Flash Memory Controller) */
142#define FLSTE_IRQ 92
143#define FLTEND_IRQ 93
144#define FLTRQ0_IRQ 94
145#define FLTRQ1_IRQ 95
146#define FLCTL_IPR_ADDR INTC_IPRH
147#define FLCTL_IPR_POS 1
148#define FLCTL_PRIORITY 3
149
150/* IIC (IIC Bus Interface) */
151#define IIC_ALI_IRQ 96
152#define IIC_TACKI_IRQ 97
153#define IIC_WAITI_IRQ 98
154#define IIC_DTEI_IRQ 99
155#define IIC_IPR_ADDR INTC_IPRH
156#define IIC_IPR_POS 0
157#define IIC_PRIORITY 3
158
159/* SIO0 */
160#define SIO0_IRQ 88
161#define SIO0_IPR_ADDR INTC_IPRI
162#define SIO0_IPR_POS 3
163#define SIO0_PRIORITY 3
164
165/* SIU (Sound Interface Unit) */
166#define SIU_IRQ 108
167#define SIU_IPR_ADDR INTC_IPRJ
168#define SIU_IPR_POS 1
169#define SIU_PRIORITY 3
170
171#endif
172#elif defined(CONFIG_CPU_SH4)
173#define DMTE0_IRQ 34
174#define DMTE1_IRQ 35
175#define DMTE2_IRQ 36
176#define DMTE3_IRQ 37
177#define DMTE4_IRQ 44 /* 7751R only */
178#define DMTE5_IRQ 45 /* 7751R only */
179#define DMTE6_IRQ 46 /* 7751R only */
180#define DMTE7_IRQ 47 /* 7751R only */
181#define DMAE_IRQ 38
182#define DMA_IPR_ADDR INTC_IPRC
183#define DMA_IPR_POS 2
184#define DMA_PRIORITY 7
185#endif
186
187#if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
188 defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
189 defined (CONFIG_CPU_SUBTYPE_SH7751)
190#define SCI_ERI_IRQ 23
191#define SCI_RXI_IRQ 24
192#define SCI_TXI_IRQ 25
193#define SCI_IPR_ADDR INTC_IPRB
194#define SCI_IPR_POS 1
195#define SCI_PRIORITY 3
196#endif
197
198#if defined(CONFIG_CPU_SUBTYPE_SH7300)
199#define SCIF0_IRQ 80
200#define SCIF0_IPR_ADDR INTC_IPRG
201#define SCIF0_IPR_POS 3
202#define SCIF0_PRIORITY 3
203#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
204 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
205 defined(CONFIG_CPU_SUBTYPE_SH7709)
206#define SCIF_ERI_IRQ 56
207#define SCIF_RXI_IRQ 57
208#define SCIF_BRI_IRQ 58
209#define SCIF_TXI_IRQ 59
210#define SCIF_IPR_ADDR INTC_IPRE
211#define SCIF_IPR_POS 1
212#define SCIF_PRIORITY 3
213
214#define IRDA_ERI_IRQ 52
215#define IRDA_RXI_IRQ 53
216#define IRDA_BRI_IRQ 54
217#define IRDA_TXI_IRQ 55
218#define IRDA_IPR_ADDR INTC_IPRE
219#define IRDA_IPR_POS 2
220#define IRDA_PRIORITY 3
221#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
222 defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
223#define SCIF_ERI_IRQ 40
224#define SCIF_RXI_IRQ 41
225#define SCIF_BRI_IRQ 42
226#define SCIF_TXI_IRQ 43
227#define SCIF_IPR_ADDR INTC_IPRC
228#define SCIF_IPR_POS 1
229#define SCIF_PRIORITY 3
230#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
231#define SCIF1_ERI_IRQ 23
232#define SCIF1_RXI_IRQ 24
233#define SCIF1_BRI_IRQ 25
234#define SCIF1_TXI_IRQ 26
235#define SCIF1_IPR_ADDR INTC_IPRB
236#define SCIF1_IPR_POS 1
237#define SCIF1_PRIORITY 3
238#endif
239#endif
240
241/* NR_IRQS is made from three components:
242 * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
243 * 2. PINT_NR_IRQS - number of PINT interrupts
244 * 3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
245 */
246
247/* 1. ONCHIP_NR_IRQS */
248#ifdef CONFIG_SH_GENERIC
249# define ONCHIP_NR_IRQS 144
250#else
251# if defined(CONFIG_CPU_SUBTYPE_SH7604)
252# define ONCHIP_NR_IRQS 24 // Actually 21
253# elif defined(CONFIG_CPU_SUBTYPE_SH7707)
254# define ONCHIP_NR_IRQS 64
255# define PINT_NR_IRQS 16
256# elif defined(CONFIG_CPU_SUBTYPE_SH7708)
257# define ONCHIP_NR_IRQS 32
258# elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
259 defined(CONFIG_CPU_SUBTYPE_SH7705)
260# define ONCHIP_NR_IRQS 64 // Actually 61
261# define PINT_NR_IRQS 16
262# elif defined(CONFIG_CPU_SUBTYPE_SH7750)
263# define ONCHIP_NR_IRQS 48 // Actually 44
264# elif defined(CONFIG_CPU_SUBTYPE_SH7751)
265# define ONCHIP_NR_IRQS 72
266# elif defined(CONFIG_CPU_SUBTYPE_SH7760)
267# define ONCHIP_NR_IRQS 110
268# elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
269# define ONCHIP_NR_IRQS 72
270# elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
271# define ONCHIP_NR_IRQS 144
272# elif defined(CONFIG_CPU_SUBTYPE_SH7300)
273# define ONCHIP_NR_IRQS 109
274# endif
275#endif
276
277/* 2. PINT_NR_IRQS */
278#ifdef CONFIG_SH_GENERIC
279# define PINT_NR_IRQS 16
280#else
281# ifndef PINT_NR_IRQS
282# define PINT_NR_IRQS 0
283# endif
284#endif
285
286#if PINT_NR_IRQS > 0
287# define PINT_IRQ_BASE ONCHIP_NR_IRQS
288#endif
289
290/* 3. OFFCHIP_NR_IRQS */
291#ifdef CONFIG_SH_GENERIC
292# define OFFCHIP_NR_IRQS 16
293#else
294# if defined(CONFIG_HD64461)
295# define OFFCHIP_NR_IRQS 18
296# elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
297# define OFFCHIP_NR_IRQS 48
298# elif defined(CONFIG_HD64465)
299# define OFFCHIP_NR_IRQS 16
300# elif defined (CONFIG_SH_EC3104)
301# define OFFCHIP_NR_IRQS 16
302# elif defined (CONFIG_SH_DREAMCAST)
303# define OFFCHIP_NR_IRQS 96
304# else
305# define OFFCHIP_NR_IRQS 0
306# endif
307#endif
308
309#if OFFCHIP_NR_IRQS > 0
310# define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
311#endif
312
313/* NR_IRQS. 1+2+3 */
314#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
315
316/* In a generic kernel, NR_IRQS is an upper bound, and we should use
317 * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
318 */
319#ifdef CONFIG_SH_GENERIC
320# define ACTUAL_NR_IRQS (sh_mv.mv_nr_irqs)
321#else
322# define ACTUAL_NR_IRQS NR_IRQS
323#endif
324
325
326extern void disable_irq(unsigned int);
327extern void disable_irq_nosync(unsigned int);
328extern void enable_irq(unsigned int);
329
330/*
331 * Simple Mask Register Support
332 */
333extern void make_maskreg_irq(unsigned int irq);
334extern unsigned short *irq_mask_register;
335
336/*
337 * Function for "on chip support modules".
338 */
339extern void make_ipr_irq(unsigned int irq, unsigned int addr,
340 int pos, int priority);
341extern void make_imask_irq(unsigned int irq);
342
343#if defined(CONFIG_CPU_SUBTYPE_SH7300)
344#undef INTC_IPRA
345#undef INTC_IPRB
346#define INTC_IPRA 0xA414FEE2UL
347#define INTC_IPRB 0xA414FEE4UL
348#define INTC_IPRC 0xA4140016UL
349#define INTC_IPRD 0xA4140018UL
350#define INTC_IPRE 0xA414001AUL
351#define INTC_IPRF 0xA4080000UL
352#define INTC_IPRG 0xA4080002UL
353#define INTC_IPRH 0xA4080004UL
354#define INTC_IPRI 0xA4080006UL
355#define INTC_IPRJ 0xA4080008UL
356
357#define INTC_IMR0 0xA4080040UL
358#define INTC_IMR1 0xA4080042UL
359#define INTC_IMR2 0xA4080044UL
360#define INTC_IMR3 0xA4080046UL
361#define INTC_IMR4 0xA4080048UL
362#define INTC_IMR5 0xA408004AUL
363#define INTC_IMR6 0xA408004CUL
364#define INTC_IMR7 0xA408004EUL
365#define INTC_IMR8 0xA4080050UL
366#define INTC_IMR9 0xA4080052UL
367#define INTC_IMR10 0xA4080054UL
368
369#define INTC_IMCR0 0xA4080060UL
370#define INTC_IMCR1 0xA4080062UL
371#define INTC_IMCR2 0xA4080064UL
372#define INTC_IMCR3 0xA4080066UL
373#define INTC_IMCR4 0xA4080068UL
374#define INTC_IMCR5 0xA408006AUL
375#define INTC_IMCR6 0xA408006CUL
376#define INTC_IMCR7 0xA408006EUL
377#define INTC_IMCR8 0xA4080070UL
378#define INTC_IMCR9 0xA4080072UL
379#define INTC_IMCR10 0xA4080074UL
380
381#define INTC_ICR0 0xA414FEE0UL
382#define INTC_ICR1 0xA4140010UL
383
384#define INTC_IRR0 0xA4140004UL
385
386#define PORT_PACR 0xA4050100UL
387#define PORT_PBCR 0xA4050102UL
388#define PORT_PCCR 0xA4050104UL
389#define PORT_PDCR 0xA4050106UL
390#define PORT_PECR 0xA4050108UL
391#define PORT_PFCR 0xA405010AUL
392#define PORT_PGCR 0xA405010CUL
393#define PORT_PHCR 0xA405010EUL
394#define PORT_PJCR 0xA4050110UL
395#define PORT_PKCR 0xA4050112UL
396#define PORT_PLCR 0xA4050114UL
397#define PORT_SCPCR 0xA4050116UL
398#define PORT_PMCR 0xA4050118UL
399#define PORT_PNCR 0xA405011AUL
400#define PORT_PQCR 0xA405011CUL
401
402#define PORT_PSELA 0xA4050140UL
403#define PORT_PSELB 0xA4050142UL
404#define PORT_PSELC 0xA4050144UL
405
406#define PORT_HIZCRA 0xA4050146UL
407#define PORT_HIZCRB 0xA4050148UL
408#define PORT_DRVCR 0xA4050150UL
409
410#define PORT_PADR 0xA4050120UL
411#define PORT_PBDR 0xA4050122UL
412#define PORT_PCDR 0xA4050124UL
413#define PORT_PDDR 0xA4050126UL
414#define PORT_PEDR 0xA4050128UL
415#define PORT_PFDR 0xA405012AUL
416#define PORT_PGDR 0xA405012CUL
417#define PORT_PHDR 0xA405012EUL
418#define PORT_PJDR 0xA4050130UL
419#define PORT_PKDR 0xA4050132UL
420#define PORT_PLDR 0xA4050134UL
421#define PORT_SCPDR 0xA4050136UL
422#define PORT_PMDR 0xA4050138UL
423#define PORT_PNDR 0xA405013AUL
424#define PORT_PQDR 0xA405013CUL
425
426#define IRQ0_IRQ 32
427#define IRQ1_IRQ 33
428#define IRQ2_IRQ 34
429#define IRQ3_IRQ 35
430#define IRQ4_IRQ 36
431#define IRQ5_IRQ 37
432
433#define IRQ0_IPR_ADDR INTC_IPRC
434#define IRQ1_IPR_ADDR INTC_IPRC
435#define IRQ2_IPR_ADDR INTC_IPRC
436#define IRQ3_IPR_ADDR INTC_IPRC
437#define IRQ4_IPR_ADDR INTC_IPRD
438#define IRQ5_IPR_ADDR INTC_IPRD
439
440#define IRQ0_IPR_POS 0
441#define IRQ1_IPR_POS 1
442#define IRQ2_IPR_POS 2
443#define IRQ3_IPR_POS 3
444#define IRQ4_IPR_POS 0
445#define IRQ5_IPR_POS 1
446
447#define IRQ0_PRIORITY 1
448#define IRQ1_PRIORITY 1
449#define IRQ2_PRIORITY 1
450#define IRQ3_PRIORITY 1
451#define IRQ4_PRIORITY 1
452#define IRQ5_PRIORITY 1
453
454extern int ipr_irq_demux(int irq);
455#define __irq_demux(irq) ipr_irq_demux(irq)
456
457#elif defined(CONFIG_CPU_SUBTYPE_SH7604)
458#define INTC_IPRA 0xfffffee2UL
459#define INTC_IPRB 0xfffffe60UL
460
461#define INTC_VCRA 0xfffffe62UL
462#define INTC_VCRB 0xfffffe64UL
463#define INTC_VCRC 0xfffffe66UL
464#define INTC_VCRD 0xfffffe68UL
465
466#define INTC_VCRWDT 0xfffffee4UL
467#define INTC_VCRDIV 0xffffff0cUL
468#define INTC_VCRDMA0 0xffffffa0UL
469#define INTC_VCRDMA1 0xffffffa8UL
470
471#define INTC_ICR 0xfffffee0UL
472#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
473 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
474 defined(CONFIG_CPU_SUBTYPE_SH7709)
475#define INTC_IRR0 0xa4000004UL
476#define INTC_IRR1 0xa4000006UL
477#define INTC_IRR2 0xa4000008UL
478
479#define INTC_ICR0 0xfffffee0UL
480#define INTC_ICR1 0xa4000010UL
481#define INTC_ICR2 0xa4000012UL
482#define INTC_INTER 0xa4000014UL
483
484#define INTC_IPRC 0xa4000016UL
485#define INTC_IPRD 0xa4000018UL
486#define INTC_IPRE 0xa400001aUL
487#if defined(CONFIG_CPU_SUBTYPE_SH7707)
488#define INTC_IPRF 0xa400001cUL
489#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
490#define INTC_IPRF 0xa4080000UL
491#define INTC_IPRG 0xa4080002UL
492#define INTC_IPRH 0xa4080004UL
493#endif
494
495#define PORT_PACR 0xa4000100UL
496#define PORT_PBCR 0xa4000102UL
497#define PORT_PCCR 0xa4000104UL
498#define PORT_PFCR 0xa400010aUL
499#define PORT_PADR 0xa4000120UL
500#define PORT_PBDR 0xa4000122UL
501#define PORT_PCDR 0xa4000124UL
502#define PORT_PFDR 0xa400012aUL
503
504#define IRQ0_IRQ 32
505#define IRQ1_IRQ 33
506#define IRQ2_IRQ 34
507#define IRQ3_IRQ 35
508#define IRQ4_IRQ 36
509#define IRQ5_IRQ 37
510
511#define IRQ0_IPR_ADDR INTC_IPRC
512#define IRQ1_IPR_ADDR INTC_IPRC
513#define IRQ2_IPR_ADDR INTC_IPRC
514#define IRQ3_IPR_ADDR INTC_IPRC
515#define IRQ4_IPR_ADDR INTC_IPRD
516#define IRQ5_IPR_ADDR INTC_IPRD
517
518#define IRQ0_IPR_POS 0
519#define IRQ1_IPR_POS 1
520#define IRQ2_IPR_POS 2
521#define IRQ3_IPR_POS 3
522#define IRQ4_IPR_POS 0
523#define IRQ5_IPR_POS 1
524
525#define IRQ0_PRIORITY 1
526#define IRQ1_PRIORITY 1
527#define IRQ2_PRIORITY 1
528#define IRQ3_PRIORITY 1
529#define IRQ4_PRIORITY 1
530#define IRQ5_PRIORITY 1
531
532#define PINT0_IRQ 40
533#define PINT8_IRQ 41
534
535#define PINT0_IPR_ADDR INTC_IPRD
536#define PINT8_IPR_ADDR INTC_IPRD
537
538#define PINT0_IPR_POS 3
539#define PINT8_IPR_POS 2
540#define PINT0_PRIORITY 2
541#define PINT8_PRIORITY 2
542
543extern int ipr_irq_demux(int irq);
544#define __irq_demux(irq) ipr_irq_demux(irq)
545
546#else
547#define __irq_demux(irq) irq
548#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
549
550#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
551 defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
552#define INTC_ICR 0xffd00000
553#define INTC_ICR_NMIL (1<<15)
554#define INTC_ICR_MAI (1<<14)
555#define INTC_ICR_NMIB (1<<9)
556#define INTC_ICR_NMIE (1<<8)
557#define INTC_ICR_IRLM (1<<7)
558#endif
559
560#ifdef CONFIG_CPU_SUBTYPE_ST40STB1
561
562#define INTC2_FIRST_IRQ 64
563#define NR_INTC2_IRQS 25
564
565#define INTC2_BASE 0xfe080000
566#define INTC2_INTC2MODE (INTC2_BASE+0x80)
567
568#define INTC2_INTPRI_OFFSET 0x00
569#define INTC2_INTREQ_OFFSET 0x20
570#define INTC2_INTMSK_OFFSET 0x40
571#define INTC2_INTMSKCLR_OFFSET 0x60
572
573void make_intc2_irq(unsigned int irq,
574 unsigned int ipr_offset, unsigned int ipr_shift,
575 unsigned int msk_offset, unsigned int msk_shift,
576 unsigned int priority);
577void init_IRQ_intc2(void);
578void intc2_add_clear_irq(int irq, int (*fn)(int));
579
580#endif /* CONFIG_CPU_SUBTYPE_ST40STB1 */
581
582static inline int generic_irq_demux(int irq)
583{
584 return irq;
585}
586
587#define irq_canonicalize(irq) (irq)
588#define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq))
589
590struct irqaction;
591struct pt_regs;
592int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
593
594#if defined(CONFIG_CPU_SUBTYPE_SH73180)
595#include <asm/irq-sh73180.h>
596#endif
597
598#endif /* __ASM_SH_IRQ_H */
diff --git a/include/asm-sh/keyboard.h b/include/asm-sh/keyboard.h
new file mode 100644
index 000000000000..1103df003243
--- /dev/null
+++ b/include/asm-sh/keyboard.h
@@ -0,0 +1,14 @@
1#ifndef __ASM_SH_KEYBOARD_H
2#define __ASM_SH_KEYBOARD_H
3/*
4 * $Id: keyboard.h,v 1.1.1.1 2001/10/15 20:45:09 mrbrown Exp $
5 */
6
7#include <linux/kd.h>
8#include <linux/config.h>
9#include <asm/machvec.h>
10
11#ifdef CONFIG_SH_MPC1211
12#include <asm/mpc1211/keyboard-mpc1211.h>
13#endif
14#endif
diff --git a/include/asm-sh/kgdb.h b/include/asm-sh/kgdb.h
new file mode 100644
index 000000000000..1653ffb75fbe
--- /dev/null
+++ b/include/asm-sh/kgdb.h
@@ -0,0 +1,131 @@
1/*
2 * May be copied or modified under the terms of the GNU General Public
3 * License. See linux/COPYING for more information.
4 *
5 * Based on original code by Glenn Engel, Jim Kingdon,
6 * David Grothe <dave@gcom.com>, Tigran Aivazian, <tigran@sco.com> and
7 * Amit S. Kale <akale@veritas.com>
8 *
9 * Super-H port based on sh-stub.c (Ben Lee and Steve Chamberlain) by
10 * Henry Bell <henry.bell@st.com>
11 *
12 * Header file for low-level support for remote debug using GDB.
13 *
14 */
15
16#ifndef __KGDB_H
17#define __KGDB_H
18
19#include <asm/ptrace.h>
20
21struct console;
22
23/* Same as pt_regs but has vbr in place of syscall_nr */
24struct kgdb_regs {
25 unsigned long regs[16];
26 unsigned long pc;
27 unsigned long pr;
28 unsigned long sr;
29 unsigned long gbr;
30 unsigned long mach;
31 unsigned long macl;
32 unsigned long vbr;
33};
34
35/* State info */
36extern char kgdb_in_gdb_mode;
37extern int kgdb_done_init;
38extern int kgdb_enabled;
39extern int kgdb_nofault; /* Ignore bus errors (in gdb mem access) */
40extern int kgdb_halt; /* Execute initial breakpoint at startup */
41extern char in_nmi; /* Debounce flag to prevent NMI reentry*/
42
43/* SCI */
44extern int kgdb_portnum;
45extern int kgdb_baud;
46extern char kgdb_parity;
47extern char kgdb_bits;
48extern int kgdb_console_setup(struct console *, char *);
49
50/* Init and interface stuff */
51extern int kgdb_init(void);
52extern int (*kgdb_serial_setup)(void);
53extern int (*kgdb_getchar)(void);
54extern void (*kgdb_putchar)(int);
55
56struct kgdb_sermap {
57 char *name;
58 int namelen;
59 int (*setup_fn)(struct console *, char *);
60 struct kgdb_sermap *next;
61};
62extern void kgdb_register_sermap(struct kgdb_sermap *map);
63extern struct kgdb_sermap *kgdb_porttype;
64
65/* Trap functions */
66typedef void (kgdb_debug_hook_t)(struct pt_regs *regs);
67typedef void (kgdb_bus_error_hook_t)(void);
68extern kgdb_debug_hook_t *kgdb_debug_hook;
69extern kgdb_bus_error_hook_t *kgdb_bus_err_hook;
70
71extern void breakpoint(void);
72
73/* Console */
74struct console;
75void kgdb_console_write(struct console *co, const char *s, unsigned count);
76void kgdb_console_init(void);
77
78/* Prototypes for jmp fns */
79#define _JBLEN 9
80typedef int jmp_buf[_JBLEN];
81extern void longjmp(jmp_buf __jmpb, int __retval);
82extern int setjmp(jmp_buf __jmpb);
83
84/* Variadic macro to print our own message to the console */
85#define KGDB_PRINTK(...) printk("KGDB: " __VA_ARGS__)
86
87/* Forced breakpoint */
88#define BREAKPOINT() do { \
89 if (kgdb_enabled) { \
90 asm volatile("trapa #0xff"); \
91 } \
92} while (0)
93
94/* KGDB should be able to flush all kernel text space */
95#if defined(CONFIG_CPU_SH4)
96#define kgdb_flush_icache_range(start, end) \
97{ \
98 extern void __flush_purge_region(void *, int); \
99 __flush_purge_region((void*)(start), (int)(end) - (int)(start));\
100 flush_icache_range((start), (end)); \
101}
102#else
103#define kgdb_flush_icache_range(start, end) do { } while (0)
104#endif
105
106/* Kernel assert macros */
107#ifdef CONFIG_KGDB_KERNEL_ASSERTS
108
109/* Predefined conditions */
110#define KA_VALID_ERRNO(errno) ((errno) > 0 && (errno) <= EMEDIUMTYPE)
111#define KA_VALID_PTR_ERR(ptr) KA_VALID_ERRNO(-PTR_ERR(ptr))
112#define KA_VALID_KPTR(ptr) (!(ptr) || \
113 ((void *)(ptr) >= (void *)PAGE_OFFSET && \
114 (void *)(ptr) < ERR_PTR(-EMEDIUMTYPE)))
115#define KA_VALID_PTRORERR(errptr) \
116 (KA_VALID_KPTR(errptr) || KA_VALID_PTR_ERR(errptr))
117#define KA_HELD_GKL() (current->lock_depth >= 0)
118
119/* The actual assert */
120#define KGDB_ASSERT(condition, message) do { \
121 if (!(condition) && (kgdb_enabled)) { \
122 KGDB_PRINTK("Assertion failed at %s:%d: %s\n", \
123 __FILE__, __LINE__, message);\
124 BREAKPOINT(); \
125 } \
126} while (0)
127#else
128#define KGDB_ASSERT(condition, message)
129#endif
130
131#endif
diff --git a/include/asm-sh/kmap_types.h b/include/asm-sh/kmap_types.h
new file mode 100644
index 000000000000..2492ba07148f
--- /dev/null
+++ b/include/asm-sh/kmap_types.h
@@ -0,0 +1,33 @@
1#ifndef __SH_KMAP_TYPES_H
2#define __SH_KMAP_TYPES_H
3
4/* Dummy header just to define km_type. */
5
6#include <linux/config.h>
7
8#ifdef CONFIG_DEBUG_HIGHMEM
9# define D(n) __KM_FENCE_##n ,
10#else
11# define D(n)
12#endif
13
14enum km_type {
15D(0) KM_BOUNCE_READ,
16D(1) KM_SKB_SUNRPC_DATA,
17D(2) KM_SKB_DATA_SOFTIRQ,
18D(3) KM_USER0,
19D(4) KM_USER1,
20D(5) KM_BIO_SRC_IRQ,
21D(6) KM_BIO_DST_IRQ,
22D(7) KM_PTE0,
23D(8) KM_PTE1,
24D(9) KM_IRQ0,
25D(10) KM_IRQ1,
26D(11) KM_SOFTIRQ0,
27D(12) KM_SOFTIRQ1,
28D(13) KM_TYPE_NR
29};
30
31#undef D
32
33#endif
diff --git a/include/asm-sh/linkage.h b/include/asm-sh/linkage.h
new file mode 100644
index 000000000000..3565a4f4009f
--- /dev/null
+++ b/include/asm-sh/linkage.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_LINKAGE_H
2#define __ASM_LINKAGE_H
3
4#define __ALIGN .balign 4
5#define __ALIGN_STR ".balign 4"
6
7#endif
diff --git a/include/asm-sh/local.h b/include/asm-sh/local.h
new file mode 100644
index 000000000000..9ed9b9cb459a
--- /dev/null
+++ b/include/asm-sh/local.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_SH_LOCAL_H
2#define __ASM_SH_LOCAL_H
3
4#include <asm-generic/local.h>
5
6#endif /* __ASM_SH_LOCAL_H */
7
diff --git a/include/asm-sh/machvec.h b/include/asm-sh/machvec.h
new file mode 100644
index 000000000000..5771f4baa478
--- /dev/null
+++ b/include/asm-sh/machvec.h
@@ -0,0 +1,73 @@
1/*
2 * include/asm-sh/machvec.h
3 *
4 * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 */
9
10#ifndef _ASM_SH_MACHVEC_H
11#define _ASM_SH_MACHVEC_H 1
12
13#include <linux/config.h>
14#include <linux/types.h>
15#include <linux/time.h>
16
17#include <asm/machtypes.h>
18#include <asm/machvec_init.h>
19
20struct device;
21struct timeval;
22
23struct sh_machine_vector
24{
25 int mv_nr_irqs;
26
27 unsigned char (*mv_inb)(unsigned long);
28 unsigned short (*mv_inw)(unsigned long);
29 unsigned int (*mv_inl)(unsigned long);
30 void (*mv_outb)(unsigned char, unsigned long);
31 void (*mv_outw)(unsigned short, unsigned long);
32 void (*mv_outl)(unsigned int, unsigned long);
33
34 unsigned char (*mv_inb_p)(unsigned long);
35 unsigned short (*mv_inw_p)(unsigned long);
36 unsigned int (*mv_inl_p)(unsigned long);
37 void (*mv_outb_p)(unsigned char, unsigned long);
38 void (*mv_outw_p)(unsigned short, unsigned long);
39 void (*mv_outl_p)(unsigned int, unsigned long);
40
41 void (*mv_insb)(unsigned long port, void *addr, unsigned long count);
42 void (*mv_insw)(unsigned long port, void *addr, unsigned long count);
43 void (*mv_insl)(unsigned long port, void *addr, unsigned long count);
44 void (*mv_outsb)(unsigned long port, const void *addr, unsigned long count);
45 void (*mv_outsw)(unsigned long port, const void *addr, unsigned long count);
46 void (*mv_outsl)(unsigned long port, const void *addr, unsigned long count);
47
48 unsigned char (*mv_readb)(unsigned long);
49 unsigned short (*mv_readw)(unsigned long);
50 unsigned int (*mv_readl)(unsigned long);
51 void (*mv_writeb)(unsigned char, unsigned long);
52 void (*mv_writew)(unsigned short, unsigned long);
53 void (*mv_writel)(unsigned int, unsigned long);
54
55 void* (*mv_ioremap)(unsigned long offset, unsigned long size);
56 void (*mv_iounmap)(void *addr);
57
58 unsigned long (*mv_isa_port2addr)(unsigned long offset);
59
60 int (*mv_irq_demux)(int irq);
61
62 void (*mv_init_irq)(void);
63 void (*mv_init_pci)(void);
64
65 void (*mv_heartbeat)(void);
66
67 void *(*mv_consistent_alloc)(struct device *, size_t, dma_addr_t *, int);
68 int (*mv_consistent_free)(struct device *, size_t, void *, dma_addr_t);
69};
70
71extern struct sh_machine_vector sh_mv;
72
73#endif /* _ASM_SH_MACHVEC_H */
diff --git a/include/asm-sh/machvec_init.h b/include/asm-sh/machvec_init.h
new file mode 100644
index 000000000000..9e7de808f7f8
--- /dev/null
+++ b/include/asm-sh/machvec_init.h
@@ -0,0 +1,54 @@
1/*
2 * include/asm-sh/machvec_init.h
3 *
4 * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * This file has goodies to help simplify instantiation of machine vectors.
10 */
11
12#ifndef __SH_MACHVEC_INIT_H
13#define __SH_MACHVEC_INIT_H
14
15#include <linux/config.h>
16
17/*
18 * In a GENERIC kernel, we have lots of these vectors floating about,
19 * all but one of which we want to go away. In a non-GENERIC kernel,
20 * we want only one, ever.
21 *
22 * Accomplish this in the GENERIC kernel by puting all of the vectors
23 * in the .init.data section where they'll go away. We'll copy the
24 * one we want to the real alpha_mv vector in setup_arch.
25 *
26 * Accomplish this in a non-GENERIC kernel by ifdef'ing out all but
27 * one of the vectors, which will not reside in .init.data. We then
28 * alias this one vector to alpha_mv, so no copy is needed.
29 *
30 * Upshot: set __initdata to nothing for non-GENERIC kernels.
31 *
32 * Note we do the same thing for the UNKNOWN kernel, as we need to write
33 * to the machine vector while setting it up.
34 */
35
36#if defined(CONFIG_SH_GENERIC) || defined(CONFIG_SH_UNKNOWN)
37#define __initmv __attribute__((unused,__section__ (".machvec.init")))
38#define ALIAS_MV(x)
39#else
40#define __initmv
41
42/* GCC actually has a syntax for defining aliases, but is under some
43 delusion that you shouldn't be able to declare it extern somewhere
44 else beforehand. Fine. We'll do it ourselves. */
45#if 0
46#define ALIAS_MV(system) \
47 struct sh_machine_vector sh_mv __attribute__((alias("mv_"#system)));
48#else
49#define ALIAS_MV(system) \
50 asm(".global sh_mv\nsh_mv = mv_"#system );
51#endif
52#endif /* GENERIC */
53
54#endif /* __SH_MACHVEC_INIT_H */
diff --git a/include/asm-sh/mc146818rtc.h b/include/asm-sh/mc146818rtc.h
new file mode 100644
index 000000000000..1707cfb2915d
--- /dev/null
+++ b/include/asm-sh/mc146818rtc.h
@@ -0,0 +1,176 @@
1/*
2 * Machine dependent access functions for RTC registers.
3 */
4#ifndef _ASM_MC146818RTC_H
5#define _ASM_MC146818RTC_H
6
7#ifdef CONFIG_SH_MPC1211
8#undef _ASM_MC146818RTC_H
9#undef RTC_IRQ
10#include <asm/mpc1211/mc146818rtc.h>
11#else
12
13#include <asm/rtc.h>
14
15#define RTC_ALWAYS_BCD 1
16
17/* FIXME:RTC Interrupt feature is not implemented yet. */
18#undef RTC_IRQ
19#define RTC_IRQ 0
20
21#if defined(CONFIG_CPU_SH3)
22#define RTC_PORT(n) (R64CNT+(n)*2)
23#define CMOS_READ(addr) __CMOS_READ(addr,b)
24#define CMOS_WRITE(val,addr) __CMOS_WRITE(val,addr,b)
25
26#elif defined(CONFIG_SH_SECUREEDGE5410)
27#include <asm/snapgear/io.h>
28
29#define RTC_PORT(n) SECUREEDGE_IOPORT_ADDR
30#define CMOS_READ(addr) secureedge5410_cmos_read(addr)
31#define CMOS_WRITE(val,addr) secureedge5410_cmos_write(val,addr)
32extern unsigned char secureedge5410_cmos_read(int addr);
33extern void secureedge5410_cmos_write(unsigned char val, int addr);
34
35#elif defined(CONFIG_CPU_SH4)
36#define RTC_PORT(n) (R64CNT+(n)*4)
37#define CMOS_READ(addr) __CMOS_READ(addr,w)
38#define CMOS_WRITE(val,addr) __CMOS_WRITE(val,addr,w)
39#endif
40
41#define __CMOS_READ(addr, s) ({ \
42 unsigned char val=0, rcr1, rcr2, r64cnt, retry; \
43 switch(addr) { \
44 case RTC_SECONDS: \
45 val = ctrl_inb(RSECCNT); \
46 break; \
47 case RTC_SECONDS_ALARM: \
48 val = ctrl_inb(RSECAR); \
49 break; \
50 case RTC_MINUTES: \
51 val = ctrl_inb(RMINCNT); \
52 break; \
53 case RTC_MINUTES_ALARM: \
54 val = ctrl_inb(RMINAR); \
55 break; \
56 case RTC_HOURS: \
57 val = ctrl_inb(RHRCNT); \
58 break; \
59 case RTC_HOURS_ALARM: \
60 val = ctrl_inb(RHRAR); \
61 break; \
62 case RTC_DAY_OF_WEEK: \
63 val = ctrl_inb(RWKCNT); \
64 break; \
65 case RTC_DAY_OF_MONTH: \
66 val = ctrl_inb(RDAYCNT); \
67 break; \
68 case RTC_MONTH: \
69 val = ctrl_inb(RMONCNT); \
70 break; \
71 case RTC_YEAR: \
72 val = ctrl_in##s(RYRCNT); \
73 break; \
74 case RTC_REG_A: /* RTC_FREQ_SELECT */ \
75 rcr2 = ctrl_inb(RCR2); \
76 val = (rcr2 & RCR2_PESMASK) >> 4; \
77 rcr1 = ctrl_inb(RCR1); \
78 rcr1 = (rcr1 & (RCR1_CIE | RCR1_AIE)) | RCR1_AF;\
79 retry = 0; \
80 do { \
81 ctrl_outb(rcr1, RCR1); /* clear CF */ \
82 r64cnt = ctrl_inb(R64CNT); \
83 } while((ctrl_inb(RCR1) & RCR1_CF) && retry++ < 1000);\
84 r64cnt ^= RTC_BIT_INVERTED; \
85 if(r64cnt == 0x7f || r64cnt == 0) \
86 val |= RTC_UIP; \
87 break; \
88 case RTC_REG_B: /* RTC_CONTROL */ \
89 rcr1 = ctrl_inb(RCR1); \
90 rcr2 = ctrl_inb(RCR2); \
91 if(rcr1 & RCR1_CIE) val |= RTC_UIE; \
92 if(rcr1 & RCR1_AIE) val |= RTC_AIE; \
93 if(rcr2 & RCR2_PESMASK) val |= RTC_PIE; \
94 if(!(rcr2 & RCR2_START))val |= RTC_SET; \
95 val |= RTC_24H; \
96 break; \
97 case RTC_REG_C: /* RTC_INTR_FLAGS */ \
98 rcr1 = ctrl_inb(RCR1); \
99 rcr1 &= ~(RCR1_CF | RCR1_AF); \
100 ctrl_outb(rcr1, RCR1); \
101 rcr2 = ctrl_inb(RCR2); \
102 rcr2 &= ~RCR2_PEF; \
103 ctrl_outb(rcr2, RCR2); \
104 break; \
105 case RTC_REG_D: /* RTC_VALID */ \
106 /* Always valid ... */ \
107 val = RTC_VRT; \
108 break; \
109 default: \
110 break; \
111 } \
112 val; \
113})
114
115#define __CMOS_WRITE(val, addr, s) ({ \
116 unsigned char rcr1,rcr2; \
117 switch(addr) { \
118 case RTC_SECONDS: \
119 ctrl_outb(val, RSECCNT); \
120 break; \
121 case RTC_SECONDS_ALARM: \
122 ctrl_outb(val, RSECAR); \
123 break; \
124 case RTC_MINUTES: \
125 ctrl_outb(val, RMINCNT); \
126 break; \
127 case RTC_MINUTES_ALARM: \
128 ctrl_outb(val, RMINAR); \
129 break; \
130 case RTC_HOURS: \
131 ctrl_outb(val, RHRCNT); \
132 break; \
133 case RTC_HOURS_ALARM: \
134 ctrl_outb(val, RHRAR); \
135 break; \
136 case RTC_DAY_OF_WEEK: \
137 ctrl_outb(val, RWKCNT); \
138 break; \
139 case RTC_DAY_OF_MONTH: \
140 ctrl_outb(val, RDAYCNT); \
141 break; \
142 case RTC_MONTH: \
143 ctrl_outb(val, RMONCNT); \
144 break; \
145 case RTC_YEAR: \
146 ctrl_out##s((ctrl_in##s(RYRCNT) & 0xff00) | (val & 0xff), RYRCNT);\
147 break; \
148 case RTC_REG_A: /* RTC_FREQ_SELECT */ \
149 rcr2 = ctrl_inb(RCR2); \
150 if((val & RTC_DIV_CTL) == RTC_DIV_RESET2) \
151 rcr2 |= RCR2_RESET; \
152 ctrl_outb(rcr2, RCR2); \
153 break; \
154 case RTC_REG_B: /* RTC_CONTROL */ \
155 rcr1 = (ctrl_inb(RCR1) & 0x99) | RCR1_AF; \
156 if(val & RTC_AIE) rcr1 |= RCR1_AIE; \
157 else rcr1 &= ~RCR1_AIE; \
158 if(val & RTC_UIE) rcr1 |= RCR1_CIE; \
159 else rcr1 &= ~RCR1_CIE; \
160 ctrl_outb(rcr1, RCR1); \
161 rcr2 = ctrl_inb(RCR2); \
162 if(val & RTC_SET) rcr2 &= ~RCR2_START; \
163 else rcr2 |= RCR2_START; \
164 ctrl_outb(rcr2, RCR2); \
165 break; \
166 case RTC_REG_C: /* RTC_INTR_FLAGS */ \
167 break; \
168 case RTC_REG_D: /* RTC_VALID */ \
169 break; \
170 default: \
171 break; \
172 } \
173})
174
175#endif /* CONFIG_SH_MPC1211 */
176#endif /* _ASM_MC146818RTC_H */
diff --git a/include/asm-sh/microdev/io.h b/include/asm-sh/microdev/io.h
new file mode 100644
index 000000000000..f2ca4ac8c88a
--- /dev/null
+++ b/include/asm-sh/microdev/io.h
@@ -0,0 +1,53 @@
1/*
2 * linux/include/asm-sh/io_microdev.h
3 *
4 * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
5 *
6 * IO functions for the SuperH SH4-202 MicroDev board.
7 *
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
10 *
11 */
12
13
14#ifndef _ASM_SH_IO_MICRODEV_H
15#define _ASM_SH_IO_MICRODEV_H
16
17extern unsigned long microdev_isa_port2addr(unsigned long offset);
18
19extern unsigned char microdev_inb(unsigned long port);
20extern unsigned short microdev_inw(unsigned long port);
21extern unsigned int microdev_inl(unsigned long port);
22
23extern void microdev_outb(unsigned char value, unsigned long port);
24extern void microdev_outw(unsigned short value, unsigned long port);
25extern void microdev_outl(unsigned int value, unsigned long port);
26
27extern unsigned char microdev_inb_p(unsigned long port);
28extern unsigned short microdev_inw_p(unsigned long port);
29extern unsigned int microdev_inl_p(unsigned long port);
30
31extern void microdev_outb_p(unsigned char value, unsigned long port);
32extern void microdev_outw_p(unsigned short value, unsigned long port);
33extern void microdev_outl_p(unsigned int value, unsigned long port);
34
35extern void microdev_insb(unsigned long port, void *addr, unsigned long count);
36extern void microdev_insw(unsigned long port, void *addr, unsigned long count);
37extern void microdev_insl(unsigned long port, void *addr, unsigned long count);
38
39extern void microdev_outsb(unsigned long port, const void *addr, unsigned long count);
40extern void microdev_outsw(unsigned long port, const void *addr, unsigned long count);
41extern void microdev_outsl(unsigned long port, const void *addr, unsigned long count);
42
43#if defined(CONFIG_PCI)
44extern unsigned char microdev_pci_inb(unsigned long port);
45extern unsigned short microdev_pci_inw(unsigned long port);
46extern unsigned long microdev_pci_inl(unsigned long port);
47extern void microdev_pci_outb(unsigned char data, unsigned long port);
48extern void microdev_pci_outw(unsigned short data, unsigned long port);
49extern void microdev_pci_outl(unsigned long data, unsigned long port);
50#endif
51
52#endif /* _ASM_SH_IO_MICRODEV_H */
53
diff --git a/include/asm-sh/microdev/irq.h b/include/asm-sh/microdev/irq.h
new file mode 100644
index 000000000000..47f6f77a65f0
--- /dev/null
+++ b/include/asm-sh/microdev/irq.h
@@ -0,0 +1,72 @@
1/*
2 * linux/include/asm-sh/irq_microdev.h
3 *
4 * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
5 *
6 * IRQ functions for the SuperH SH4-202 MicroDev board.
7 *
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
10 *
11 */
12
13
14#ifndef _ASM_SH_IRQ_MICRODEV_H
15#define _ASM_SH_IRQ_MICRODEV_H
16
17extern void init_microdev_irq(void);
18extern void microdev_print_fpga_intc_status(void);
19
20
21 /*
22 * The following are useful macros for manipulating the
23 * interrupt controller (INTC) on the CPU-board FPGA.
24 * It should be noted that there is an INTC on the FPGA,
25 * and a seperate INTC on the SH4-202 core - these are
26 * two different things, both of which need to be prorammed
27 * to correctly route - unfortunately, they have the
28 * same name and abbreviations!
29 */
30#define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */
31#define MICRODEV_FPGA_INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */
32#define MICRODEV_FPGA_INTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */
33#define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interupt mask to enable/disable INTC in CPU-board FPGA */
34#define MICRODEV_FPGA_INTPRI_REG(n) (MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */
35#define MICRODEV_FPGA_INTPRI_LEVEL(n,x) ((x)<<(((n)%8)*4)) /* MICRODEV_FPGA_INTPRI_LEVEL(int_number, int_level) */
36#define MICRODEV_FPGA_INTPRI_MASK(n) (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */
37#define MICRODEV_FPGA_INTSRC_REG (MICRODEV_FPGA_INTC_BASE+0x30ul) /* Interrupt Source Register on INTC on CPU-board FPGA */
38#define MICRODEV_FPGA_INTREQ_REG (MICRODEV_FPGA_INTC_BASE+0x38ul) /* Interrupt Request Register on INTC on CPU-board FPGA */
39
40
41 /*
42 * The following are the IRQ numbers for the Linux Kernel for external interrupts.
43 * i.e. the numbers seen by 'cat /proc/interrupt'.
44 */
45#define MICRODEV_LINUX_IRQ_KEYBOARD 1 /* SuperIO Keyboard */
46#define MICRODEV_LINUX_IRQ_SERIAL1 2 /* SuperIO Serial #1 */
47#define MICRODEV_LINUX_IRQ_ETHERNET 3 /* on-board Ethnernet */
48#define MICRODEV_LINUX_IRQ_SERIAL2 4 /* SuperIO Serial #2 */
49#define MICRODEV_LINUX_IRQ_USB_HC 7 /* on-board USB HC */
50#define MICRODEV_LINUX_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */
51#define MICRODEV_LINUX_IRQ_IDE2 13 /* SuperIO IDE #2 */
52#define MICRODEV_LINUX_IRQ_IDE1 14 /* SuperIO IDE #1 */
53
54 /*
55 * The following are the IRQ numbers for the INTC on the FPGA for external interrupts.
56 * i.e. the bits in the INTC registers in the FPGA.
57 */
58#define MICRODEV_FPGA_IRQ_KEYBOARD 1 /* SuperIO Keyboard */
59#define MICRODEV_FPGA_IRQ_SERIAL1 3 /* SuperIO Serial #1 */
60#define MICRODEV_FPGA_IRQ_SERIAL2 4 /* SuperIO Serial #2 */
61#define MICRODEV_FPGA_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */
62#define MICRODEV_FPGA_IRQ_IDE1 14 /* SuperIO IDE #1 */
63#define MICRODEV_FPGA_IRQ_IDE2 15 /* SuperIO IDE #2 */
64#define MICRODEV_FPGA_IRQ_USB_HC 16 /* on-board USB HC */
65#define MICRODEV_FPGA_IRQ_ETHERNET 18 /* on-board Ethnernet */
66
67#define MICRODEV_IRQ_PCI_INTA 8
68#define MICRODEV_IRQ_PCI_INTB 9
69#define MICRODEV_IRQ_PCI_INTC 10
70#define MICRODEV_IRQ_PCI_INTD 11
71
72#endif /* _ASM_SH_IRQ_MICRODEV_H */
diff --git a/include/asm-sh/mman.h b/include/asm-sh/mman.h
new file mode 100644
index 000000000000..3ebab5f79db7
--- /dev/null
+++ b/include/asm-sh/mman.h
@@ -0,0 +1,43 @@
1#ifndef __ASM_SH_MMAN_H
2#define __ASM_SH_MMAN_H
3
4#define PROT_READ 0x1 /* page can be read */
5#define PROT_WRITE 0x2 /* page can be written */
6#define PROT_EXEC 0x4 /* page can be executed */
7#define PROT_SEM 0x8 /* page may be used for atomic ops */
8#define PROT_NONE 0x0 /* page can not be accessed */
9#define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
10#define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */
11
12#define MAP_SHARED 0x01 /* Share changes */
13#define MAP_PRIVATE 0x02 /* Changes are private */
14#define MAP_TYPE 0x0f /* Mask for type of mapping */
15#define MAP_FIXED 0x10 /* Interpret addr exactly */
16#define MAP_ANONYMOUS 0x20 /* don't use a file */
17
18#define MAP_GROWSDOWN 0x0100 /* stack-like segment */
19#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
20#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
21#define MAP_LOCKED 0x2000 /* pages are locked */
22#define MAP_NORESERVE 0x4000 /* don't check for reservations */
23#define MAP_POPULATE 0x8000 /* populate (prefault) page tables */
24#define MAP_NONBLOCK 0x10000 /* do not block on IO */
25
26#define MS_ASYNC 1 /* sync memory asynchronously */
27#define MS_INVALIDATE 2 /* invalidate the caches */
28#define MS_SYNC 4 /* synchronous memory sync */
29
30#define MCL_CURRENT 1 /* lock all current mappings */
31#define MCL_FUTURE 2 /* lock all future mappings */
32
33#define MADV_NORMAL 0x0 /* default page-in behavior */
34#define MADV_RANDOM 0x1 /* page-in minimum required */
35#define MADV_SEQUENTIAL 0x2 /* read-ahead aggressively */
36#define MADV_WILLNEED 0x3 /* pre-fault pages */
37#define MADV_DONTNEED 0x4 /* discard these pages */
38
39/* compatibility flags */
40#define MAP_ANON MAP_ANONYMOUS
41#define MAP_FILE 0
42
43#endif /* __ASM_SH_MMAN_H */
diff --git a/include/asm-sh/mmu.h b/include/asm-sh/mmu.h
new file mode 100644
index 000000000000..72f07be6117f
--- /dev/null
+++ b/include/asm-sh/mmu.h
@@ -0,0 +1,29 @@
1#ifndef __MMU_H
2#define __MMU_H
3
4#if !defined(CONFIG_MMU)
5
6struct mm_rblock_struct {
7 int size;
8 int refcount;
9 void *kblock;
10};
11
12struct mm_tblock_struct {
13 struct mm_rblock_struct *rblock;
14 struct mm_tblock_struct *next;
15};
16
17typedef struct {
18 struct mm_tblock_struct tblock;
19 unsigned long end_brk;
20} mm_context_t;
21
22#else
23
24/* Default "unsigned long" context */
25typedef unsigned long mm_context_t;
26
27#endif /* CONFIG_MMU */
28#endif /* __MMH_H */
29
diff --git a/include/asm-sh/mmu_context.h b/include/asm-sh/mmu_context.h
new file mode 100644
index 000000000000..6760d064bd02
--- /dev/null
+++ b/include/asm-sh/mmu_context.h
@@ -0,0 +1,206 @@
1/*
2 * Copyright (C) 1999 Niibe Yutaka
3 * Copyright (C) 2003 Paul Mundt
4 *
5 * ASID handling idea taken from MIPS implementation.
6 */
7#ifndef __ASM_SH_MMU_CONTEXT_H
8#define __ASM_SH_MMU_CONTEXT_H
9#ifdef __KERNEL__
10
11#include <asm/cpu/mmu_context.h>
12#include <asm/tlbflush.h>
13#include <asm/pgalloc.h>
14#include <asm/uaccess.h>
15#include <asm/io.h>
16
17/*
18 * The MMU "context" consists of two things:
19 * (a) TLB cache version (or round, cycle whatever expression you like)
20 * (b) ASID (Address Space IDentifier)
21 */
22
23/*
24 * Cache of MMU context last used.
25 */
26extern unsigned long mmu_context_cache;
27
28#define MMU_CONTEXT_ASID_MASK 0x000000ff
29#define MMU_CONTEXT_VERSION_MASK 0xffffff00
30#define MMU_CONTEXT_FIRST_VERSION 0x00000100
31#define NO_CONTEXT 0
32
33/* ASID is 8-bit value, so it can't be 0x100 */
34#define MMU_NO_ASID 0x100
35
36/*
37 * Virtual Page Number mask
38 */
39#define MMU_VPN_MASK 0xfffff000
40
41#ifdef CONFIG_MMU
42/*
43 * Get MMU context if needed.
44 */
45static __inline__ void
46get_mmu_context(struct mm_struct *mm)
47{
48 extern void flush_tlb_all(void);
49 unsigned long mc = mmu_context_cache;
50
51 /* Check if we have old version of context. */
52 if (((mm->context ^ mc) & MMU_CONTEXT_VERSION_MASK) == 0)
53 /* It's up to date, do nothing */
54 return;
55
56 /* It's old, we need to get new context with new version. */
57 mc = ++mmu_context_cache;
58 if (!(mc & MMU_CONTEXT_ASID_MASK)) {
59 /*
60 * We exhaust ASID of this version.
61 * Flush all TLB and start new cycle.
62 */
63 flush_tlb_all();
64 /*
65 * Fix version; Note that we avoid version #0
66 * to distingush NO_CONTEXT.
67 */
68 if (!mc)
69 mmu_context_cache = mc = MMU_CONTEXT_FIRST_VERSION;
70 }
71 mm->context = mc;
72}
73
74/*
75 * Initialize the context related info for a new mm_struct
76 * instance.
77 */
78static __inline__ int init_new_context(struct task_struct *tsk,
79 struct mm_struct *mm)
80{
81 mm->context = NO_CONTEXT;
82
83 return 0;
84}
85
86/*
87 * Destroy context related info for an mm_struct that is about
88 * to be put to rest.
89 */
90static __inline__ void destroy_context(struct mm_struct *mm)
91{
92 /* Do nothing */
93}
94
95static __inline__ void set_asid(unsigned long asid)
96{
97 unsigned long __dummy;
98
99 __asm__ __volatile__ ("mov.l %2, %0\n\t"
100 "and %3, %0\n\t"
101 "or %1, %0\n\t"
102 "mov.l %0, %2"
103 : "=&r" (__dummy)
104 : "r" (asid), "m" (__m(MMU_PTEH)),
105 "r" (0xffffff00));
106}
107
108static __inline__ unsigned long get_asid(void)
109{
110 unsigned long asid;
111
112 __asm__ __volatile__ ("mov.l %1, %0"
113 : "=r" (asid)
114 : "m" (__m(MMU_PTEH)));
115 asid &= MMU_CONTEXT_ASID_MASK;
116 return asid;
117}
118
119/*
120 * After we have set current->mm to a new value, this activates
121 * the context for the new mm so we see the new mappings.
122 */
123static __inline__ void activate_context(struct mm_struct *mm)
124{
125 get_mmu_context(mm);
126 set_asid(mm->context & MMU_CONTEXT_ASID_MASK);
127}
128
129/* MMU_TTB can be used for optimizing the fault handling.
130 (Currently not used) */
131static __inline__ void switch_mm(struct mm_struct *prev,
132 struct mm_struct *next,
133 struct task_struct *tsk)
134{
135 if (likely(prev != next)) {
136 unsigned long __pgdir = (unsigned long)next->pgd;
137
138 __asm__ __volatile__("mov.l %0, %1"
139 : /* no output */
140 : "r" (__pgdir), "m" (__m(MMU_TTB)));
141 activate_context(next);
142 }
143}
144
145#define deactivate_mm(tsk,mm) do { } while (0)
146
147#define activate_mm(prev, next) \
148 switch_mm((prev),(next),NULL)
149
150static __inline__ void
151enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
152{
153}
154#else /* !CONFIG_MMU */
155#define get_mmu_context(mm) do { } while (0)
156#define init_new_context(tsk,mm) (0)
157#define destroy_context(mm) do { } while (0)
158#define set_asid(asid) do { } while (0)
159#define get_asid() (0)
160#define activate_context(mm) do { } while (0)
161#define switch_mm(prev,next,tsk) do { } while (0)
162#define deactivate_mm(tsk,mm) do { } while (0)
163#define activate_mm(prev,next) do { } while (0)
164#define enter_lazy_tlb(mm,tsk) do { } while (0)
165#endif /* CONFIG_MMU */
166
167#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4)
168/*
169 * If this processor has an MMU, we need methods to turn it off/on ..
170 * paging_init() will also have to be updated for the processor in
171 * question.
172 */
173static inline void enable_mmu(void)
174{
175 /* Enable MMU */
176 ctrl_outl(MMU_CONTROL_INIT, MMUCR);
177
178 /* The manual suggests doing some nops after turning on the MMU */
179 __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop\n\t");
180
181 if (mmu_context_cache == NO_CONTEXT)
182 mmu_context_cache = MMU_CONTEXT_FIRST_VERSION;
183
184 set_asid(mmu_context_cache & MMU_CONTEXT_ASID_MASK);
185}
186
187static inline void disable_mmu(void)
188{
189 unsigned long cr;
190
191 cr = ctrl_inl(MMUCR);
192 cr &= ~MMU_CONTROL_INIT;
193 ctrl_outl(cr, MMUCR);
194 __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop\n\t");
195}
196#else
197/*
198 * MMU control handlers for processors lacking memory
199 * management hardware.
200 */
201#define enable_mmu() do { BUG(); } while (0)
202#define disable_mmu() do { BUG(); } while (0)
203#endif
204
205#endif /* __KERNEL__ */
206#endif /* __ASM_SH_MMU_CONTEXT_H */
diff --git a/include/asm-sh/mmzone.h b/include/asm-sh/mmzone.h
new file mode 100644
index 000000000000..0e7406601fdf
--- /dev/null
+++ b/include/asm-sh/mmzone.h
@@ -0,0 +1,61 @@
1/*
2 * linux/include/asm-sh/mmzone.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8#ifndef __ASM_SH_MMZONE_H
9#define __ASM_SH_MMZONE_H
10
11#include <linux/config.h>
12
13#ifdef CONFIG_DISCONTIGMEM
14
15/* Currently, just for HP690 */
16#define PHYSADDR_TO_NID(phys) ((((phys) - __MEMORY_START) >= 0x01000000)?1:0)
17
18extern pg_data_t discontig_page_data[MAX_NUMNODES];
19extern bootmem_data_t discontig_node_bdata[MAX_NUMNODES];
20
21/*
22 * Following are macros that each numa implmentation must define.
23 */
24
25/*
26 * Given a kernel address, find the home node of the underlying memory.
27 */
28#define KVADDR_TO_NID(kaddr) PHYSADDR_TO_NID(__pa(kaddr))
29
30/*
31 * Return a pointer to the node data for node n.
32 */
33#define NODE_DATA(nid) (&discontig_page_data[nid])
34
35/*
36 * NODE_MEM_MAP gives the kaddr for the mem_map of the node.
37 */
38#define NODE_MEM_MAP(nid) (NODE_DATA(nid)->node_mem_map)
39
40#define phys_to_page(phys) \
41({ unsigned int node = PHYSADDR_TO_NID(phys); \
42 NODE_MEM_MAP(node) \
43 + (((phys) - NODE_DATA(node)->node_start_paddr) >> PAGE_SHIFT); })
44
45static inline int is_valid_page(struct page *page)
46{
47 unsigned int i;
48
49 for (i = 0; i < MAX_NUMNODES; i++) {
50 if (page >= NODE_MEM_MAP(i) &&
51 page < NODE_MEM_MAP(i) + NODE_DATA(i)->node_size)
52 return 1;
53 }
54 return 0;
55}
56
57#define VALID_PAGE(page) is_valid_page(page)
58#define page_to_phys(page) PHYSADDR(page_address(page))
59
60#endif /* CONFIG_DISCONTIGMEM */
61#endif
diff --git a/include/asm-sh/module.h b/include/asm-sh/module.h
new file mode 100644
index 000000000000..118d5a2b228f
--- /dev/null
+++ b/include/asm-sh/module.h
@@ -0,0 +1,40 @@
1#ifndef _ASM_SH_MODULE_H
2#define _ASM_SH_MODULE_H
3
4/*
5 * This file contains the SH architecture specific module code.
6 */
7
8struct mod_arch_specific {
9 /* Nothing to see here .. */
10};
11
12#define Elf_Shdr Elf32_Shdr
13#define Elf_Sym Elf32_Sym
14#define Elf_Ehdr Elf32_Ehdr
15
16#ifdef CONFIG_CPU_LITTLE_ENDIAN
17# ifdef CONFIG_CPU_SH2
18# define MODULE_PROC_FAMILY "SH2LE "
19# elif defined CONFIG_CPU_SH3
20# define MODULE_PROC_FAMILY "SH3LE "
21# elif defined CONFIG_CPU_SH4
22# define MODULE_PROC_FAMILY "SH4LE "
23# else
24# error unknown processor family
25# endif
26#else
27# ifdef CONFIG_CPU_SH2
28# define MODULE_PROC_FAMILY "SH2BE "
29# elif defined CONFIG_CPU_SH3
30# define MODULE_PROC_FAMILY "SH3BE "
31# elif defined CONFIG_CPU_SH4
32# define MODULE_PROC_FAMILY "SH4BE "
33# else
34# error unknown processor family
35# endif
36#endif
37
38#define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY
39
40#endif /* _ASM_SH_MODULE_H */
diff --git a/include/asm-sh/mpc1211/dma.h b/include/asm-sh/mpc1211/dma.h
new file mode 100644
index 000000000000..0a2fdab3e454
--- /dev/null
+++ b/include/asm-sh/mpc1211/dma.h
@@ -0,0 +1,304 @@
1/* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
3 * Written by Hennus Bergman, 1992.
4 * High DMA channel support & info by Hannu Savolainen
5 * and John Boyd, Nov. 1992.
6 */
7
8#ifndef _ASM_MPC1211_DMA_H
9#define _ASM_MPC1211_DMA_H
10
11#include <linux/config.h>
12#include <linux/spinlock.h> /* And spinlocks */
13#include <asm/io.h> /* need byte IO */
14#include <linux/delay.h>
15
16
17#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
18#define dma_outb outb_p
19#else
20#define dma_outb outb
21#endif
22
23#define dma_inb inb
24
25/*
26 * NOTES about DMA transfers:
27 *
28 * controller 1: channels 0-3, byte operations, ports 00-1F
29 * controller 2: channels 4-7, word operations, ports C0-DF
30 *
31 * - ALL registers are 8 bits only, regardless of transfer size
32 * - channel 4 is not used - cascades 1 into 2.
33 * - channels 0-3 are byte - addresses/counts are for physical bytes
34 * - channels 5-7 are word - addresses/counts are for physical words
35 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
36 * - transfer count loaded to registers is 1 less than actual count
37 * - controller 2 offsets are all even (2x offsets for controller 1)
38 * - page registers for 5-7 don't use data bit 0, represent 128K pages
39 * - page registers for 0-3 use bit 0, represent 64K pages
40 *
41 * DMA transfers are limited to the lower 16MB of _physical_ memory.
42 * Note that addresses loaded into registers must be _physical_ addresses,
43 * not logical addresses (which may differ if paging is active).
44 *
45 * Address mapping for channels 0-3:
46 *
47 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
48 * | ... | | ... | | ... |
49 * | ... | | ... | | ... |
50 * | ... | | ... | | ... |
51 * P7 ... P0 A7 ... A0 A7 ... A0
52 * | Page | Addr MSB | Addr LSB | (DMA registers)
53 *
54 * Address mapping for channels 5-7:
55 *
56 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
57 * | ... | \ \ ... \ \ \ ... \ \
58 * | ... | \ \ ... \ \ \ ... \ (not used)
59 * | ... | \ \ ... \ \ \ ... \
60 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
61 * | Page | Addr MSB | Addr LSB | (DMA registers)
62 *
63 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
64 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
65 * the hardware level, so odd-byte transfers aren't possible).
66 *
67 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
68 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
69 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
70 *
71 */
72
73#define MAX_DMA_CHANNELS 8
74
75/* The maximum address that we can perform a DMA transfer to on this platform */
76#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
77
78/* 8237 DMA controllers */
79#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
80#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
81
82/* DMA controller registers */
83#define DMA1_CMD_REG 0x08 /* command register (w) */
84#define DMA1_STAT_REG 0x08 /* status register (r) */
85#define DMA1_REQ_REG 0x09 /* request register (w) */
86#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
87#define DMA1_MODE_REG 0x0B /* mode register (w) */
88#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
89#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
90#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
91#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
92#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
93
94#define DMA2_CMD_REG 0xD0 /* command register (w) */
95#define DMA2_STAT_REG 0xD0 /* status register (r) */
96#define DMA2_REQ_REG 0xD2 /* request register (w) */
97#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
98#define DMA2_MODE_REG 0xD6 /* mode register (w) */
99#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
100#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
101#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
102#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
103#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
104
105#define DMA_ADDR_0 0x00 /* DMA address registers */
106#define DMA_ADDR_1 0x02
107#define DMA_ADDR_2 0x04
108#define DMA_ADDR_3 0x06
109#define DMA_ADDR_4 0xC0
110#define DMA_ADDR_5 0xC4
111#define DMA_ADDR_6 0xC8
112#define DMA_ADDR_7 0xCC
113
114#define DMA_CNT_0 0x01 /* DMA count registers */
115#define DMA_CNT_1 0x03
116#define DMA_CNT_2 0x05
117#define DMA_CNT_3 0x07
118#define DMA_CNT_4 0xC2
119#define DMA_CNT_5 0xC6
120#define DMA_CNT_6 0xCA
121#define DMA_CNT_7 0xCE
122
123#define DMA_PAGE_0 0x87 /* DMA page registers */
124#define DMA_PAGE_1 0x83
125#define DMA_PAGE_2 0x81
126#define DMA_PAGE_3 0x82
127#define DMA_PAGE_5 0x8B
128#define DMA_PAGE_6 0x89
129#define DMA_PAGE_7 0x8A
130
131#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
132#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
133#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
134
135#define DMA_AUTOINIT 0x10
136
137
138extern spinlock_t dma_spin_lock;
139
140static __inline__ unsigned long claim_dma_lock(void)
141{
142 unsigned long flags;
143 spin_lock_irqsave(&dma_spin_lock, flags);
144 return flags;
145}
146
147static __inline__ void release_dma_lock(unsigned long flags)
148{
149 spin_unlock_irqrestore(&dma_spin_lock, flags);
150}
151
152/* enable/disable a specific DMA channel */
153static __inline__ void enable_dma(unsigned int dmanr)
154{
155 if (dmanr<=3)
156 dma_outb(dmanr, DMA1_MASK_REG);
157 else
158 dma_outb(dmanr & 3, DMA2_MASK_REG);
159}
160
161static __inline__ void disable_dma(unsigned int dmanr)
162{
163 if (dmanr<=3)
164 dma_outb(dmanr | 4, DMA1_MASK_REG);
165 else
166 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
167}
168
169/* Clear the 'DMA Pointer Flip Flop'.
170 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
171 * Use this once to initialize the FF to a known state.
172 * After that, keep track of it. :-)
173 * --- In order to do that, the DMA routines below should ---
174 * --- only be used while holding the DMA lock ! ---
175 */
176static __inline__ void clear_dma_ff(unsigned int dmanr)
177{
178 if (dmanr<=3)
179 dma_outb(0, DMA1_CLEAR_FF_REG);
180 else
181 dma_outb(0, DMA2_CLEAR_FF_REG);
182}
183
184/* set mode (above) for a specific DMA channel */
185static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
186{
187 if (dmanr<=3)
188 dma_outb(mode | dmanr, DMA1_MODE_REG);
189 else
190 dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
191}
192
193/* Set only the page register bits of the transfer address.
194 * This is used for successive transfers when we know the contents of
195 * the lower 16 bits of the DMA current address register, but a 64k boundary
196 * may have been crossed.
197 */
198static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
199{
200 switch(dmanr) {
201 case 0:
202 dma_outb( pagenr & 0xff, DMA_PAGE_0);
203 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_0 + 0x400);
204 break;
205 case 1:
206 dma_outb( pagenr & 0xff, DMA_PAGE_1);
207 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_1 + 0x400);
208 break;
209 case 2:
210 dma_outb( pagenr & 0xff, DMA_PAGE_2);
211 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_2 + 0x400);
212 break;
213 case 3:
214 dma_outb( pagenr & 0xff, DMA_PAGE_3);
215 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_3 + 0x400);
216 break;
217 case 5:
218 dma_outb( pagenr & 0xfe, DMA_PAGE_5);
219 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_5 + 0x400);
220 break;
221 case 6:
222 dma_outb( pagenr & 0xfe, DMA_PAGE_6);
223 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_6 + 0x400);
224 break;
225 case 7:
226 dma_outb( pagenr & 0xfe, DMA_PAGE_7);
227 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_7 + 0x400);
228 break;
229 }
230}
231
232
233/* Set transfer address & page bits for specific DMA channel.
234 * Assumes dma flipflop is clear.
235 */
236static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
237{
238 set_dma_page(dmanr, a>>16);
239 if (dmanr <= 3) {
240 dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
241 dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
242 } else {
243 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
244 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
245 }
246}
247
248
249/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
250 * a specific DMA channel.
251 * You must ensure the parameters are valid.
252 * NOTE: from a manual: "the number of transfers is one more
253 * than the initial word count"! This is taken into account.
254 * Assumes dma flip-flop is clear.
255 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
256 */
257static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
258{
259 count--;
260 if (dmanr <= 3) {
261 dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
262 dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
263 } else {
264 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
265 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
266 }
267}
268
269
270/* Get DMA residue count. After a DMA transfer, this
271 * should return zero. Reading this while a DMA transfer is
272 * still in progress will return unpredictable results.
273 * If called before the channel has been used, it may return 1.
274 * Otherwise, it returns the number of _bytes_ left to transfer.
275 *
276 * Assumes DMA flip-flop is clear.
277 */
278static __inline__ int get_dma_residue(unsigned int dmanr)
279{
280 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
281 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
282
283 /* using short to get 16-bit wrap around */
284 unsigned short count;
285
286 count = 1 + dma_inb(io_port);
287 count += dma_inb(io_port) << 8;
288 return (dmanr<=3)? count : (count<<1);
289}
290
291
292/* These are in kernel/dma.c: */
293extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
294extern void free_dma(unsigned int dmanr); /* release it again */
295
296/* From PCI */
297
298#ifdef CONFIG_PCI
299extern int isa_dma_bridge_buggy;
300#else
301#define isa_dma_bridge_buggy (0)
302#endif
303
304#endif /* _ASM_MPC1211_DMA_H */
diff --git a/include/asm-sh/mpc1211/io.h b/include/asm-sh/mpc1211/io.h
new file mode 100644
index 000000000000..eba8a0b5fd7b
--- /dev/null
+++ b/include/asm-sh/mpc1211/io.h
@@ -0,0 +1,22 @@
1/*
2 * include/asm-sh/io_mpc1211.h
3 *
4 * Copyright 2001 Saito.K & Jeanne
5 *
6 * IO functions for an Interface MPC-1211
7 */
8
9#ifndef _ASM_SH_IO_MPC1211_H
10#define _ASM_SH_IO_MPC1211_H
11
12#include <linux/time.h>
13
14extern int mpc1211_irq_demux(int irq);
15
16extern void init_mpc1211_IRQ(void);
17extern void heartbeat_mpc1211(void);
18
19extern void mpc1211_rtc_gettimeofday(struct timeval *tv);
20extern int mpc1211_rtc_settimeofday(const struct timeval *tv);
21
22#endif /* _ASM_SH_IO_MPC1211_H */
diff --git a/include/asm-sh/mpc1211/keyboard.h b/include/asm-sh/mpc1211/keyboard.h
new file mode 100644
index 000000000000..5f0b9088c796
--- /dev/null
+++ b/include/asm-sh/mpc1211/keyboard.h
@@ -0,0 +1,64 @@
1/*
2 * MPC1211 specific keybord definitions
3 * Taken from the old asm-i386/keybord.h for PC/AT-style definitions
4 * created 3 Nov 1996 by Geert Uytterhoeven.
5 */
6
7#ifdef __KERNEL__
8
9#include <linux/kernel.h>
10#include <linux/ioport.h>
11#include <linux/kd.h>
12#include <linux/pm.h>
13#include <asm/io.h>
14
15#define KEYBOARD_IRQ 1
16#define DISABLE_KBD_DURING_INTERRUPTS 0
17
18extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
19extern int pckbd_getkeycode(unsigned int scancode);
20extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
21 char raw_mode);
22extern char pckbd_unexpected_up(unsigned char keycode);
23extern void pckbd_leds(unsigned char leds);
24extern void pckbd_init_hw(void);
25extern int pckbd_pm_resume(struct pm_dev *, pm_request_t, void *);
26extern pm_callback pm_kbd_request_override;
27extern unsigned char pckbd_sysrq_xlate[128];
28
29#define kbd_setkeycode pckbd_setkeycode
30#define kbd_getkeycode pckbd_getkeycode
31#define kbd_translate pckbd_translate
32#define kbd_unexpected_up pckbd_unexpected_up
33#define kbd_leds pckbd_leds
34#define kbd_init_hw pckbd_init_hw
35#define kbd_sysrq_xlate pckbd_sysrq_xlate
36
37#define SYSRQ_KEY 0x54
38
39/* resource allocation */
40#define kbd_request_region()
41#define kbd_request_irq(handler) request_irq(KEYBOARD_IRQ, handler, 0, \
42 "keyboard", NULL)
43
44/* How to access the keyboard macros on this platform. */
45#define kbd_read_input() inb(KBD_DATA_REG)
46#define kbd_read_status() inb(KBD_STATUS_REG)
47#define kbd_write_output(val) outb(val, KBD_DATA_REG)
48#define kbd_write_command(val) outb(val, KBD_CNTL_REG)
49
50/* Some stoneage hardware needs delays after some operations. */
51#define kbd_pause() do { } while(0)
52
53/*
54 * Machine specific bits for the PS/2 driver
55 */
56
57#define AUX_IRQ 12
58
59#define aux_request_irq(hand, dev_id) \
60 request_irq(AUX_IRQ, hand, SA_SHIRQ, "PS2 Mouse", dev_id)
61
62#define aux_free_irq(dev_id) free_irq(AUX_IRQ, dev_id)
63
64#endif /* __KERNEL__ */
diff --git a/include/asm-sh/mpc1211/m1543c.h b/include/asm-sh/mpc1211/m1543c.h
new file mode 100644
index 000000000000..c95d13236c3b
--- /dev/null
+++ b/include/asm-sh/mpc1211/m1543c.h
@@ -0,0 +1,200 @@
1#ifndef __ASM_SH_M1543C_H
2#define __ASM_SH_M1543C_H
3
4/*
5 * linux/include/asm-sh/m1543c.h
6 * Copyright (C) 2001 Nobuhiro Sakawa
7 * M1543C:PCI-ISA Bus Bridge with Super IO Chip support
8 *
9 * from
10 *
11 * linux/include/asm-sh/smc37c93x.h
12 *
13 * Copyright (C) 2000 Kazumoto Kojima
14 *
15 * SMSC 37C93x Super IO Chip support
16 */
17
18/* Default base I/O address */
19#define FDC_PRIMARY_BASE 0x3f0
20#define IDE1_PRIMARY_BASE 0x1f0
21#define IDE1_SECONDARY_BASE 0x170
22#define PARPORT_PRIMARY_BASE 0x378
23#define COM1_PRIMARY_BASE 0x2f8
24#define COM2_PRIMARY_BASE 0x3f8
25#define COM3_PRIMARY_BASE 0x3e8
26#define RTC_PRIMARY_BASE 0x070
27#define KBC_PRIMARY_BASE 0x060
28#define AUXIO_PRIMARY_BASE 0x000 /* XXX */
29#define I8259_M_CR 0x20
30#define I8259_M_MR 0x21
31#define I8259_S_CR 0xa0
32#define I8259_S_MR 0xa1
33
34/* Logical device number */
35#define LDN_FDC 0
36#define LDN_IDE1 1
37#define LDN_IDE2 2
38#define LDN_PARPORT 3
39#define LDN_COM1 4
40#define LDN_COM2 5
41#define LDN_COM3 11
42#define LDN_RTC 6
43#define LDN_KBC 7
44
45/* Configuration port and key */
46#define CONFIG_PORT 0x3f0
47#define INDEX_PORT CONFIG_PORT
48#define DATA_PORT 0x3f1
49#define CONFIG_ENTER1 0x51
50#define CONFIG_ENTER2 0x23
51#define CONFIG_EXIT 0xbb
52
53/* Configuration index */
54#define CURRENT_LDN_INDEX 0x07
55#define POWER_CONTROL_INDEX 0x22
56#define ACTIVATE_INDEX 0x30
57#define IO_BASE_HI_INDEX 0x60
58#define IO_BASE_LO_INDEX 0x61
59#define IRQ_SELECT_INDEX 0x70
60#define PS2_IRQ_INDEX 0x72
61#define DMA_SELECT_INDEX 0x74
62
63/* UART stuff. Only for debugging. */
64/* UART Register */
65
66#define UART_RBR 0x0 /* Receiver Buffer Register (Read Only) */
67#define UART_THR 0x0 /* Transmitter Holding Register (Write Only) */
68#define UART_IER 0x2 /* Interrupt Enable Register */
69#define UART_IIR 0x4 /* Interrupt Ident Register (Read Only) */
70#define UART_FCR 0x4 /* FIFO Control Register (Write Only) */
71#define UART_LCR 0x6 /* Line Control Register */
72#define UART_MCR 0x8 /* MODEM Control Register */
73#define UART_LSR 0xa /* Line Status Register */
74#define UART_MSR 0xc /* MODEM Status Register */
75#define UART_SCR 0xe /* Scratch Register */
76#define UART_DLL 0x0 /* Divisor Latch (LS) */
77#define UART_DLM 0x2 /* Divisor Latch (MS) */
78
79#ifndef __ASSEMBLY__
80typedef struct uart_reg {
81 volatile __u16 rbr;
82 volatile __u16 ier;
83 volatile __u16 iir;
84 volatile __u16 lcr;
85 volatile __u16 mcr;
86 volatile __u16 lsr;
87 volatile __u16 msr;
88 volatile __u16 scr;
89} uart_reg;
90#endif /* ! __ASSEMBLY__ */
91
92/* Alias for Write Only Register */
93
94#define thr rbr
95#define tcr iir
96
97/* Alias for Divisor Latch Register */
98
99#define dll rbr
100#define dlm ier
101#define fcr iir
102
103/* Interrupt Enable Register */
104
105#define IER_ERDAI 0x0100 /* Enable Received Data Available Interrupt */
106#define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */
107#define IER_ELSI 0x0400 /* Enable Receiver Line Status Interrupt */
108#define IER_EMSI 0x0800 /* Enable MODEM Status Interrupt */
109
110/* Interrupt Ident Register */
111
112#define IIR_IP 0x0100 /* "0" if Interrupt Pending */
113#define IIR_IIB0 0x0200 /* Interrupt ID Bit 0 */
114#define IIR_IIB1 0x0400 /* Interrupt ID Bit 1 */
115#define IIR_IIB2 0x0800 /* Interrupt ID Bit 2 */
116#define IIR_FIFO 0xc000 /* FIFOs enabled */
117
118/* FIFO Control Register */
119
120#define FCR_FEN 0x0100 /* FIFO enable */
121#define FCR_RFRES 0x0200 /* Receiver FIFO reset */
122#define FCR_TFRES 0x0400 /* Transmitter FIFO reset */
123#define FCR_DMA 0x0800 /* DMA mode select */
124#define FCR_RTL 0x4000 /* Receiver triger (LSB) */
125#define FCR_RTM 0x8000 /* Receiver triger (MSB) */
126
127/* Line Control Register */
128
129#define LCR_WLS0 0x0100 /* Word Length Select Bit 0 */
130#define LCR_WLS1 0x0200 /* Word Length Select Bit 1 */
131#define LCR_STB 0x0400 /* Number of Stop Bits */
132#define LCR_PEN 0x0800 /* Parity Enable */
133#define LCR_EPS 0x1000 /* Even Parity Select */
134#define LCR_SP 0x2000 /* Stick Parity */
135#define LCR_SB 0x4000 /* Set Break */
136#define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */
137
138/* MODEM Control Register */
139
140#define MCR_DTR 0x0100 /* Data Terminal Ready */
141#define MCR_RTS 0x0200 /* Request to Send */
142#define MCR_OUT1 0x0400 /* Out 1 */
143#define MCR_IRQEN 0x0800 /* IRQ Enable */
144#define MCR_LOOP 0x1000 /* Loop */
145
146/* Line Status Register */
147
148#define LSR_DR 0x0100 /* Data Ready */
149#define LSR_OE 0x0200 /* Overrun Error */
150#define LSR_PE 0x0400 /* Parity Error */
151#define LSR_FE 0x0800 /* Framing Error */
152#define LSR_BI 0x1000 /* Break Interrupt */
153#define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */
154#define LSR_TEMT 0x4000 /* Transmitter Empty */
155#define LSR_FIFOE 0x8000 /* Receiver FIFO error */
156
157/* MODEM Status Register */
158
159#define MSR_DCTS 0x0100 /* Delta Clear to Send */
160#define MSR_DDSR 0x0200 /* Delta Data Set Ready */
161#define MSR_TERI 0x0400 /* Trailing Edge Ring Indicator */
162#define MSR_DDCD 0x0800 /* Delta Data Carrier Detect */
163#define MSR_CTS 0x1000 /* Clear to Send */
164#define MSR_DSR 0x2000 /* Data Set Ready */
165#define MSR_RI 0x4000 /* Ring Indicator */
166#define MSR_DCD 0x8000 /* Data Carrier Detect */
167
168/* Baud Rate Divisor */
169
170#define UART_CLK (1843200) /* 1.8432 MHz */
171#define UART_BAUD(x) (UART_CLK / (16 * (x)))
172
173/* RTC register definition */
174#define RTC_SECONDS 0
175#define RTC_SECONDS_ALARM 1
176#define RTC_MINUTES 2
177#define RTC_MINUTES_ALARM 3
178#define RTC_HOURS 4
179#define RTC_HOURS_ALARM 5
180#define RTC_DAY_OF_WEEK 6
181#define RTC_DAY_OF_MONTH 7
182#define RTC_MONTH 8
183#define RTC_YEAR 9
184#define RTC_FREQ_SELECT 10
185# define RTC_UIP 0x80
186# define RTC_DIV_CTL 0x70
187/* This RTC can work under 32.768KHz clock only. */
188# define RTC_OSC_ENABLE 0x20
189# define RTC_OSC_DISABLE 0x00
190#define RTC_CONTROL 11
191# define RTC_SET 0x80
192# define RTC_PIE 0x40
193# define RTC_AIE 0x20
194# define RTC_UIE 0x10
195# define RTC_SQWE 0x08
196# define RTC_DM_BINARY 0x04
197# define RTC_24H 0x02
198# define RTC_DST_EN 0x01
199
200#endif /* __ASM_SH_M1543C_H */
diff --git a/include/asm-sh/mpc1211/mc146818rtc.h b/include/asm-sh/mpc1211/mc146818rtc.h
new file mode 100644
index 000000000000..0ec78f66cea4
--- /dev/null
+++ b/include/asm-sh/mpc1211/mc146818rtc.h
@@ -0,0 +1,6 @@
1/*
2 * MPC1211 uses PC/AT style RTC definitions.
3 */
4#include <asm-i386/mc146818rtc.h>
5
6
diff --git a/include/asm-sh/mpc1211/mpc1211.h b/include/asm-sh/mpc1211/mpc1211.h
new file mode 100644
index 000000000000..fa456c3e4e01
--- /dev/null
+++ b/include/asm-sh/mpc1211/mpc1211.h
@@ -0,0 +1,18 @@
1#ifndef __ASM_SH_MPC1211_H
2#define __ASM_SH_MPC1211_H
3
4/*
5 * linux/include/asm-sh/mpc1211.h
6 *
7 * Copyright (C) 2001 Saito.K & Jeanne
8 *
9 * Interface MPC-1211 support
10 */
11
12#define PA_PCI_IO (0xa4000000) /* PCI I/O space */
13#define PA_PCI_MEM (0xb0000000) /* PCI MEM space */
14
15#define PCIPAR (0xa4000cf8) /* PCI Config address */
16#define PCIPDR (0xa4000cfc) /* PCI Config data */
17
18#endif /* __ASM_SH_MPC1211_H */
diff --git a/include/asm-sh/mpc1211/pci.h b/include/asm-sh/mpc1211/pci.h
new file mode 100644
index 000000000000..5d3712c3a701
--- /dev/null
+++ b/include/asm-sh/mpc1211/pci.h
@@ -0,0 +1,40 @@
1/*
2 * Low-Level PCI Support for MPC-1211
3 *
4 * (c) 2002 Saito.K & Jeanne
5 *
6 */
7
8#ifndef _PCI_MPC1211_H_
9#define _PCI_MPC1211_H_
10
11#include <linux/pci.h>
12
13/* set debug level 4=verbose...1=terse */
14//#define DEBUG_PCI 3
15#undef DEBUG_PCI
16
17#ifdef DEBUG_PCI
18#define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); }
19#else
20#define PCIDBG(n, x...)
21#endif
22
23/* startup values */
24#define PCI_PROBE_BIOS 1
25#define PCI_PROBE_CONF1 2
26#define PCI_PROBE_CONF2 4
27#define PCI_NO_SORT 0x100
28#define PCI_BIOS_SORT 0x200
29#define PCI_NO_CHECKS 0x400
30#define PCI_ASSIGN_ROMS 0x1000
31#define PCI_BIOS_IRQ_SCAN 0x2000
32
33/* MPC-1211 Specific Values */
34#define PCIPAR (0xa4000cf8) /* PCI Config address */
35#define PCIPDR (0xa4000cfc) /* PCI Config data */
36
37#define PA_PCI_IO (0xa4000000) /* PCI I/O space */
38#define PA_PCI_MEM (0xb0000000) /* PCI MEM space */
39
40#endif /* _PCI_MPC1211_H_ */
diff --git a/include/asm-sh/msgbuf.h b/include/asm-sh/msgbuf.h
new file mode 100644
index 000000000000..517432343fb5
--- /dev/null
+++ b/include/asm-sh/msgbuf.h
@@ -0,0 +1,31 @@
1#ifndef __ASM_SH_MSGBUF_H
2#define __ASM_SH_MSGBUF_H
3
4/*
5 * The msqid64_ds structure for i386 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct msqid64_ds {
15 struct ipc64_perm msg_perm;
16 __kernel_time_t msg_stime; /* last msgsnd time */
17 unsigned long __unused1;
18 __kernel_time_t msg_rtime; /* last msgrcv time */
19 unsigned long __unused2;
20 __kernel_time_t msg_ctime; /* last change time */
21 unsigned long __unused3;
22 unsigned long msg_cbytes; /* current number of bytes on queue */
23 unsigned long msg_qnum; /* number of messages in queue */
24 unsigned long msg_qbytes; /* max number of bytes on queue */
25 __kernel_pid_t msg_lspid; /* pid of last msgsnd */
26 __kernel_pid_t msg_lrpid; /* last receive pid */
27 unsigned long __unused4;
28 unsigned long __unused5;
29};
30
31#endif /* __ASM_SH_MSGBUF_H */
diff --git a/include/asm-sh/namei.h b/include/asm-sh/namei.h
new file mode 100644
index 000000000000..338a5d947143
--- /dev/null
+++ b/include/asm-sh/namei.h
@@ -0,0 +1,17 @@
1/* $Id: namei.h,v 1.3 2000/07/04 06:24:49 gniibe Exp $
2 * linux/include/asm-sh/namei.h
3 *
4 * Included from linux/fs/namei.c
5 */
6
7#ifndef __ASM_SH_NAMEI_H
8#define __ASM_SH_NAMEI_H
9
10/* This dummy routine maybe changed to something useful
11 * for /usr/gnemul/ emulation stuff.
12 * Look at asm-sparc/namei.h for details.
13 */
14
15#define __emul_prefix() NULL
16
17#endif /* __ASM_SH_NAMEI_H */
diff --git a/include/asm-sh/numnodes.h b/include/asm-sh/numnodes.h
new file mode 100644
index 000000000000..f73e85b72ecb
--- /dev/null
+++ b/include/asm-sh/numnodes.h
@@ -0,0 +1,7 @@
1#ifndef _ASM_MAX_NUMNODES_H
2#define _ASM_MAX_NUMNODES_H
3
4/* Max 2 Nodes */
5#define NODES_SHIFT 1
6
7#endif /* _ASM_MAX_NUMNODES_H */
diff --git a/include/asm-sh/overdrive/fpga.h b/include/asm-sh/overdrive/fpga.h
new file mode 100644
index 000000000000..1cd87992c124
--- /dev/null
+++ b/include/asm-sh/overdrive/fpga.h
@@ -0,0 +1,15 @@
1/*
2 * Copyright (C) 2000 David J. Mckay (david.mckay@st.com)
3 *
4 * May be copied or modified under the terms of the GNU General Public
5 * License. See linux/COPYING for more information.
6 *
7 */
8
9#ifndef __FPGA_OD_H__
10#define __FPGA_OD_H__
11
12/* This routine will program up the fpga which interfaces to the galileo */
13int init_overdrive_fpga(void);
14
15#endif
diff --git a/include/asm-sh/overdrive/gt64111.h b/include/asm-sh/overdrive/gt64111.h
new file mode 100644
index 000000000000..01d58bc13a44
--- /dev/null
+++ b/include/asm-sh/overdrive/gt64111.h
@@ -0,0 +1,109 @@
1#ifndef _GT64111_H_
2#define _GT64111_H_
3
4#define MASTER_INTERFACE 0x0
5#define RAS10_LO_DEC_ADR 0x8
6#define RAS10_HI_DEC_ADR 0x10
7#define RAS32_LO_DEC_ADR 0x18
8#define RAS32_HI_DEC_ADR 0x20
9#define CS20_LO_DEC_ADR 0x28
10#define CS20_HI_DEC_ADR 0x30
11#define CS3_LO_DEC_ADR 0x38
12#define CS3_HI_DEC_ADR 0x40
13#define PCI_IO_LO_DEC_ADR 0x48
14#define PCI_IO_HI_DEC_ADR 0x50
15#define PCI_MEM0_LO_DEC_ADR 0x58
16#define PCI_MEM0_HI_DEC_ADR 0x60
17#define INTERNAL_SPACE_DEC 0x68
18#define BUS_ERR_ADR_LO_CPU 0x70
19#define READONLY0 0x78
20#define PCI_MEM1_LO_DEC_ADR 0x80
21#define PCI_MEM1_HI_DEC_ADR 0x88
22#define RAS0_LO_DEC_ADR 0x400
23#define RAS0_HI_DEC_ADR 0x404
24#define RAS1_LO_DEC_ADR 0x408
25#define RAS1_HI_DEC_ADR 0x40c
26#define RAS2_LO_DEC_ADR 0x410
27#define RAS2_HI_DEC_ADR 0x414
28#define RAS3_LO_DEC_ADR 0x418
29#define RAS3_HI_DEC_ADR 0x41c
30#define DEV_CS0_LO_DEC_ADR 0x420
31#define DEV_CS0_HI_DEC_ADR 0x424
32#define DEV_CS1_LO_DEC_ADR 0x428
33#define DEV_CS1_HI_DEC_ADR 0x42c
34#define DEV_CS2_LO_DEC_ADR 0x430
35#define DEV_CS2_HI_DEC_ADR 0x434
36#define DEV_CS3_LO_DEC_ADR 0x438
37#define DEV_CS3_HI_DEC_ADR 0x43c
38#define DEV_BOOTCS_LO_DEC_ADR 0x440
39#define DEV_BOOTCS_HI_DEC_ADR 0x444
40#define DEV_ADR_DEC_ERR 0x470
41#define DRAM_CFG 0x448
42#define DRAM_BANK0_PARMS 0x44c
43#define DRAM_BANK1_PARMS 0x450
44#define DRAM_BANK2_PARMS 0x454
45#define DRAM_BANK3_PARMS 0x458
46#define DEV_BANK0_PARMS 0x45c
47#define DEV_BANK1_PARMS 0x460
48#define DEV_BANK2_PARMS 0x464
49#define DEV_BANK3_PARMS 0x468
50#define DEV_BOOT_BANK_PARMS 0x46c
51#define CH0_DMA_BYTECOUNT 0x800
52#define CH1_DMA_BYTECOUNT 0x804
53#define CH2_DMA_BYTECOUNT 0x808
54#define CH3_DMA_BYTECOUNT 0x80c
55#define CH0_DMA_SRC_ADR 0x810
56#define CH1_DMA_SRC_ADR 0x814
57#define CH2_DMA_SRC_ADR 0x818
58#define CH3_DMA_SRC_ADR 0x81c
59#define CH0_DMA_DST_ADR 0x820
60#define CH1_DMA_DST_ADR 0x824
61#define CH2_DMA_DST_ADR 0x828
62#define CH3_DMA_DST_ADR 0x82c
63#define CH0_NEXT_REC_PTR 0x830
64#define CH1_NEXT_REC_PTR 0x834
65#define CH2_NEXT_REC_PTR 0x838
66#define CH3_NEXT_REC_PTR 0x83c
67#define CH0_CTRL 0x840
68#define CH1_CTRL 0x844
69#define CH2_CTRL 0x848
70#define CH3_CTRL 0x84c
71#define DMA_ARBITER 0x860
72#define TIMER0 0x850
73#define TIMER1 0x854
74#define TIMER2 0x858
75#define TIMER3 0x85c
76#define TIMER_CTRL 0x864
77#define PCI_CMD 0xc00
78#define PCI_TIMEOUT 0xc04
79#define PCI_RAS10_BANK_SIZE 0xc08
80#define PCI_RAS32_BANK_SIZE 0xc0c
81#define PCI_CS20_BANK_SIZE 0xc10
82#define PCI_CS3_BANK_SIZE 0xc14
83#define PCI_SERRMASK 0xc28
84#define PCI_INTACK 0xc34
85#define PCI_BAR_EN 0xc3c
86#define PCI_CFG_ADR 0xcf8
87#define PCI_CFG_DATA 0xcfc
88#define PCI_INTCAUSE 0xc18
89#define PCI_MAST_MASK 0xc1c
90#define PCI_PCIMASK 0xc24
91#define BAR_ENABLE_ADR 0xc3c
92
93/* These are config registers, accessible via PCI space */
94#define PCI_CONFIG_RAS10_BASE_ADR 0x010
95#define PCI_CONFIG_RAS32_BASE_ADR 0x014
96#define PCI_CONFIG_CS20_BASE_ADR 0x018
97#define PCI_CONFIG_CS3_BASE_ADR 0x01c
98#define PCI_CONFIG_INT_REG_MM_ADR 0x020
99#define PCI_CONFIG_INT_REG_IO_ADR 0x024
100#define PCI_CONFIG_BOARD_VENDOR 0x02c
101#define PCI_CONFIG_ROM_ADR 0x030
102#define PCI_CONFIG_INT_PIN_LINE 0x03c
103
104
105
106
107
108#endif
109
diff --git a/include/asm-sh/overdrive/io.h b/include/asm-sh/overdrive/io.h
new file mode 100644
index 000000000000..0dba700e9643
--- /dev/null
+++ b/include/asm-sh/overdrive/io.h
@@ -0,0 +1,39 @@
1/*
2 * include/asm-sh/io_od.h
3 *
4 * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * IO functions for an STMicroelectronics Overdrive
10 */
11
12#ifndef _ASM_SH_IO_OD_H
13#define _ASM_SH_IO_OD_H
14
15extern unsigned char od_inb(unsigned long port);
16extern unsigned short od_inw(unsigned long port);
17extern unsigned int od_inl(unsigned long port);
18
19extern void od_outb(unsigned char value, unsigned long port);
20extern void od_outw(unsigned short value, unsigned long port);
21extern void od_outl(unsigned int value, unsigned long port);
22
23extern unsigned char od_inb_p(unsigned long port);
24extern unsigned short od_inw_p(unsigned long port);
25extern unsigned int od_inl_p(unsigned long port);
26extern void od_outb_p(unsigned char value, unsigned long port);
27extern void od_outw_p(unsigned short value, unsigned long port);
28extern void od_outl_p(unsigned int value, unsigned long port);
29
30extern void od_insb(unsigned long port, void *addr, unsigned long count);
31extern void od_insw(unsigned long port, void *addr, unsigned long count);
32extern void od_insl(unsigned long port, void *addr, unsigned long count);
33extern void od_outsb(unsigned long port, const void *addr, unsigned long count);
34extern void od_outsw(unsigned long port, const void *addr, unsigned long count);
35extern void od_outsl(unsigned long port, const void *addr, unsigned long count);
36
37extern unsigned long od_isa_port2addr(unsigned long offset);
38
39#endif /* _ASM_SH_IO_OD_H */
diff --git a/include/asm-sh/overdrive/overdrive.h b/include/asm-sh/overdrive/overdrive.h
new file mode 100644
index 000000000000..aa62ae68c55c
--- /dev/null
+++ b/include/asm-sh/overdrive/overdrive.h
@@ -0,0 +1,89 @@
1/*
2 * Copyright (C) 2000 David J. Mckay (david.mckay@st.com)
3 *
4 * May be copied or modified under the terms of the GNU General Public
5 * License. See linux/COPYING for more information.
6 *
7 */
8
9#include <linux/config.h>
10
11#ifndef __OVERDRIVE_H__
12#define __OVERDRIVE_H__
13
14#define OVERDRIVE_INT_CT 0xa3a00000
15#define OVERDRIVE_INT_DT 0xa3b00000
16
17#define OVERDRIVE_CTRL 0xa3000000
18
19/* Shoving all these bits into the same register is not a good idea.
20 * As soon as I get a spare moment, I'll change the FPGA and put each
21 * bit in a separate register
22 */
23
24#define VALID_CTRL_BITS 0x1f
25
26#define ENABLE_RS232_MASK 0x1e
27#define DISABLE_RS232_BIT 0x01
28
29#define ENABLE_NMI_MASK 0x1d
30#define DISABLE_NMI_BIT 0x02
31
32#define RESET_PCI_MASK 0x1b
33#define ENABLE_PCI_BIT 0x04
34
35#define ENABLE_LED_MASK 0x17
36#define DISABLE_LED_BIT 0x08
37
38#define RESET_FPGA_MASK 0x0f
39#define ENABLE_FPGA_BIT 0x10
40
41
42#define FPGA_DCLK_ADDRESS 0xA3C00000
43
44#define FPGA_DATA 0x01 /* W */
45#define FPGA_CONFDONE 0x02 /* R */
46#define FPGA_NOT_STATUS 0x04 /* R */
47#define FPGA_INITDONE 0x08 /* R */
48
49#define FPGA_TIMEOUT 100000
50
51
52/* Interrupts for the overdrive. Note that these numbers have
53 * nothing to do with the actual IRQ numbers they appear on,
54 * this is all programmable. This is simply the position in the
55 * INT_CT register.
56 */
57
58#define OVERDRIVE_PCI_INTA 0
59#define OVERDRIVE_PCI_INTB 1
60#define OVERDRIVE_PCI_INTC 2
61#define OVERDRIVE_PCI_INTD 3
62#define OVERDRIVE_GALILEO_INT 4
63#define OVERDRIVE_GALILEO_LOCAL_INT 5
64#define OVERDRIVE_AUDIO_INT 6
65#define OVERDRIVE_KEYBOARD_INT 7
66
67/* Which Linux IRQ should we assign to each interrupt source? */
68#define OVERDRIVE_PCI_IRQ1 2
69#ifdef CONFIG_HACKED_NE2K
70#define OVERDRIVE_PCI_IRQ2 7
71#else
72#define OVERDRIVE_PCI_IRQ2 2
73#undef OVERDRIVE_PCI_INTB
74#define OVERDRIVE_PCI_INTB OVERDRIVE_PCI_INTA
75
76#endif
77
78/* Put the ESS solo audio chip on IRQ 4 */
79#define OVERDRIVE_ESS_IRQ 4
80
81/* Where the memory behind the PCI bus appears */
82#define PCI_DRAM_BASE 0xb7000000
83#define PCI_DRAM_SIZE (16*1024*1024)
84#define PCI_DRAM_FINISH (PCI_DRAM_BASE+PCI_DRAM_SIZE-1)
85
86/* Where the IO region appears in the memory */
87#define PCI_GTIO_BASE 0xb8000000
88
89#endif
diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h
new file mode 100644
index 000000000000..4c6d129e7d91
--- /dev/null
+++ b/include/asm-sh/page.h
@@ -0,0 +1,144 @@
1#ifndef __ASM_SH_PAGE_H
2#define __ASM_SH_PAGE_H
3
4/*
5 * Copyright (C) 1999 Niibe Yutaka
6 */
7
8/*
9 [ P0/U0 (virtual) ] 0x00000000 <------ User space
10 [ P1 (fixed) cached ] 0x80000000 <------ Kernel space
11 [ P2 (fixed) non-cachable] 0xA0000000 <------ Physical access
12 [ P3 (virtual) cached] 0xC0000000 <------ vmalloced area
13 [ P4 control ] 0xE0000000
14 */
15
16#include <linux/config.h>
17
18/* PAGE_SHIFT determines the page size */
19#define PAGE_SHIFT 12
20#define PAGE_SIZE (1UL << PAGE_SHIFT)
21#define PAGE_MASK (~(PAGE_SIZE-1))
22#define PTE_MASK PAGE_MASK
23
24#if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
25#define HPAGE_SHIFT 16
26#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
27#define HPAGE_SHIFT 20
28#endif
29
30#ifdef CONFIG_HUGETLB_PAGE
31#define HPAGE_SIZE (1UL << HPAGE_SHIFT)
32#define HPAGE_MASK (~(HPAGE_SIZE-1))
33#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT-PAGE_SHIFT)
34#endif
35
36#ifdef __KERNEL__
37#ifndef __ASSEMBLY__
38
39extern void (*clear_page)(void *to);
40extern void (*copy_page)(void *to, void *from);
41
42extern void clear_page_slow(void *to);
43extern void copy_page_slow(void *to, void *from);
44
45#if defined(CONFIG_SH7705_CACHE_32KB) && defined(CONFIG_MMU)
46struct page;
47extern void clear_user_page(void *to, unsigned long address, struct page *pg);
48extern void copy_user_page(void *to, void *from, unsigned long address, struct page *pg);
49extern void __clear_user_page(void *to, void *orig_to);
50extern void __copy_user_page(void *to, void *from, void *orig_to);
51#elif defined(CONFIG_CPU_SH2) || defined(CONFIG_CPU_SH3) || !defined(CONFIG_MMU)
52#define clear_user_page(page, vaddr, pg) clear_page(page)
53#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
54#elif defined(CONFIG_CPU_SH4)
55struct page;
56extern void clear_user_page(void *to, unsigned long address, struct page *pg);
57extern void copy_user_page(void *to, void *from, unsigned long address, struct page *pg);
58extern void __clear_user_page(void *to, void *orig_to);
59extern void __copy_user_page(void *to, void *from, void *orig_to);
60#endif
61
62/*
63 * These are used to make use of C type-checking..
64 */
65typedef struct { unsigned long pte; } pte_t;
66typedef struct { unsigned long pmd; } pmd_t;
67typedef struct { unsigned long pgd; } pgd_t;
68typedef struct { unsigned long pgprot; } pgprot_t;
69
70#define pte_val(x) ((x).pte)
71#define pmd_val(x) ((x).pmd)
72#define pgd_val(x) ((x).pgd)
73#define pgprot_val(x) ((x).pgprot)
74
75#define __pte(x) ((pte_t) { (x) } )
76#define __pmd(x) ((pmd_t) { (x) } )
77#define __pgd(x) ((pgd_t) { (x) } )
78#define __pgprot(x) ((pgprot_t) { (x) } )
79
80#endif /* !__ASSEMBLY__ */
81
82/* to align the pointer to the (next) page boundary */
83#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK)
84
85/*
86 * IF YOU CHANGE THIS, PLEASE ALSO CHANGE
87 *
88 * arch/sh/kernel/vmlinux.lds.S
89 *
90 * which has the same constant encoded..
91 */
92
93#define __MEMORY_START CONFIG_MEMORY_START
94#define __MEMORY_SIZE CONFIG_MEMORY_SIZE
95#ifdef CONFIG_DISCONTIGMEM
96/* Just for HP690, for now.. */
97#define __MEMORY_START_2ND (__MEMORY_START+0x02000000)
98#define __MEMORY_SIZE_2ND 0x001000000 /* 16MB */
99#endif
100
101#define PAGE_OFFSET (0x80000000UL)
102#define __pa(x) ((unsigned long)(x)-PAGE_OFFSET)
103#define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET))
104
105#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)
106
107#ifndef CONFIG_DISCONTIGMEM
108#define phys_to_page(phys) (mem_map + (((phys)-__MEMORY_START) >> PAGE_SHIFT))
109#define page_to_phys(page) (((page - mem_map) << PAGE_SHIFT) + __MEMORY_START)
110#endif
111
112/* PFN start number, because of __MEMORY_START */
113#define PFN_START (__MEMORY_START >> PAGE_SHIFT)
114
115#define pfn_to_page(pfn) (mem_map + (pfn) - PFN_START)
116#define page_to_pfn(page) ((unsigned long)((page) - mem_map) + PFN_START)
117#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
118#define pfn_valid(pfn) (((pfn) - PFN_START) < max_mapnr)
119#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
120
121#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
122 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
123
124#ifndef __ASSEMBLY__
125
126/* Pure 2^n version of get_order */
127static __inline__ int get_order(unsigned long size)
128{
129 int order;
130
131 size = (size-1) >> (PAGE_SHIFT-1);
132 order = -1;
133 do {
134 size >>= 1;
135 order++;
136 } while (size);
137 return order;
138}
139
140#endif
141
142#endif /* __KERNEL__ */
143
144#endif /* __ASM_SH_PAGE_H */
diff --git a/include/asm-sh/param.h b/include/asm-sh/param.h
new file mode 100644
index 000000000000..ce13064fec21
--- /dev/null
+++ b/include/asm-sh/param.h
@@ -0,0 +1,26 @@
1#ifndef __ASM_SH_PARAM_H
2#define __ASM_SH_PARAM_H
3
4#ifdef __KERNEL__
5# ifdef CONFIG_SH_WDT
6# define HZ 1000 /* Needed for high-res WOVF */
7# else
8# define HZ 100
9# endif
10# define USER_HZ 100 /* User interfaces are in "ticks" */
11# define CLOCKS_PER_SEC (USER_HZ) /* frequency at which times() counts */
12#endif
13
14#ifndef HZ
15#define HZ 100
16#endif
17
18#define EXEC_PAGESIZE 4096
19
20#ifndef NOGROUP
21#define NOGROUP (-1)
22#endif
23
24#define MAXHOSTNAMELEN 64 /* max length of hostname */
25
26#endif /* __ASM_SH_PARAM_H */
diff --git a/include/asm-sh/pci.h b/include/asm-sh/pci.h
new file mode 100644
index 000000000000..9c3b63d0105e
--- /dev/null
+++ b/include/asm-sh/pci.h
@@ -0,0 +1,120 @@
1#ifndef __ASM_SH_PCI_H
2#define __ASM_SH_PCI_H
3
4#ifdef __KERNEL__
5
6#include <linux/dma-mapping.h>
7
8/* Can be used to override the logic in pci_scan_bus for skipping
9 already-configured bus numbers - to be used for buggy BIOSes
10 or architectures with incomplete PCI setup by the loader */
11
12#define pcibios_assign_all_busses() 1
13#define pcibios_scan_all_fns(a, b) 0
14
15/*
16 * A board can define one or more PCI channels that represent built-in (or
17 * external) PCI controllers.
18 */
19struct pci_channel {
20 struct pci_ops *pci_ops;
21 struct resource *io_resource;
22 struct resource *mem_resource;
23 int first_devfn;
24 int last_devfn;
25};
26
27/*
28 * Each board initializes this array and terminates it with a NULL entry.
29 */
30extern struct pci_channel board_pci_channels[];
31
32#define PCIBIOS_MIN_IO board_pci_channels->io_resource->start
33#define PCIBIOS_MIN_MEM board_pci_channels->mem_resource->start
34
35struct pci_dev;
36
37extern void pcibios_set_master(struct pci_dev *dev);
38
39static inline void pcibios_penalize_isa_irq(int irq)
40{
41 /* We don't do dynamic PCI IRQ allocation */
42}
43
44/* Dynamic DMA mapping stuff.
45 * SuperH has everything mapped statically like x86.
46 */
47
48/* The PCI address space does equal the physical memory
49 * address space. The networking and block device layers use
50 * this boolean for bounce buffer decisions.
51 */
52#define PCI_DMA_BUS_IS_PHYS (1)
53
54#include <linux/types.h>
55#include <linux/slab.h>
56#include <asm/scatterlist.h>
57#include <linux/string.h>
58#include <asm/io.h>
59
60/* pci_unmap_{single,page} being a nop depends upon the
61 * configuration.
62 */
63#ifdef CONFIG_SH_PCIDMA_NONCOHERENT
64#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
65 dma_addr_t ADDR_NAME;
66#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
67 __u32 LEN_NAME;
68#define pci_unmap_addr(PTR, ADDR_NAME) \
69 ((PTR)->ADDR_NAME)
70#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
71 (((PTR)->ADDR_NAME) = (VAL))
72#define pci_unmap_len(PTR, LEN_NAME) \
73 ((PTR)->LEN_NAME)
74#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
75 (((PTR)->LEN_NAME) = (VAL))
76#else
77#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
78#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
79#define pci_unmap_addr(PTR, ADDR_NAME) (0)
80#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
81#define pci_unmap_len(PTR, LEN_NAME) (0)
82#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
83#endif
84
85/* Not supporting more than 32-bit PCI bus addresses now, but
86 * must satisfy references to this function. Change if needed.
87 */
88#define pci_dac_dma_supported(pci_dev, mask) (0)
89
90/* These macros should be used after a pci_map_sg call has been done
91 * to get bus addresses of each of the SG entries and their lengths.
92 * You should only work with the number of sg entries pci_map_sg
93 * returns, or alternatively stop on the first sg_dma_len(sg) which
94 * is 0.
95 */
96#define sg_dma_address(sg) (virt_to_bus((sg)->dma_address))
97#define sg_dma_len(sg) ((sg)->length)
98
99/* Board-specific fixup routines. */
100extern void pcibios_fixup(void);
101extern void pcibios_fixup_irqs(void);
102
103#ifdef CONFIG_PCI_AUTO
104extern int pciauto_assign_resources(int busno, struct pci_channel *hose);
105#endif
106
107static inline void pcibios_add_platform_entries(struct pci_dev *dev)
108{
109}
110
111#endif /* __KERNEL__ */
112
113/* generic pci stuff */
114#include <asm-generic/pci.h>
115
116/* generic DMA-mapping stuff */
117#include <asm-generic/pci-dma-compat.h>
118
119#endif /* __ASM_SH_PCI_H */
120
diff --git a/include/asm-sh/percpu.h b/include/asm-sh/percpu.h
new file mode 100644
index 000000000000..4db4b39a4399
--- /dev/null
+++ b/include/asm-sh/percpu.h
@@ -0,0 +1,6 @@
1#ifndef __ARCH_SH_PERCPU
2#define __ARCH_SH_PERCPU
3
4#include <asm-generic/percpu.h>
5
6#endif /* __ARCH_SH_PERCPU */
diff --git a/include/asm-sh/pgalloc.h b/include/asm-sh/pgalloc.h
new file mode 100644
index 000000000000..f4f233f7a4f5
--- /dev/null
+++ b/include/asm-sh/pgalloc.h
@@ -0,0 +1,88 @@
1#ifndef __ASM_SH_PGALLOC_H
2#define __ASM_SH_PGALLOC_H
3
4#include <linux/threads.h>
5#include <linux/slab.h>
6#include <linux/mm.h>
7
8#define pgd_quicklist ((unsigned long *)0)
9#define pmd_quicklist ((unsigned long *)0)
10#define pte_quicklist ((unsigned long *)0)
11#define pgtable_cache_size 0L
12
13#define pmd_populate_kernel(mm, pmd, pte) \
14 set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte)))
15
16static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
17 struct page *pte)
18{
19 set_pmd(pmd, __pmd(_PAGE_TABLE + page_to_phys(pte)));
20}
21
22/*
23 * Allocate and free page tables.
24 */
25static inline pgd_t *pgd_alloc(struct mm_struct *mm)
26{
27 unsigned int pgd_size = (USER_PTRS_PER_PGD * sizeof(pgd_t));
28 pgd_t *pgd = (pgd_t *)kmalloc(pgd_size, GFP_KERNEL);
29
30 if (pgd)
31 memset(pgd, 0, pgd_size);
32
33 return pgd;
34}
35
36static inline void pgd_free(pgd_t *pgd)
37{
38 kfree(pgd);
39}
40
41static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
42 unsigned long address)
43{
44 pte_t *pte;
45
46 pte = (pte_t *) __get_free_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO);
47
48 return pte;
49}
50
51static inline struct page *pte_alloc_one(struct mm_struct *mm,
52 unsigned long address)
53{
54 struct page *pte;
55
56 pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0);
57
58 return pte;
59}
60
61static inline void pte_free_kernel(pte_t *pte)
62{
63 free_page((unsigned long)pte);
64}
65
66static inline void pte_free(struct page *pte)
67{
68 __free_page(pte);
69}
70
71#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte))
72
73/*
74 * allocating and freeing a pmd is trivial: the 1-entry pmd is
75 * inside the pgd, so has no extra memory associated with it.
76 */
77
78#define pmd_alloc_one(mm, addr) ({ BUG(); ((pmd_t *)2); })
79#define pmd_free(x) do { } while (0)
80#define __pmd_free_tlb(tlb,x) do { } while (0)
81#define pgd_populate(mm, pmd, pte) BUG()
82#define check_pgt_cache() do { } while (0)
83
84#ifdef CONFIG_CPU_SH4
85#define PG_mapped PG_arch_1
86#endif
87
88#endif /* __ASM_SH_PGALLOC_H */
diff --git a/include/asm-sh/pgtable-2level.h b/include/asm-sh/pgtable-2level.h
new file mode 100644
index 000000000000..b0528aa3cb1f
--- /dev/null
+++ b/include/asm-sh/pgtable-2level.h
@@ -0,0 +1,67 @@
1#ifndef __ASM_SH_PGTABLE_2LEVEL_H
2#define __ASM_SH_PGTABLE_2LEVEL_H
3
4/*
5 * traditional two-level paging structure:
6 */
7
8#define PGDIR_SHIFT 22
9#define PTRS_PER_PGD 1024
10
11/*
12 * this is two-level, so we don't really have any
13 * PMD directory physically.
14 */
15#define PMD_SHIFT 22
16#define PTRS_PER_PMD 1
17
18#define PTRS_PER_PTE 1024
19
20#ifndef __ASSEMBLY__
21#define pte_ERROR(e) \
22 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
23#define pmd_ERROR(e) \
24 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
25#define pgd_ERROR(e) \
26 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
27
28/*
29 * The "pgd_xxx()" functions here are trivial for a folded two-level
30 * setup: the pgd is never bad, and a pmd always exists (as it's folded
31 * into the pgd entry)
32 */
33static inline int pgd_none(pgd_t pgd) { return 0; }
34static inline int pgd_bad(pgd_t pgd) { return 0; }
35static inline int pgd_present(pgd_t pgd) { return 1; }
36static inline void pgd_clear (pgd_t * pgdp) { }
37
38/*
39 * Certain architectures need to do special things when PTEs
40 * within a page table are directly modified. Thus, the following
41 * hook is made available.
42 */
43#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
44#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
45
46/*
47 * (pmds are folded into pgds so this doesn't get actually called,
48 * but the define is needed for a generic inline function.)
49 */
50#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
51#define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval)
52
53#define pgd_page(pgd) \
54((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
55
56static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
57{
58 return (pmd_t *) dir;
59}
60
61#define pte_pfn(x) ((unsigned long)(((x).pte >> PAGE_SHIFT)))
62#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
63#define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
64
65#endif /* !__ASSEMBLY__ */
66
67#endif /* __ASM_SH_PGTABLE_2LEVEL_H */
diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h
new file mode 100644
index 000000000000..8a9689d5366f
--- /dev/null
+++ b/include/asm-sh/pgtable.h
@@ -0,0 +1,306 @@
1#ifndef __ASM_SH_PGTABLE_H
2#define __ASM_SH_PGTABLE_H
3
4#include <asm-generic/4level-fixup.h>
5
6/*
7 * Copyright (C) 1999 Niibe Yutaka
8 * Copyright (C) 2002, 2003, 2004 Paul Mundt
9 */
10
11#include <linux/config.h>
12#include <asm/pgtable-2level.h>
13
14/*
15 * This file contains the functions and defines necessary to modify and use
16 * the SuperH page table tree.
17 */
18#ifndef __ASSEMBLY__
19#include <asm/processor.h>
20#include <asm/addrspace.h>
21#include <asm/fixmap.h>
22#include <linux/threads.h>
23
24extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
25extern void paging_init(void);
26
27/*
28 * Basically we have the same two-level (which is the logical three level
29 * Linux page table layout folded) page tables as the i386.
30 */
31
32/*
33 * ZERO_PAGE is a global shared page that is always zero: used
34 * for zero-mapped memory areas etc..
35 */
36extern unsigned long empty_zero_page[1024];
37#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
38
39#endif /* !__ASSEMBLY__ */
40
41#define PMD_SIZE (1UL << PMD_SHIFT)
42#define PMD_MASK (~(PMD_SIZE-1))
43#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
44#define PGDIR_MASK (~(PGDIR_SIZE-1))
45
46#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
47#define FIRST_USER_PGD_NR 0
48
49#define PTE_PHYS_MASK 0x1ffff000
50
51#ifndef __ASSEMBLY__
52/*
53 * First 1MB map is used by fixed purpose.
54 * Currently only 4-enty (16kB) is used (see arch/sh/mm/cache.c)
55 */
56#define VMALLOC_START (P3SEG+0x00100000)
57#define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
58
59#define _PAGE_WT 0x001 /* WT-bit on SH-4, 0 on SH-3 */
60#define _PAGE_HW_SHARED 0x002 /* SH-bit : page is shared among processes */
61#define _PAGE_DIRTY 0x004 /* D-bit : page changed */
62#define _PAGE_CACHABLE 0x008 /* C-bit : cachable */
63#define _PAGE_SZ0 0x010 /* SZ0-bit : Size of page */
64#define _PAGE_RW 0x020 /* PR0-bit : write access allowed */
65#define _PAGE_USER 0x040 /* PR1-bit : user space access allowed */
66#define _PAGE_SZ1 0x080 /* SZ1-bit : Size of page (on SH-4) */
67#define _PAGE_PRESENT 0x100 /* V-bit : page is valid */
68#define _PAGE_PROTNONE 0x200 /* software: if not present */
69#define _PAGE_ACCESSED 0x400 /* software: page referenced */
70#define _PAGE_U0_SHARED 0x800 /* software: page is shared in user space */
71
72#define _PAGE_FILE _PAGE_WT /* software: pagecache or swap? */
73
74/* software: moves to PTEA.TC (Timing Control) */
75#define _PAGE_PCC_AREA5 0x00000000 /* use BSC registers for area5 */
76#define _PAGE_PCC_AREA6 0x80000000 /* use BSC registers for area6 */
77
78/* software: moves to PTEA.SA[2:0] (Space Attributes) */
79#define _PAGE_PCC_IODYN 0x00000001 /* IO space, dynamically sized bus */
80#define _PAGE_PCC_IO8 0x20000000 /* IO space, 8 bit bus */
81#define _PAGE_PCC_IO16 0x20000001 /* IO space, 16 bit bus */
82#define _PAGE_PCC_COM8 0x40000000 /* Common Memory space, 8 bit bus */
83#define _PAGE_PCC_COM16 0x40000001 /* Common Memory space, 16 bit bus */
84#define _PAGE_PCC_ATR8 0x60000000 /* Attribute Memory space, 8 bit bus */
85#define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */
86
87
88/* Mask which drop software flags
89 * We also drop WT bit since it is used for _PAGE_FILE
90 * bit in this implementation.
91 */
92#define _PAGE_CLEAR_FLAGS (_PAGE_WT | _PAGE_PROTNONE | _PAGE_ACCESSED | _PAGE_U0_SHARED)
93
94#if defined(CONFIG_CPU_SH3)
95/*
96 * MMU on SH-3 has bug on SH-bit: We can't use it if MMUCR.IX=1.
97 * Work around: Just drop SH-bit.
98 */
99#define _PAGE_FLAGS_HARDWARE_MASK (0x1fffffff & ~(_PAGE_CLEAR_FLAGS | _PAGE_HW_SHARED))
100#else
101#define _PAGE_FLAGS_HARDWARE_MASK (0x1fffffff & ~(_PAGE_CLEAR_FLAGS))
102#endif
103
104/* Hardware flags: SZ0=1 (4k-byte) */
105#define _PAGE_FLAGS_HARD _PAGE_SZ0
106
107#if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
108#define _PAGE_SZHUGE (_PAGE_SZ1)
109#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
110#define _PAGE_SZHUGE (_PAGE_SZ0 | _PAGE_SZ1)
111#endif
112
113#define _PAGE_SHARED _PAGE_U0_SHARED
114
115#define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
116#define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
117#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | _PAGE_DIRTY | _PAGE_SHARED)
118
119#ifdef CONFIG_MMU
120#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE |_PAGE_ACCESSED | _PAGE_FLAGS_HARD)
121#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_CACHABLE |_PAGE_ACCESSED | _PAGE_SHARED | _PAGE_FLAGS_HARD)
122#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
123#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
124#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_CACHABLE | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
125#define PAGE_KERNEL_NOCACHE \
126 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
127#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
128#define PAGE_KERNEL_PCC(slot, type) \
129 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_FLAGS_HARD | (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | (type))
130#else /* no mmu */
131#define PAGE_NONE __pgprot(0)
132#define PAGE_SHARED __pgprot(0)
133#define PAGE_COPY __pgprot(0)
134#define PAGE_READONLY __pgprot(0)
135#define PAGE_KERNEL __pgprot(0)
136#define PAGE_KERNEL_NOCACHE __pgprot(0)
137#define PAGE_KERNEL_RO __pgprot(0)
138#define PAGE_KERNEL_PCC __pgprot(0)
139#endif
140
141/*
142 * As i386 and MIPS, SuperH can't do page protection for execute, and
143 * considers that the same as a read. Also, write permissions imply
144 * read permissions. This is the closest we can get..
145 */
146
147#define __P000 PAGE_NONE
148#define __P001 PAGE_READONLY
149#define __P010 PAGE_COPY
150#define __P011 PAGE_COPY
151#define __P100 PAGE_READONLY
152#define __P101 PAGE_READONLY
153#define __P110 PAGE_COPY
154#define __P111 PAGE_COPY
155
156#define __S000 PAGE_NONE
157#define __S001 PAGE_READONLY
158#define __S010 PAGE_SHARED
159#define __S011 PAGE_SHARED
160#define __S100 PAGE_READONLY
161#define __S101 PAGE_READONLY
162#define __S110 PAGE_SHARED
163#define __S111 PAGE_SHARED
164
165#define pte_none(x) (!pte_val(x))
166#define pte_present(x) (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE))
167#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
168
169#define pmd_none(x) (!pmd_val(x))
170#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
171#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
172#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
173
174#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
175#define pte_page(x) phys_to_page(pte_val(x)&PTE_PHYS_MASK)
176
177/*
178 * The following only work if pte_present() is true.
179 * Undefined behaviour if not..
180 */
181static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
182static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
183static inline int pte_dirty(pte_t pte){ return pte_val(pte) & _PAGE_DIRTY; }
184static inline int pte_young(pte_t pte){ return pte_val(pte) & _PAGE_ACCESSED; }
185static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
186static inline int pte_write(pte_t pte){ return pte_val(pte) & _PAGE_RW; }
187static inline int pte_not_present(pte_t pte){ return !(pte_val(pte) & _PAGE_PRESENT); }
188
189static inline pte_t pte_rdprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; }
190static inline pte_t pte_exprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; }
191static inline pte_t pte_mkclean(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; }
192static inline pte_t pte_mkold(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_ACCESSED)); return pte; }
193static inline pte_t pte_wrprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_RW)); return pte; }
194static inline pte_t pte_mkread(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_USER)); return pte; }
195static inline pte_t pte_mkexec(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_USER)); return pte; }
196static inline pte_t pte_mkdirty(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; }
197static inline pte_t pte_mkyoung(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; }
198static inline pte_t pte_mkwrite(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_RW)); return pte; }
199
200/*
201 * Macro and implementation to make a page protection as uncachable.
202 */
203#define pgprot_noncached pgprot_noncached
204
205static inline pgprot_t pgprot_noncached(pgprot_t _prot)
206{
207 unsigned long prot = pgprot_val(_prot);
208
209 prot &= ~_PAGE_CACHABLE;
210 return __pgprot(prot);
211}
212
213#define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
214
215/*
216 * Conversion functions: convert a page and protection to a page entry,
217 * and a page entry and page directory to the page they refer to.
218 *
219 * extern pte_t mk_pte(struct page *page, pgprot_t pgprot)
220 */
221#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
222
223static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
224{ set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))); return pte; }
225
226#define page_pte(page) page_pte_prot(page, __pgprot(0))
227
228#define pmd_page_kernel(pmd) \
229((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
230
231#define pmd_page(pmd) \
232 (phys_to_page(pmd_val(pmd)))
233
234/* to find an entry in a page-table-directory. */
235#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
236#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
237
238/* to find an entry in a kernel page-table-directory */
239#define pgd_offset_k(address) pgd_offset(&init_mm, address)
240
241/* Find an entry in the third-level page table.. */
242#define pte_index(address) \
243 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
244#define pte_offset_kernel(dir, address) \
245 ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(address))
246#define pte_offset_map(dir, address) pte_offset_kernel(dir, address)
247#define pte_offset_map_nested(dir, address) pte_offset_kernel(dir, address)
248#define pte_unmap(pte) do { } while (0)
249#define pte_unmap_nested(pte) do { } while (0)
250
251struct vm_area_struct;
252extern void update_mmu_cache(struct vm_area_struct * vma,
253 unsigned long address, pte_t pte);
254
255/* Encode and de-code a swap entry */
256/*
257 * NOTE: We should set ZEROs at the position of _PAGE_PRESENT
258 * and _PAGE_PROTNONE bits
259 */
260#define __swp_type(x) ((x).val & 0xff)
261#define __swp_offset(x) ((x).val >> 10)
262#define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 10) })
263#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 1 })
264#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 1 })
265
266/*
267 * Encode and decode a nonlinear file mapping entry
268 */
269#define PTE_FILE_MAX_BITS 29
270#define pte_to_pgoff(pte) (pte_val(pte) >> 1)
271#define pgoff_to_pte(off) ((pte_t) { ((off) << 1) | _PAGE_FILE })
272
273typedef pte_t *pte_addr_t;
274
275#endif /* !__ASSEMBLY__ */
276
277#define kern_addr_valid(addr) (1)
278
279#define io_remap_page_range(vma, vaddr, paddr, size, prot) \
280 remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)
281
282#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
283 remap_pfn_range(vma, vaddr, pfn, size, prot)
284
285#define MK_IOSPACE_PFN(space, pfn) (pfn)
286#define GET_IOSPACE(pfn) 0
287#define GET_PFN(pfn) (pfn)
288
289/*
290 * No page table caches to initialise
291 */
292#define pgtable_cache_init() do { } while (0)
293
294#ifndef CONFIG_MMU
295extern unsigned int kobjsize(const void *objp);
296#endif /* !CONFIG_MMU */
297
298#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
299#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
300extern pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
301#endif
302
303#include <asm-generic/pgtable.h>
304
305#endif /* __ASM_SH_PAGE_H */
306
diff --git a/include/asm-sh/poll.h b/include/asm-sh/poll.h
new file mode 100644
index 000000000000..52f95b9188dc
--- /dev/null
+++ b/include/asm-sh/poll.h
@@ -0,0 +1,26 @@
1#ifndef __ASM_SH_POLL_H
2#define __ASM_SH_POLL_H
3
4/* These are specified by iBCS2 */
5#define POLLIN 0x0001
6#define POLLPRI 0x0002
7#define POLLOUT 0x0004
8#define POLLERR 0x0008
9#define POLLHUP 0x0010
10#define POLLNVAL 0x0020
11
12/* The rest seem to be more-or-less nonstandard. Check them! */
13#define POLLRDNORM 0x0040
14#define POLLRDBAND 0x0080
15#define POLLWRNORM 0x0100
16#define POLLWRBAND 0x0200
17#define POLLMSG 0x0400
18#define POLLREMOVE 0x1000
19
20struct pollfd {
21 int fd;
22 short events;
23 short revents;
24};
25
26#endif /* __ASM_SH_POLL_H */
diff --git a/include/asm-sh/posix_types.h b/include/asm-sh/posix_types.h
new file mode 100644
index 000000000000..0a3d2f54ab27
--- /dev/null
+++ b/include/asm-sh/posix_types.h
@@ -0,0 +1,122 @@
1#ifndef __ASM_SH_POSIX_TYPES_H
2#define __ASM_SH_POSIX_TYPES_H
3
4/*
5 * This file is generally used by user-level software, so you need to
6 * be a little careful about namespace pollution etc. Also, we cannot
7 * assume GCC is being used.
8 */
9
10typedef unsigned long __kernel_ino_t;
11typedef unsigned short __kernel_mode_t;
12typedef unsigned short __kernel_nlink_t;
13typedef long __kernel_off_t;
14typedef int __kernel_pid_t;
15typedef unsigned short __kernel_ipc_pid_t;
16typedef unsigned short __kernel_uid_t;
17typedef unsigned short __kernel_gid_t;
18typedef unsigned int __kernel_size_t;
19typedef int __kernel_ssize_t;
20typedef int __kernel_ptrdiff_t;
21typedef long __kernel_time_t;
22typedef long __kernel_suseconds_t;
23typedef long __kernel_clock_t;
24typedef int __kernel_timer_t;
25typedef int __kernel_clockid_t;
26typedef int __kernel_daddr_t;
27typedef char * __kernel_caddr_t;
28typedef unsigned short __kernel_uid16_t;
29typedef unsigned short __kernel_gid16_t;
30typedef unsigned int __kernel_uid32_t;
31typedef unsigned int __kernel_gid32_t;
32
33typedef unsigned short __kernel_old_uid_t;
34typedef unsigned short __kernel_old_gid_t;
35typedef unsigned short __kernel_old_dev_t;
36
37#ifdef __GNUC__
38typedef long long __kernel_loff_t;
39#endif
40
41typedef struct {
42#if defined(__KERNEL__) || defined(__USE_ALL)
43 int val[2];
44#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
45 int __val[2];
46#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
47} __kernel_fsid_t;
48
49#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
50
51#undef __FD_SET
52static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
53{
54 unsigned long __tmp = __fd / __NFDBITS;
55 unsigned long __rem = __fd % __NFDBITS;
56 __fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
57}
58
59#undef __FD_CLR
60static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
61{
62 unsigned long __tmp = __fd / __NFDBITS;
63 unsigned long __rem = __fd % __NFDBITS;
64 __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
65}
66
67
68#undef __FD_ISSET
69static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
70{
71 unsigned long __tmp = __fd / __NFDBITS;
72 unsigned long __rem = __fd % __NFDBITS;
73 return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
74}
75
76/*
77 * This will unroll the loop for the normal constant case (8 ints,
78 * for a 256-bit fd_set)
79 */
80#undef __FD_ZERO
81static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
82{
83 unsigned long *__tmp = __p->fds_bits;
84 int __i;
85
86 if (__builtin_constant_p(__FDSET_LONGS)) {
87 switch (__FDSET_LONGS) {
88 case 16:
89 __tmp[ 0] = 0; __tmp[ 1] = 0;
90 __tmp[ 2] = 0; __tmp[ 3] = 0;
91 __tmp[ 4] = 0; __tmp[ 5] = 0;
92 __tmp[ 6] = 0; __tmp[ 7] = 0;
93 __tmp[ 8] = 0; __tmp[ 9] = 0;
94 __tmp[10] = 0; __tmp[11] = 0;
95 __tmp[12] = 0; __tmp[13] = 0;
96 __tmp[14] = 0; __tmp[15] = 0;
97 return;
98
99 case 8:
100 __tmp[ 0] = 0; __tmp[ 1] = 0;
101 __tmp[ 2] = 0; __tmp[ 3] = 0;
102 __tmp[ 4] = 0; __tmp[ 5] = 0;
103 __tmp[ 6] = 0; __tmp[ 7] = 0;
104 return;
105
106 case 4:
107 __tmp[ 0] = 0; __tmp[ 1] = 0;
108 __tmp[ 2] = 0; __tmp[ 3] = 0;
109 return;
110 }
111 }
112 __i = __FDSET_LONGS;
113 while (__i) {
114 __i--;
115 *__tmp = 0;
116 __tmp++;
117 }
118}
119
120#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
121
122#endif /* __ASM_SH_POSIX_TYPES_H */
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
new file mode 100644
index 000000000000..c4904797d6df
--- /dev/null
+++ b/include/asm-sh/processor.h
@@ -0,0 +1,275 @@
1/*
2 * include/asm-sh/processor.h
3 *
4 * Copyright (C) 1999, 2000 Niibe Yutaka
5 * Copyright (C) 2002, 2003 Paul Mundt
6 */
7
8#ifndef __ASM_SH_PROCESSOR_H
9#define __ASM_SH_PROCESSOR_H
10#ifdef __KERNEL__
11
12#include <asm/page.h>
13#include <asm/types.h>
14#include <asm/cache.h>
15#include <linux/threads.h>
16#include <asm/ptrace.h>
17
18/*
19 * Default implementation of macro that returns current
20 * instruction pointer ("program counter").
21 */
22#define current_text_addr() ({ void *pc; __asm__("mova 1f, %0\n1:":"=z" (pc)); pc; })
23
24/* Core Processor Version Register */
25#define CCN_PVR 0xff000030
26#define CCN_CVR 0xff000040
27#define CCN_PRR 0xff000044
28
29/*
30 * CPU type and hardware bug flags. Kept separately for each CPU.
31 *
32 * Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry
33 * in arch/sh/Kconfig, as well as an entry in arch/sh/kernel/setup.c
34 * for parsing the subtype in get_cpu_subtype().
35 */
36enum cpu_type {
37 /* SH-2 types */
38 CPU_SH7604,
39
40 /* SH-3 types */
41 CPU_SH7705, CPU_SH7707, CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
42 CPU_SH7709, CPU_SH7709A, CPU_SH7729, CPU_SH7300,
43
44 /* SH-4 types */
45 CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
46 CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501,
47 CPU_SH73180,
48
49 /* Unknown subtype */
50 CPU_SH_NONE
51};
52
53struct sh_cpuinfo {
54 enum cpu_type type;
55 char hard_math;
56 unsigned long loops_per_jiffy;
57
58 unsigned int cpu_clock, master_clock, bus_clock, module_clock;
59#ifdef CONFIG_CPU_SUBTYPE_ST40STB1
60 unsigned int memory_clock;
61#endif
62
63 struct cache_info icache;
64 struct cache_info dcache;
65
66 unsigned long flags;
67};
68
69extern struct sh_cpuinfo boot_cpu_data;
70
71#ifdef CONFIG_SMP
72extern struct sh_cpuinfo cpu_data[];
73#define current_cpu_data cpu_data[smp_processor_id()]
74#else
75#define cpu_data (&boot_cpu_data)
76#define current_cpu_data boot_cpu_data
77#endif
78
79/*
80 * User space process size: 2GB.
81 *
82 * Since SH7709 and SH7750 have "area 7", we can't use 0x7c000000--0x7fffffff
83 */
84#define TASK_SIZE 0x7c000000UL
85
86/* This decides where the kernel will search for a free chunk of vm
87 * space during mmap's.
88 */
89#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
90
91/*
92 * Bit of SR register
93 *
94 * FD-bit:
95 * When it's set, it means the processor doesn't have right to use FPU,
96 * and it results exception when the floating operation is executed.
97 *
98 * IMASK-bit:
99 * Interrupt level mask
100 */
101#define SR_FD 0x00008000
102#define SR_DSP 0x00001000
103#define SR_IMASK 0x000000f0
104
105/*
106 * FPU structure and data
107 */
108
109struct sh_fpu_hard_struct {
110 unsigned long fp_regs[16];
111 unsigned long xfp_regs[16];
112 unsigned long fpscr;
113 unsigned long fpul;
114
115 long status; /* software status information */
116};
117
118/* Dummy fpu emulator */
119struct sh_fpu_soft_struct {
120 unsigned long fp_regs[16];
121 unsigned long xfp_regs[16];
122 unsigned long fpscr;
123 unsigned long fpul;
124
125 unsigned char lookahead;
126 unsigned long entry_pc;
127};
128
129union sh_fpu_union {
130 struct sh_fpu_hard_struct hard;
131 struct sh_fpu_soft_struct soft;
132};
133
134/*
135 * Processor flags
136 */
137
138#define CPU_HAS_FPU 0x0001 /* Hardware FPU support */
139#define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */
140#define CPU_HAS_MMU_PAGE_ASSOC 0x0004 /* SH3: TLB way selection bit support */
141#define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */
142#define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */
143
144struct thread_struct {
145 unsigned long sp;
146 unsigned long pc;
147
148 unsigned long trap_no, error_code;
149 unsigned long address;
150 /* Hardware debugging registers may come here */
151 unsigned long ubc_pc;
152
153 /* floating point info */
154 union sh_fpu_union fpu;
155};
156
157/* Count of active tasks with UBC settings */
158extern int ubc_usercnt;
159
160#define INIT_THREAD { \
161 sizeof(init_stack) + (long) &init_stack, /* sp */ \
162 0, /* pc */ \
163 0, 0, \
164 0, \
165 0, \
166 {{{0,}},} /* fpu state */ \
167}
168
169/*
170 * Do necessary setup to start up a newly executed thread.
171 */
172#define start_thread(regs, new_pc, new_sp) \
173 set_fs(USER_DS); \
174 regs->pr = 0; \
175 regs->sr = SR_FD; /* User mode. */ \
176 regs->pc = new_pc; \
177 regs->regs[15] = new_sp
178
179/* Forward declaration, a strange C thing */
180struct task_struct;
181struct mm_struct;
182
183/* Free all resources held by a thread. */
184extern void release_thread(struct task_struct *);
185
186/* Prepare to copy thread state - unlazy all lazy status */
187#define prepare_to_copy(tsk) do { } while (0)
188
189/*
190 * create a kernel thread without removing it from tasklists
191 */
192extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
193
194/* Copy and release all segment info associated with a VM */
195#define copy_segments(p, mm) do { } while(0)
196#define release_segments(mm) do { } while(0)
197
198/*
199 * FPU lazy state save handling.
200 */
201
202static __inline__ void disable_fpu(void)
203{
204 unsigned long __dummy;
205
206 /* Set FD flag in SR */
207 __asm__ __volatile__("stc sr, %0\n\t"
208 "or %1, %0\n\t"
209 "ldc %0, sr"
210 : "=&r" (__dummy)
211 : "r" (SR_FD));
212}
213
214static __inline__ void enable_fpu(void)
215{
216 unsigned long __dummy;
217
218 /* Clear out FD flag in SR */
219 __asm__ __volatile__("stc sr, %0\n\t"
220 "and %1, %0\n\t"
221 "ldc %0, sr"
222 : "=&r" (__dummy)
223 : "r" (~SR_FD));
224}
225
226static __inline__ void release_fpu(struct pt_regs *regs)
227{
228 regs->sr |= SR_FD;
229}
230
231static __inline__ void grab_fpu(struct pt_regs *regs)
232{
233 regs->sr &= ~SR_FD;
234}
235
236#ifdef CONFIG_CPU_SH4
237extern void save_fpu(struct task_struct *__tsk, struct pt_regs *regs);
238#else
239#define save_fpu(tsk) do { } while (0)
240#endif
241
242#define unlazy_fpu(tsk, regs) do { \
243 if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { \
244 save_fpu(tsk, regs); \
245 } \
246} while (0)
247
248#define clear_fpu(tsk, regs) do { \
249 if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { \
250 clear_tsk_thread_flag(tsk, TIF_USEDFPU); \
251 release_fpu(regs); \
252 } \
253} while (0)
254
255/* Double presision, NANS as NANS, rounding to nearest, no exceptions */
256#define FPSCR_INIT 0x00080000
257
258#define FPSCR_CAUSE_MASK 0x0001f000 /* Cause bits */
259#define FPSCR_FLAG_MASK 0x0000007c /* Flag bits */
260
261/*
262 * Return saved PC of a blocked thread.
263 */
264#define thread_saved_pc(tsk) (tsk->thread.pc)
265
266extern unsigned long get_wchan(struct task_struct *p);
267
268#define KSTK_EIP(tsk) ((tsk)->thread.pc)
269#define KSTK_ESP(tsk) ((tsk)->thread.sp)
270
271#define cpu_sleep() __asm__ __volatile__ ("sleep" : : : "memory")
272#define cpu_relax() do { } while (0)
273
274#endif /* __KERNEL__ */
275#endif /* __ASM_SH_PROCESSOR_H */
diff --git a/include/asm-sh/ptrace.h b/include/asm-sh/ptrace.h
new file mode 100644
index 000000000000..0f75e16a7415
--- /dev/null
+++ b/include/asm-sh/ptrace.h
@@ -0,0 +1,104 @@
1#ifndef __ASM_SH_PTRACE_H
2#define __ASM_SH_PTRACE_H
3
4#include <asm/ubc.h>
5
6/*
7 * Copyright (C) 1999, 2000 Niibe Yutaka
8 *
9 */
10
11/*
12 * GCC defines register number like this:
13 * -----------------------------
14 * 0 - 15 are integer registers
15 * 17 - 22 are control/special registers
16 * 24 - 39 fp registers
17 * 40 - 47 xd registers
18 * 48 - fpscr register
19 * -----------------------------
20 *
21 * We follows above, except:
22 * 16 --- program counter (PC)
23 * 22 --- syscall #
24 * 23 --- floating point communication register
25 */
26#define REG_REG0 0
27#define REG_REG15 15
28
29#define REG_PC 16
30
31#define REG_PR 17
32#define REG_SR 18
33#define REG_GBR 19
34#define REG_MACH 20
35#define REG_MACL 21
36
37#define REG_SYSCALL 22
38
39#define REG_FPREG0 23
40#define REG_FPREG15 38
41#define REG_XFREG0 39
42#define REG_XFREG15 54
43
44#define REG_FPSCR 55
45#define REG_FPUL 56
46
47/* options set using PTRACE_SETOPTIONS */
48#define PTRACE_O_TRACESYSGOOD 0x00000001
49
50/*
51 * This struct defines the way the registers are stored on the
52 * kernel stack during a system call or other kernel entry.
53 */
54struct pt_regs {
55 unsigned long regs[16];
56 unsigned long pc;
57 unsigned long pr;
58 unsigned long sr;
59 unsigned long gbr;
60 unsigned long mach;
61 unsigned long macl;
62 long tra;
63};
64
65/*
66 * This struct defines the way the DSP registers are stored on the
67 * kernel stack during a system call or other kernel entry.
68 */
69struct pt_dspregs {
70 unsigned long a1;
71 unsigned long a0g;
72 unsigned long a1g;
73 unsigned long m0;
74 unsigned long m1;
75 unsigned long a0;
76 unsigned long x0;
77 unsigned long x1;
78 unsigned long y0;
79 unsigned long y1;
80 unsigned long dsr;
81 unsigned long rs;
82 unsigned long re;
83 unsigned long mod;
84};
85
86#define PTRACE_GETDSPREGS 55
87#define PTRACE_SETDSPREGS 56
88
89#ifdef __KERNEL__
90#define user_mode(regs) (((regs)->sr & 0x40000000)==0)
91#define instruction_pointer(regs) ((regs)->pc)
92extern void show_regs(struct pt_regs *);
93
94static inline unsigned long profile_pc(struct pt_regs *regs)
95{
96 unsigned long pc = instruction_pointer(regs);
97
98 if (pc >= 0xa0000000UL && pc < 0xc0000000UL)
99 pc -= 0x20000000;
100 return pc;
101}
102#endif
103
104#endif /* __ASM_SH_PTRACE_H */
diff --git a/include/asm-sh/resource.h b/include/asm-sh/resource.h
new file mode 100644
index 000000000000..9c2499a86ec0
--- /dev/null
+++ b/include/asm-sh/resource.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_SH_RESOURCE_H
2#define __ASM_SH_RESOURCE_H
3
4#include <asm-generic/resource.h>
5
6#endif /* __ASM_SH_RESOURCE_H */
diff --git a/include/asm-sh/rtc.h b/include/asm-sh/rtc.h
new file mode 100644
index 000000000000..cea9cdf9b925
--- /dev/null
+++ b/include/asm-sh/rtc.h
@@ -0,0 +1,29 @@
1#ifndef _ASM_RTC_H
2#define _ASM_RTC_H
3#ifdef __KERNEL__
4
5#include <asm/machvec.h>
6#include <asm/cpu/rtc.h>
7
8extern void sh_rtc_gettimeofday(struct timespec *ts);
9extern int sh_rtc_settimeofday(const time_t secs);
10extern void (*board_time_init)(void);
11extern void (*rtc_get_time)(struct timespec *);
12extern int (*rtc_set_time)(const time_t);
13
14/* RCR1 Bits */
15#define RCR1_CF 0x80 /* Carry Flag */
16#define RCR1_CIE 0x10 /* Carry Interrupt Enable */
17#define RCR1_AIE 0x08 /* Alarm Interrupt Enable */
18#define RCR1_AF 0x01 /* Alarm Flag */
19
20/* RCR2 Bits */
21#define RCR2_PEF 0x80 /* PEriodic interrupt Flag */
22#define RCR2_PESMASK 0x70 /* Periodic interrupt Set */
23#define RCR2_RTCEN 0x08 /* ENable RTC */
24#define RCR2_ADJ 0x04 /* ADJustment (30-second) */
25#define RCR2_RESET 0x02 /* Reset bit */
26#define RCR2_START 0x01 /* Start bit */
27
28#endif /* __KERNEL__ */
29#endif /* _ASM_RTC_H */
diff --git a/include/asm-sh/rts7751r2d/ide.h b/include/asm-sh/rts7751r2d/ide.h
new file mode 100644
index 000000000000..416f96b407cb
--- /dev/null
+++ b/include/asm-sh/rts7751r2d/ide.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_SH_RTS7751R2D_IDE_H
2#define __ASM_SH_RTS7751R2D_IDE_H
3
4/* Nothing to see here.. */
5#include <asm/rts7751r2d/rts7751r2d.h>
6
7#endif /* __ASM_SH_RTS7751R2D_IDE_H */
8
diff --git a/include/asm-sh/rts7751r2d/io.h b/include/asm-sh/rts7751r2d/io.h
new file mode 100644
index 000000000000..241094020567
--- /dev/null
+++ b/include/asm-sh/rts7751r2d/io.h
@@ -0,0 +1,37 @@
1/*
2 * include/asm-sh/io_rts7751r2d.h
3 *
4 * Modified version of io_se.h for the rts7751r2d-specific functions.
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * IO functions for an Renesas Technology sales RTS7751R2D
10 */
11
12#ifndef _ASM_SH_IO_RTS7751R2D_H
13#define _ASM_SH_IO_RTS7751R2D_H
14
15extern unsigned char rts7751r2d_inb(unsigned long port);
16extern unsigned short rts7751r2d_inw(unsigned long port);
17extern unsigned int rts7751r2d_inl(unsigned long port);
18
19extern void rts7751r2d_outb(unsigned char value, unsigned long port);
20extern void rts7751r2d_outw(unsigned short value, unsigned long port);
21extern void rts7751r2d_outl(unsigned int value, unsigned long port);
22
23extern unsigned char rts7751r2d_inb_p(unsigned long port);
24extern void rts7751r2d_outb_p(unsigned char value, unsigned long port);
25
26extern void rts7751r2d_insb(unsigned long port, void *addr, unsigned long count);
27extern void rts7751r2d_insw(unsigned long port, void *addr, unsigned long count);
28extern void rts7751r2d_insl(unsigned long port, void *addr, unsigned long count);
29extern void rts7751r2d_outsb(unsigned long port, const void *addr, unsigned long count);
30extern void rts7751r2d_outsw(unsigned long port, const void *addr, unsigned long count);
31extern void rts7751r2d_outsl(unsigned long port, const void *addr, unsigned long count);
32
33extern void *rts7751r2d_ioremap(unsigned long offset, unsigned long size);
34
35extern unsigned long rts7751r2d_isa_port2addr(unsigned long offset);
36
37#endif /* _ASM_SH_IO_RTS7751R2D_H */
diff --git a/include/asm-sh/rts7751r2d/rts7751r2d.h b/include/asm-sh/rts7751r2d/rts7751r2d.h
new file mode 100644
index 000000000000..4e09ba597e9a
--- /dev/null
+++ b/include/asm-sh/rts7751r2d/rts7751r2d.h
@@ -0,0 +1,73 @@
1#ifndef __ASM_SH_RENESAS_RTS7751R2D_H
2#define __ASM_SH_RENESAS_RTS7751R2D_H
3
4/*
5 * linux/include/asm-sh/renesas_rts7751r2d.h
6 *
7 * Copyright (C) 2000 Atom Create Engineering Co., Ltd.
8 *
9 * Renesas Technology Sales RTS7751R2D support
10 */
11
12/* Box specific addresses. */
13
14#define PA_BCR 0xa4000000 /* FPGA */
15#define PA_IRLMON 0xa4000002 /* Interrupt Status control */
16#define PA_CFCTL 0xa4000004 /* CF Timing control */
17#define PA_CFPOW 0xa4000006 /* CF Power control */
18#define PA_DISPCTL 0xa4000008 /* Display Timing control */
19#define PA_SDMPOW 0xa400000a /* SD Power control */
20#define PA_RTCCE 0xa400000c /* RTC(9701) Enable control */
21#define PA_PCICD 0xa400000e /* PCI Extention detect control */
22#define PA_VOYAGERRTS 0xa4000020 /* VOYAGER Reset control */
23#if defined(CONFIG_RTS7751R2D_REV11)
24#define PA_AXRST 0xa4000022 /* AX_LAN Reset control */
25#define PA_CFRST 0xa4000024 /* CF Reset control */
26#define PA_ADMRTS 0xa4000026 /* SD Reset control */
27#define PA_EXTRST 0xa4000028 /* Extention Reset control */
28#define PA_CFCDINTCLR 0xa400002a /* CF Insert Interrupt clear */
29#else
30#define PA_CFRST 0xa4000022 /* CF Reset control */
31#define PA_ADMRTS 0xa4000024 /* SD Reset control */
32#define PA_EXTRST 0xa4000026 /* Extention Reset control */
33#define PA_CFCDINTCLR 0xa4000028 /* CF Insert Interrupt clear */
34#define PA_KEYCTLCLR 0xa400002a /* Key Interrupt clear */
35#endif
36#define PA_POWOFF 0xa4000030 /* Board Power OFF control */
37#define PA_VERREG 0xa4000032 /* FPGA Version Register */
38#define PA_INPORT 0xa4000034 /* KEY Input Port control */
39#define PA_OUTPORT 0xa4000036 /* LED control */
40#define PA_DMPORT 0xa4000038 /* DM270 Output Port control */
41
42#define PA_AX88796L 0xaa000400 /* AX88796L Area */
43#define PA_VOYAGER 0xab000000 /* VOYAGER GX Area */
44#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
45#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
46#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
47#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
48
49#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
50
51#if defined(CONFIG_RTS7751R2D_REV11)
52#define IRQ_PCIETH 0 /* PCI Ethernet IRQ */
53#define IRQ_CFCARD 1 /* CF Card IRQ */
54#define IRQ_CFINST 2 /* CF Card Insert IRQ */
55#define IRQ_PCMCIA 3 /* PCMCIA IRQ */
56#define IRQ_VOYAGER 4 /* VOYAGER IRQ */
57#define IRQ_ONETH 5 /* On board Ethernet IRQ */
58#else
59#define IRQ_KEYIN 0 /* Key Input IRQ */
60#define IRQ_PCIETH 1 /* PCI Ethernet IRQ */
61#define IRQ_CFCARD 2 /* CF Card IRQ */
62#define IRQ_CFINST 3 /* CF Card Insert IRQ */
63#define IRQ_PCMCIA 4 /* PCMCIA IRQ */
64#define IRQ_VOYAGER 5 /* VOYAGER IRQ */
65#endif
66#define IRQ_RTCALM 6 /* RTC Alarm IRQ */
67#define IRQ_RTCTIME 7 /* RTC Timer IRQ */
68#define IRQ_SDCARD 8 /* SD Card IRQ */
69#define IRQ_PCISLOT1 9 /* PCI Slot #1 IRQ */
70#define IRQ_PCISLOT2 10 /* PCI Slot #2 IRQ */
71#define IRQ_EXTENTION 11 /* EXTn IRQ */
72
73#endif /* __ASM_SH_RENESAS_RTS7751R2D */
diff --git a/include/asm-sh/rts7751r2d/voyagergx_reg.h b/include/asm-sh/rts7751r2d/voyagergx_reg.h
new file mode 100644
index 000000000000..f031b5d6cf54
--- /dev/null
+++ b/include/asm-sh/rts7751r2d/voyagergx_reg.h
@@ -0,0 +1,313 @@
1/* -------------------------------------------------------------------- */
2/* voyagergx_reg.h */
3/* -------------------------------------------------------------------- */
4/* This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17
18 Copyright 2003 (c) Lineo uSolutions,Inc.
19*/
20/* -------------------------------------------------------------------- */
21
22#ifndef _VOYAGER_GX_REG_H
23#define _VOYAGER_GX_REG_H
24
25#define VOYAGER_BASE 0xb3e00000
26#define VOYAGER_USBH_BASE (0x40000 + VOYAGER_BASE)
27#define VOYAGER_UART_BASE (0x30000 + VOYAGER_BASE)
28#define VOYAGER_AC97_BASE (0xa0000 + VOYAGER_BASE)
29
30#define VOYAGER_IRQ_NUM 32
31#define VOYAGER_IRQ_BASE 50
32#define VOYAGER_USBH_IRQ VOYAGER_IRQ_BASE + 6
33#define VOYAGER_8051_IRQ VOYAGER_IRQ_BASE + 10
34#define VOYAGER_UART0_IRQ VOYAGER_IRQ_BASE + 12
35#define VOYAGER_UART1_IRQ VOYAGER_IRQ_BASE + 13
36#define VOYAGER_AC97_IRQ VOYAGER_IRQ_BASE + 17
37
38/* ----- MISC controle register ------------------------------ */
39#define MISC_CTRL (0x000004 + VOYAGER_BASE)
40#define MISC_CTRL_USBCLK_48 (3 << 28)
41#define MISC_CTRL_USBCLK_96 (2 << 28)
42#define MISC_CTRL_USBCLK_CRYSTAL (1 << 28)
43
44/* ----- GPIO[31:0] register --------------------------------- */
45#define GPIO_MUX_LOW (0x000008 + VOYAGER_BASE)
46#define GPIO_MUX_LOW_AC97 0x1F000000
47#define GPIO_MUX_LOW_8051 0x0000ffff
48#define GPIO_MUX_LOW_PWM (1 << 29)
49
50/* ----- GPIO[63:32] register --------------------------------- */
51#define GPIO_MUX_HIGH (0x00000C + VOYAGER_BASE)
52
53/* ----- DRAM controle register ------------------------------- */
54#define DRAM_CTRL (0x000010 + VOYAGER_BASE)
55#define DRAM_CTRL_EMBEDDED (1 << 31)
56#define DRAM_CTRL_CPU_BURST_1 (0 << 28)
57#define DRAM_CTRL_CPU_BURST_2 (1 << 28)
58#define DRAM_CTRL_CPU_BURST_4 (2 << 28)
59#define DRAM_CTRL_CPU_BURST_8 (3 << 28)
60#define DRAM_CTRL_CPU_CAS_LATENCY (1 << 27)
61#define DRAM_CTRL_CPU_SIZE_2 (0 << 24)
62#define DRAM_CTRL_CPU_SIZE_4 (1 << 24)
63#define DRAM_CTRL_CPU_SIZE_64 (4 << 24)
64#define DRAM_CTRL_CPU_SIZE_32 (5 << 24)
65#define DRAM_CTRL_CPU_SIZE_16 (6 << 24)
66#define DRAM_CTRL_CPU_SIZE_8 (7 << 24)
67#define DRAM_CTRL_CPU_COLUMN_SIZE_1024 (0 << 22)
68#define DRAM_CTRL_CPU_COLUMN_SIZE_512 (2 << 22)
69#define DRAM_CTRL_CPU_COLUMN_SIZE_256 (3 << 22)
70#define DRAM_CTRL_CPU_ACTIVE_PRECHARGE (1 << 21)
71#define DRAM_CTRL_CPU_RESET (1 << 20)
72#define DRAM_CTRL_CPU_BANKS (1 << 19)
73#define DRAM_CTRL_CPU_WRITE_PRECHARGE (1 << 18)
74#define DRAM_CTRL_BLOCK_WRITE (1 << 17)
75#define DRAM_CTRL_REFRESH_COMMAND (1 << 16)
76#define DRAM_CTRL_SIZE_4 (0 << 13)
77#define DRAM_CTRL_SIZE_8 (1 << 13)
78#define DRAM_CTRL_SIZE_16 (2 << 13)
79#define DRAM_CTRL_SIZE_32 (3 << 13)
80#define DRAM_CTRL_SIZE_64 (4 << 13)
81#define DRAM_CTRL_SIZE_2 (5 << 13)
82#define DRAM_CTRL_COLUMN_SIZE_256 (0 << 11)
83#define DRAM_CTRL_COLUMN_SIZE_512 (2 << 11)
84#define DRAM_CTRL_COLUMN_SIZE_1024 (3 << 11)
85#define DRAM_CTRL_BLOCK_WRITE_TIME (1 << 10)
86#define DRAM_CTRL_BLOCK_WRITE_PRECHARGE (1 << 9)
87#define DRAM_CTRL_ACTIVE_PRECHARGE (1 << 8)
88#define DRAM_CTRL_RESET (1 << 7)
89#define DRAM_CTRL_REMAIN_ACTIVE (1 << 6)
90#define DRAM_CTRL_BANKS (1 << 1)
91#define DRAM_CTRL_WRITE_PRECHARGE (1 << 0)
92
93/* ----- Arvitration control register -------------------------- */
94#define ARBITRATION_CTRL (0x000014 + VOYAGER_BASE)
95#define ARBITRATION_CTRL_CPUMEM (1 << 29)
96#define ARBITRATION_CTRL_INTMEM (1 << 28)
97#define ARBITRATION_CTRL_USB_OFF (0 << 24)
98#define ARBITRATION_CTRL_USB_PRIORITY_1 (1 << 24)
99#define ARBITRATION_CTRL_USB_PRIORITY_2 (2 << 24)
100#define ARBITRATION_CTRL_USB_PRIORITY_3 (3 << 24)
101#define ARBITRATION_CTRL_USB_PRIORITY_4 (4 << 24)
102#define ARBITRATION_CTRL_USB_PRIORITY_5 (5 << 24)
103#define ARBITRATION_CTRL_USB_PRIORITY_6 (6 << 24)
104#define ARBITRATION_CTRL_USB_PRIORITY_7 (7 << 24)
105#define ARBITRATION_CTRL_PANEL_OFF (0 << 20)
106#define ARBITRATION_CTRL_PANEL_PRIORITY_1 (1 << 20)
107#define ARBITRATION_CTRL_PANEL_PRIORITY_2 (2 << 20)
108#define ARBITRATION_CTRL_PANEL_PRIORITY_3 (3 << 20)
109#define ARBITRATION_CTRL_PANEL_PRIORITY_4 (4 << 20)
110#define ARBITRATION_CTRL_PANEL_PRIORITY_5 (5 << 20)
111#define ARBITRATION_CTRL_PANEL_PRIORITY_6 (6 << 20)
112#define ARBITRATION_CTRL_PANEL_PRIORITY_7 (7 << 20)
113#define ARBITRATION_CTRL_ZVPORT_OFF (0 << 16)
114#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_1 (1 << 16)
115#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_2 (2 << 16)
116#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_3 (3 << 16)
117#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_4 (4 << 16)
118#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_5 (5 << 16)
119#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_6 (6 << 16)
120#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_7 (7 << 16)
121#define ARBITRATION_CTRL_CMD_INTPR_OFF (0 << 12)
122#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_1 (1 << 12)
123#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_2 (2 << 12)
124#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_3 (3 << 12)
125#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_4 (4 << 12)
126#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_5 (5 << 12)
127#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_6 (6 << 12)
128#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_7 (7 << 12)
129#define ARBITRATION_CTRL_DMA_OFF (0 << 8)
130#define ARBITRATION_CTRL_DMA_PRIORITY_1 (1 << 8)
131#define ARBITRATION_CTRL_DMA_PRIORITY_2 (2 << 8)
132#define ARBITRATION_CTRL_DMA_PRIORITY_3 (3 << 8)
133#define ARBITRATION_CTRL_DMA_PRIORITY_4 (4 << 8)
134#define ARBITRATION_CTRL_DMA_PRIORITY_5 (5 << 8)
135#define ARBITRATION_CTRL_DMA_PRIORITY_6 (6 << 8)
136#define ARBITRATION_CTRL_DMA_PRIORITY_7 (7 << 8)
137#define ARBITRATION_CTRL_VIDEO_OFF (0 << 4)
138#define ARBITRATION_CTRL_VIDEO_PRIORITY_1 (1 << 4)
139#define ARBITRATION_CTRL_VIDEO_PRIORITY_2 (2 << 4)
140#define ARBITRATION_CTRL_VIDEO_PRIORITY_3 (3 << 4)
141#define ARBITRATION_CTRL_VIDEO_PRIORITY_4 (4 << 4)
142#define ARBITRATION_CTRL_VIDEO_PRIORITY_5 (5 << 4)
143#define ARBITRATION_CTRL_VIDEO_PRIORITY_6 (6 << 4)
144#define ARBITRATION_CTRL_VIDEO_PRIORITY_7 (7 << 4)
145#define ARBITRATION_CTRL_CRT_OFF (0 << 0)
146#define ARBITRATION_CTRL_CRT_PRIORITY_1 (1 << 0)
147#define ARBITRATION_CTRL_CRT_PRIORITY_2 (2 << 0)
148#define ARBITRATION_CTRL_CRT_PRIORITY_3 (3 << 0)
149#define ARBITRATION_CTRL_CRT_PRIORITY_4 (4 << 0)
150#define ARBITRATION_CTRL_CRT_PRIORITY_5 (5 << 0)
151#define ARBITRATION_CTRL_CRT_PRIORITY_6 (6 << 0)
152#define ARBITRATION_CTRL_CRT_PRIORITY_7 (7 << 0)
153
154/* ----- Command list status register -------------------------- */
155#define CMD_INTPR_STATUS (0x000024 + VOYAGER_BASE)
156
157/* ----- Interrupt status register ----------------------------- */
158#define INT_STATUS (0x00002c + VOYAGER_BASE)
159#define INT_STATUS_UH (1 << 6)
160#define INT_STATUS_MC (1 << 10)
161#define INT_STATUS_U0 (1 << 12)
162#define INT_STATUS_U1 (1 << 13)
163#define INT_STATUS_AC (1 << 17)
164
165/* ----- Interrupt mask register ------------------------------ */
166#define VOYAGER_INT_MASK (0x000030 + VOYAGER_BASE)
167#define VOYAGER_INT_MASK_AC (1 << 17)
168
169/* ----- Current Gate register ---------------------------------*/
170#define CURRENT_GATE (0x000038 + VOYAGER_BASE)
171
172/* ----- Power mode 0 gate register --------------------------- */
173#define POWER_MODE0_GATE (0x000040 + VOYAGER_BASE)
174#define POWER_MODE0_GATE_G (1 << 6)
175#define POWER_MODE0_GATE_U0 (1 << 7)
176#define POWER_MODE0_GATE_U1 (1 << 8)
177#define POWER_MODE0_GATE_UH (1 << 11)
178#define POWER_MODE0_GATE_AC (1 << 18)
179
180/* ----- Power mode 1 gate register --------------------------- */
181#define POWER_MODE1_GATE (0x000048 + VOYAGER_BASE)
182#define POWER_MODE1_GATE_G (1 << 6)
183#define POWER_MODE1_GATE_U0 (1 << 7)
184#define POWER_MODE1_GATE_U1 (1 << 8)
185#define POWER_MODE1_GATE_UH (1 << 11)
186#define POWER_MODE1_GATE_AC (1 << 18)
187
188/* ----- Power mode 0 clock register -------------------------- */
189#define POWER_MODE0_CLOCK (0x000044 + VOYAGER_BASE)
190
191/* ----- Power mode 1 clock register -------------------------- */
192#define POWER_MODE1_CLOCK (0x00004C + VOYAGER_BASE)
193
194/* ----- Power mode controll register ------------------------- */
195#define POWER_MODE_CTRL (0x000054 + VOYAGER_BASE)
196
197/* ----- Miscellaneous Timing register ------------------------ */
198#define SYSTEM_DRAM_CTRL (0x000068 + VOYAGER_BASE)
199
200/* ----- PWM register ------------------------------------------*/
201#define PWM_0 (0x010020 + VOYAGER_BASE)
202#define PWM_0_HC(x) (((x)&0x0fff)<<20)
203#define PWM_0_LC(x) (((x)&0x0fff)<<8 )
204#define PWM_0_CLK_DEV(x) (((x)&0x000f)<<4 )
205#define PWM_0_EN (1<<0)
206
207/* ----- I2C register ----------------------------------------- */
208#define I2C_BYTECOUNT (0x010040 + VOYAGER_BASE)
209#define I2C_CONTROL (0x010041 + VOYAGER_BASE)
210#define I2C_STATUS (0x010042 + VOYAGER_BASE)
211#define I2C_RESET (0x010042 + VOYAGER_BASE)
212#define I2C_SADDRESS (0x010043 + VOYAGER_BASE)
213#define I2C_DATA (0x010044 + VOYAGER_BASE)
214
215/* ----- Controle register bits ----------------------------------------- */
216#define I2C_CONTROL_E (1 << 0)
217#define I2C_CONTROL_MODE (1 << 1)
218#define I2C_CONTROL_STATUS (1 << 2)
219#define I2C_CONTROL_INT (1 << 4)
220#define I2C_CONTROL_INTACK (1 << 5)
221#define I2C_CONTROL_REPEAT (1 << 6)
222
223/* ----- Status register bits ----------------------------------------- */
224#define I2C_STATUS_BUSY (1 << 0)
225#define I2C_STATUS_ACK (1 << 1)
226#define I2C_STATUS_ERROR (1 << 2)
227#define I2C_STATUS_COMPLETE (1 << 3)
228
229/* ----- Reset register ---------------------------------------------- */
230#define I2C_RESET_ERROR (1 << 2)
231
232/* ----- transmission frequencies ------------------------------------- */
233#define I2C_SADDRESS_SELECT (1 << 0)
234
235/* ----- Display Controll register ----------------------------------------- */
236#define PANEL_DISPLAY_CTRL (0x080000 + VOYAGER_BASE)
237#define PANEL_DISPLAY_CTRL_BIAS (1<<26)
238#define PANEL_PAN_CTRL (0x080004 + VOYAGER_BASE)
239#define PANEL_COLOR_KEY (0x080008 + VOYAGER_BASE)
240#define PANEL_FB_ADDRESS (0x08000C + VOYAGER_BASE)
241#define PANEL_FB_WIDTH (0x080010 + VOYAGER_BASE)
242#define PANEL_WINDOW_WIDTH (0x080014 + VOYAGER_BASE)
243#define PANEL_WINDOW_HEIGHT (0x080018 + VOYAGER_BASE)
244#define PANEL_PLANE_TL (0x08001C + VOYAGER_BASE)
245#define PANEL_PLANE_BR (0x080020 + VOYAGER_BASE)
246#define PANEL_HORIZONTAL_TOTAL (0x080024 + VOYAGER_BASE)
247#define PANEL_HORIZONTAL_SYNC (0x080028 + VOYAGER_BASE)
248#define PANEL_VERTICAL_TOTAL (0x08002C + VOYAGER_BASE)
249#define PANEL_VERTICAL_SYNC (0x080030 + VOYAGER_BASE)
250#define PANEL_CURRENT_LINE (0x080034 + VOYAGER_BASE)
251#define VIDEO_DISPLAY_CTRL (0x080040 + VOYAGER_BASE)
252#define VIDEO_FB_0_ADDRESS (0x080044 + VOYAGER_BASE)
253#define VIDEO_FB_WIDTH (0x080048 + VOYAGER_BASE)
254#define VIDEO_FB_0_LAST_ADDRESS (0x08004C + VOYAGER_BASE)
255#define VIDEO_PLANE_TL (0x080050 + VOYAGER_BASE)
256#define VIDEO_PLANE_BR (0x080054 + VOYAGER_BASE)
257#define VIDEO_SCALE (0x080058 + VOYAGER_BASE)
258#define VIDEO_INITIAL_SCALE (0x08005C + VOYAGER_BASE)
259#define VIDEO_YUV_CONSTANTS (0x080060 + VOYAGER_BASE)
260#define VIDEO_FB_1_ADDRESS (0x080064 + VOYAGER_BASE)
261#define VIDEO_FB_1_LAST_ADDRESS (0x080068 + VOYAGER_BASE)
262#define VIDEO_ALPHA_DISPLAY_CTRL (0x080080 + VOYAGER_BASE)
263#define VIDEO_ALPHA_FB_ADDRESS (0x080084 + VOYAGER_BASE)
264#define VIDEO_ALPHA_FB_WIDTH (0x080088 + VOYAGER_BASE)
265#define VIDEO_ALPHA_FB_LAST_ADDRESS (0x08008C + VOYAGER_BASE)
266#define VIDEO_ALPHA_PLANE_TL (0x080090 + VOYAGER_BASE)
267#define VIDEO_ALPHA_PLANE_BR (0x080094 + VOYAGER_BASE)
268#define VIDEO_ALPHA_SCALE (0x080098 + VOYAGER_BASE)
269#define VIDEO_ALPHA_INITIAL_SCALE (0x08009C + VOYAGER_BASE)
270#define VIDEO_ALPHA_CHROMA_KEY (0x0800A0 + VOYAGER_BASE)
271#define PANEL_HWC_ADDRESS (0x0800F0 + VOYAGER_BASE)
272#define PANEL_HWC_LOCATION (0x0800F4 + VOYAGER_BASE)
273#define PANEL_HWC_COLOR_12 (0x0800F8 + VOYAGER_BASE)
274#define PANEL_HWC_COLOR_3 (0x0800FC + VOYAGER_BASE)
275#define ALPHA_DISPLAY_CTRL (0x080100 + VOYAGER_BASE)
276#define ALPHA_FB_ADDRESS (0x080104 + VOYAGER_BASE)
277#define ALPHA_FB_WIDTH (0x080108 + VOYAGER_BASE)
278#define ALPHA_PLANE_TL (0x08010C + VOYAGER_BASE)
279#define ALPHA_PLANE_BR (0x080110 + VOYAGER_BASE)
280#define ALPHA_CHROMA_KEY (0x080114 + VOYAGER_BASE)
281#define CRT_DISPLAY_CTRL (0x080200 + VOYAGER_BASE)
282#define CRT_FB_ADDRESS (0x080204 + VOYAGER_BASE)
283#define CRT_FB_WIDTH (0x080208 + VOYAGER_BASE)
284#define CRT_HORIZONTAL_TOTAL (0x08020C + VOYAGER_BASE)
285#define CRT_HORIZONTAL_SYNC (0x080210 + VOYAGER_BASE)
286#define CRT_VERTICAL_TOTAL (0x080214 + VOYAGER_BASE)
287#define CRT_VERTICAL_SYNC (0x080218 + VOYAGER_BASE)
288#define CRT_SIGNATURE_ANALYZER (0x08021C + VOYAGER_BASE)
289#define CRT_CURRENT_LINE (0x080220 + VOYAGER_BASE)
290#define CRT_MONITOR_DETECT (0x080224 + VOYAGER_BASE)
291#define CRT_HWC_ADDRESS (0x080230 + VOYAGER_BASE)
292#define CRT_HWC_LOCATION (0x080234 + VOYAGER_BASE)
293#define CRT_HWC_COLOR_12 (0x080238 + VOYAGER_BASE)
294#define CRT_HWC_COLOR_3 (0x08023C + VOYAGER_BASE)
295#define CRT_PALETTE_RAM (0x080400 + VOYAGER_BASE)
296#define PANEL_PALETTE_RAM (0x080800 + VOYAGER_BASE)
297#define VIDEO_PALETTE_RAM (0x080C00 + VOYAGER_BASE)
298
299/* ----- 8051 Controle register ----------------------------------------- */
300#define VOYAGER_8051_BASE (0x000c0000 + VOYAGER_BASE)
301#define VOYAGER_8051_RESET (0x000b0000 + VOYAGER_BASE)
302#define VOYAGER_8051_SELECT (0x000b0004 + VOYAGER_BASE)
303#define VOYAGER_8051_CPU_INT (0x000b000c + VOYAGER_BASE)
304
305/* ----- AC97 Controle register ----------------------------------------- */
306#define AC97_TX_SLOT0 (0x00000000 + VOYAGER_AC97_BASE)
307#define AC97_CONTROL_STATUS (0x00000080 + VOYAGER_AC97_BASE)
308#define AC97C_READ (1 << 19)
309#define AC97C_WD_BIT (1 << 2)
310#define AC97C_INDEX_MASK 0x7f
311/* -------------------------------------------------------------------- */
312
313#endif /* _VOYAGER_GX_REG_H */
diff --git a/include/asm-sh/rwsem.h b/include/asm-sh/rwsem.h
new file mode 100644
index 000000000000..1be4337f5259
--- /dev/null
+++ b/include/asm-sh/rwsem.h
@@ -0,0 +1,170 @@
1/*
2 * include/asm-ppc/rwsem.h: R/W semaphores for SH using the stuff
3 * in lib/rwsem.c.
4 */
5
6#ifndef _ASM_SH_RWSEM_H
7#define _ASM_SH_RWSEM_H
8
9#ifdef __KERNEL__
10#include <linux/list.h>
11#include <linux/spinlock.h>
12#include <asm/atomic.h>
13#include <asm/system.h>
14
15/*
16 * the semaphore definition
17 */
18struct rw_semaphore {
19 long count;
20#define RWSEM_UNLOCKED_VALUE 0x00000000
21#define RWSEM_ACTIVE_BIAS 0x00000001
22#define RWSEM_ACTIVE_MASK 0x0000ffff
23#define RWSEM_WAITING_BIAS (-0x00010000)
24#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
25#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
26 spinlock_t wait_lock;
27 struct list_head wait_list;
28#if RWSEM_DEBUG
29 int debug;
30#endif
31};
32
33/*
34 * initialisation
35 */
36#if RWSEM_DEBUG
37#define __RWSEM_DEBUG_INIT , 0
38#else
39#define __RWSEM_DEBUG_INIT /* */
40#endif
41
42#define __RWSEM_INITIALIZER(name) \
43 { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
44 LIST_HEAD_INIT((name).wait_list) \
45 __RWSEM_DEBUG_INIT }
46
47#define DECLARE_RWSEM(name) \
48 struct rw_semaphore name = __RWSEM_INITIALIZER(name)
49
50extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
51extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
52extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
53extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
54
55static inline void init_rwsem(struct rw_semaphore *sem)
56{
57 sem->count = RWSEM_UNLOCKED_VALUE;
58 spin_lock_init(&sem->wait_lock);
59 INIT_LIST_HEAD(&sem->wait_list);
60#if RWSEM_DEBUG
61 sem->debug = 0;
62#endif
63}
64
65/*
66 * lock for reading
67 */
68static inline void __down_read(struct rw_semaphore *sem)
69{
70 if (atomic_inc_return((atomic_t *)(&sem->count)) > 0)
71 smp_wmb();
72 else
73 rwsem_down_read_failed(sem);
74}
75
76static inline int __down_read_trylock(struct rw_semaphore *sem)
77{
78 int tmp;
79
80 while ((tmp = sem->count) >= 0) {
81 if (tmp == cmpxchg(&sem->count, tmp,
82 tmp + RWSEM_ACTIVE_READ_BIAS)) {
83 smp_wmb();
84 return 1;
85 }
86 }
87 return 0;
88}
89
90/*
91 * lock for writing
92 */
93static inline void __down_write(struct rw_semaphore *sem)
94{
95 int tmp;
96
97 tmp = atomic_add_return(RWSEM_ACTIVE_WRITE_BIAS,
98 (atomic_t *)(&sem->count));
99 if (tmp == RWSEM_ACTIVE_WRITE_BIAS)
100 smp_wmb();
101 else
102 rwsem_down_write_failed(sem);
103}
104
105static inline int __down_write_trylock(struct rw_semaphore *sem)
106{
107 int tmp;
108
109 tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
110 RWSEM_ACTIVE_WRITE_BIAS);
111 smp_wmb();
112 return tmp == RWSEM_UNLOCKED_VALUE;
113}
114
115/*
116 * unlock after reading
117 */
118static inline void __up_read(struct rw_semaphore *sem)
119{
120 int tmp;
121
122 smp_wmb();
123 tmp = atomic_dec_return((atomic_t *)(&sem->count));
124 if (tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0)
125 rwsem_wake(sem);
126}
127
128/*
129 * unlock after writing
130 */
131static inline void __up_write(struct rw_semaphore *sem)
132{
133 smp_wmb();
134 if (atomic_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
135 (atomic_t *)(&sem->count)) < 0)
136 rwsem_wake(sem);
137}
138
139/*
140 * implement atomic add functionality
141 */
142static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
143{
144 atomic_add(delta, (atomic_t *)(&sem->count));
145}
146
147/*
148 * downgrade write lock to read lock
149 */
150static inline void __downgrade_write(struct rw_semaphore *sem)
151{
152 int tmp;
153
154 smp_wmb();
155 tmp = atomic_add_return(-RWSEM_WAITING_BIAS, (atomic_t *)(&sem->count));
156 if (tmp < 0)
157 rwsem_downgrade_wake(sem);
158}
159
160/*
161 * implement exchange and add functionality
162 */
163static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
164{
165 smp_mb();
166 return atomic_add_return(delta, (atomic_t *)(&sem->count));
167}
168
169#endif /* __KERNEL__ */
170#endif /* _ASM_SH_RWSEM_H */
diff --git a/include/asm-sh/saturn/io.h b/include/asm-sh/saturn/io.h
new file mode 100644
index 000000000000..f1b9b5d633f4
--- /dev/null
+++ b/include/asm-sh/saturn/io.h
@@ -0,0 +1,19 @@
1/*
2 * include/asm-sh/saturn/io.h
3 *
4 * I/O functions for use on the Sega Saturn.
5 *
6 * Copyright (C) 2002 Paul Mundt
7 *
8 * Released under the terms of the GNU GPL v2.0.
9 */
10#ifndef __ASM_SH_SATURN_IO_H
11#define __ASM_SH_SATURN_IO_H
12
13/* arch/sh/boards/saturn/io.c */
14extern unsigned long saturn_isa_port2addr(unsigned long offset);
15extern void *saturn_ioremap(unsigned long offset, unsigned long size);
16extern void saturn_iounmap(void *addr);
17
18#endif /* __ASM_SH_SATURN_IO_H */
19
diff --git a/include/asm-sh/saturn/smpc.h b/include/asm-sh/saturn/smpc.h
new file mode 100644
index 000000000000..5de5c12d6347
--- /dev/null
+++ b/include/asm-sh/saturn/smpc.h
@@ -0,0 +1,34 @@
1/*
2 * include/asm-sh/saturn/smpc.h
3 *
4 * System Manager / Peripheral Control definitions.
5 *
6 * Copyright (C) 2002 Paul Mundt
7 *
8 * Released under the terms of the GNU GPL v2.0.
9 */
10#ifndef __ASM_SH_SATURN_SMPC_H
11#define __ASM_SH_SATURN_SMPC_H
12
13#include <asm/io.h>
14
15#define SMPC_COMMAND 0x2010001f /* SMPC command register */
16#define SMPC_RESULT 0x2010005f /* SMPC result register */
17#define SMPC_STATUS 0x20100063 /* SMPC status register */
18
19#define SMPC_CMD_MSHON 0x0001 /* Master SH On */
20#define SMPC_CMD_SSHON 0x0002 /* Slave SH On */
21#define SMPC_CMD_SSHOFF 0x0003 /* Slave SH Off */
22#define SMPC_CMD_SNDON 0x0004 /* Sound On */
23#define SMPC_CMD_SNDOFF 0x0005 /* Sound Off */
24#define SMPC_CMD_CDON 0x0006 /* CD On */
25#define SMPC_CMD_CDOFF 0x0007 /* CD Off */
26
27static inline void smpc_barrier(void)
28{
29 while ((ctrl_inb(SMPC_STATUS) & 0x0001) == 0x0001)
30 ;
31}
32
33#endif /* __ASM_SH_SATURN_SMPC_H */
34
diff --git a/include/asm-sh/scatterlist.h b/include/asm-sh/scatterlist.h
new file mode 100644
index 000000000000..7b91df140022
--- /dev/null
+++ b/include/asm-sh/scatterlist.h
@@ -0,0 +1,13 @@
1#ifndef __ASM_SH_SCATTERLIST_H
2#define __ASM_SH_SCATTERLIST_H
3
4struct scatterlist {
5 struct page * page; /* Location for highmem page, if any */
6 unsigned int offset;/* for highmem, page offset */
7 dma_addr_t dma_address;
8 unsigned int length;
9};
10
11#define ISA_DMA_THRESHOLD (0x1fffffff)
12
13#endif /* !(__ASM_SH_SCATTERLIST_H) */
diff --git a/include/asm-sh/se/io.h b/include/asm-sh/se/io.h
new file mode 100644
index 000000000000..9eeb86cd6cef
--- /dev/null
+++ b/include/asm-sh/se/io.h
@@ -0,0 +1,35 @@
1/*
2 * include/asm-sh/io_se.h
3 *
4 * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * IO functions for an Hitachi SolutionEngine
10 */
11
12#ifndef _ASM_SH_IO_SE_H
13#define _ASM_SH_IO_SE_H
14
15extern unsigned char se_inb(unsigned long port);
16extern unsigned short se_inw(unsigned long port);
17extern unsigned int se_inl(unsigned long port);
18
19extern void se_outb(unsigned char value, unsigned long port);
20extern void se_outw(unsigned short value, unsigned long port);
21extern void se_outl(unsigned int value, unsigned long port);
22
23extern unsigned char se_inb_p(unsigned long port);
24extern void se_outb_p(unsigned char value, unsigned long port);
25
26extern void se_insb(unsigned long port, void *addr, unsigned long count);
27extern void se_insw(unsigned long port, void *addr, unsigned long count);
28extern void se_insl(unsigned long port, void *addr, unsigned long count);
29extern void se_outsb(unsigned long port, const void *addr, unsigned long count);
30extern void se_outsw(unsigned long port, const void *addr, unsigned long count);
31extern void se_outsl(unsigned long port, const void *addr, unsigned long count);
32
33extern unsigned long se_isa_port2addr(unsigned long offset);
34
35#endif /* _ASM_SH_IO_SE_H */
diff --git a/include/asm-sh/se/se.h b/include/asm-sh/se/se.h
new file mode 100644
index 000000000000..791c5da0388a
--- /dev/null
+++ b/include/asm-sh/se/se.h
@@ -0,0 +1,77 @@
1#ifndef __ASM_SH_HITACHI_SE_H
2#define __ASM_SH_HITACHI_SE_H
3
4/*
5 * linux/include/asm-sh/hitachi_se.h
6 *
7 * Copyright (C) 2000 Kazumoto Kojima
8 *
9 * Hitachi SolutionEngine support
10 */
11
12/* Box specific addresses. */
13
14#define PA_ROM 0x00000000 /* EPROM */
15#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
16#define PA_FROM 0x01000000 /* EPROM */
17#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
18#define PA_EXT1 0x04000000
19#define PA_EXT1_SIZE 0x04000000
20#define PA_EXT2 0x08000000
21#define PA_EXT2_SIZE 0x04000000
22#define PA_SDRAM 0x0c000000
23#define PA_SDRAM_SIZE 0x04000000
24
25#define PA_EXT4 0x12000000
26#define PA_EXT4_SIZE 0x02000000
27#define PA_EXT5 0x14000000
28#define PA_EXT5_SIZE 0x04000000
29#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
30
31#define PA_83902 0xb0000000 /* DP83902A */
32#define PA_83902_IF 0xb0040000 /* DP83902A remote io port */
33#define PA_83902_RST 0xb0080000 /* DP83902A reset port */
34
35#define PA_SUPERIO 0xb0400000 /* SMC37C935A super io chip */
36#define PA_DIPSW0 0xb0800000 /* Dip switch 5,6 */
37#define PA_DIPSW1 0xb0800002 /* Dip switch 7,8 */
38#define PA_LED 0xb0c00000 /* LED */
39#if defined(CONFIG_CPU_SUBTYPE_SH7705)
40#define PA_BCR 0xb0e00000
41#else
42#define PA_BCR 0xb1400000 /* FPGA */
43#endif
44
45#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */
46#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
47#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
48#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
49#define MRSHPC_OPTION (PA_MRSHPC + 6)
50#define MRSHPC_CSR (PA_MRSHPC + 8)
51#define MRSHPC_ISR (PA_MRSHPC + 10)
52#define MRSHPC_ICR (PA_MRSHPC + 12)
53#define MRSHPC_CPWCR (PA_MRSHPC + 14)
54#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
55#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
56#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
57#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
58#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
59#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
60#define MRSHPC_CDCR (PA_MRSHPC + 28)
61#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
62
63#define BCR_ILCRA (PA_BCR + 0)
64#define BCR_ILCRB (PA_BCR + 2)
65#define BCR_ILCRC (PA_BCR + 4)
66#define BCR_ILCRD (PA_BCR + 6)
67#define BCR_ILCRE (PA_BCR + 8)
68#define BCR_ILCRF (PA_BCR + 10)
69#define BCR_ILCRG (PA_BCR + 12)
70
71#if defined(CONFIG_CPU_SUBTYPE_SH7705)
72#define IRQ_STNIC 12
73#else
74#define IRQ_STNIC 10
75#endif
76
77#endif /* __ASM_SH_HITACHI_SE_H */
diff --git a/include/asm-sh/se/smc37c93x.h b/include/asm-sh/se/smc37c93x.h
new file mode 100644
index 000000000000..585da2a8fc45
--- /dev/null
+++ b/include/asm-sh/se/smc37c93x.h
@@ -0,0 +1,190 @@
1#ifndef __ASM_SH_SMC37C93X_H
2#define __ASM_SH_SMC37C93X_H
3
4/*
5 * linux/include/asm-sh/smc37c93x.h
6 *
7 * Copyright (C) 2000 Kazumoto Kojima
8 *
9 * SMSC 37C93x Super IO Chip support
10 */
11
12/* Default base I/O address */
13#define FDC_PRIMARY_BASE 0x3f0
14#define IDE1_PRIMARY_BASE 0x1f0
15#define IDE1_SECONDARY_BASE 0x170
16#define PARPORT_PRIMARY_BASE 0x378
17#define COM1_PRIMARY_BASE 0x2f8
18#define COM2_PRIMARY_BASE 0x3f8
19#define RTC_PRIMARY_BASE 0x070
20#define KBC_PRIMARY_BASE 0x060
21#define AUXIO_PRIMARY_BASE 0x000 /* XXX */
22
23/* Logical device number */
24#define LDN_FDC 0
25#define LDN_IDE1 1
26#define LDN_IDE2 2
27#define LDN_PARPORT 3
28#define LDN_COM1 4
29#define LDN_COM2 5
30#define LDN_RTC 6
31#define LDN_KBC 7
32#define LDN_AUXIO 8
33
34/* Configuration port and key */
35#define CONFIG_PORT 0x3f0
36#define INDEX_PORT CONFIG_PORT
37#define DATA_PORT 0x3f1
38#define CONFIG_ENTER 0x55
39#define CONFIG_EXIT 0xaa
40
41/* Configuration index */
42#define CURRENT_LDN_INDEX 0x07
43#define POWER_CONTROL_INDEX 0x22
44#define ACTIVATE_INDEX 0x30
45#define IO_BASE_HI_INDEX 0x60
46#define IO_BASE_LO_INDEX 0x61
47#define IRQ_SELECT_INDEX 0x70
48#define DMA_SELECT_INDEX 0x74
49
50#define GPIO46_INDEX 0xc6
51#define GPIO47_INDEX 0xc7
52
53/* UART stuff. Only for debugging. */
54/* UART Register */
55
56#define UART_RBR 0x0 /* Receiver Buffer Register (Read Only) */
57#define UART_THR 0x0 /* Transmitter Holding Register (Write Only) */
58#define UART_IER 0x2 /* Interrupt Enable Register */
59#define UART_IIR 0x4 /* Interrupt Ident Register (Read Only) */
60#define UART_FCR 0x4 /* FIFO Control Register (Write Only) */
61#define UART_LCR 0x6 /* Line Control Register */
62#define UART_MCR 0x8 /* MODEM Control Register */
63#define UART_LSR 0xa /* Line Status Register */
64#define UART_MSR 0xc /* MODEM Status Register */
65#define UART_SCR 0xe /* Scratch Register */
66#define UART_DLL 0x0 /* Divisor Latch (LS) */
67#define UART_DLM 0x2 /* Divisor Latch (MS) */
68
69#ifndef __ASSEMBLY__
70typedef struct uart_reg {
71 volatile __u16 rbr;
72 volatile __u16 ier;
73 volatile __u16 iir;
74 volatile __u16 lcr;
75 volatile __u16 mcr;
76 volatile __u16 lsr;
77 volatile __u16 msr;
78 volatile __u16 scr;
79} uart_reg;
80#endif /* ! __ASSEMBLY__ */
81
82/* Alias for Write Only Register */
83
84#define thr rbr
85#define tcr iir
86
87/* Alias for Divisor Latch Register */
88
89#define dll rbr
90#define dlm ier
91#define fcr iir
92
93/* Interrupt Enable Register */
94
95#define IER_ERDAI 0x0100 /* Enable Received Data Available Interrupt */
96#define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */
97#define IER_ELSI 0x0400 /* Enable Receiver Line Status Interrupt */
98#define IER_EMSI 0x0800 /* Enable MODEM Status Interrupt */
99
100/* Interrupt Ident Register */
101
102#define IIR_IP 0x0100 /* "0" if Interrupt Pending */
103#define IIR_IIB0 0x0200 /* Interrupt ID Bit 0 */
104#define IIR_IIB1 0x0400 /* Interrupt ID Bit 1 */
105#define IIR_IIB2 0x0800 /* Interrupt ID Bit 2 */
106#define IIR_FIFO 0xc000 /* FIFOs enabled */
107
108/* FIFO Control Register */
109
110#define FCR_FEN 0x0100 /* FIFO enable */
111#define FCR_RFRES 0x0200 /* Receiver FIFO reset */
112#define FCR_TFRES 0x0400 /* Transmitter FIFO reset */
113#define FCR_DMA 0x0800 /* DMA mode select */
114#define FCR_RTL 0x4000 /* Receiver triger (LSB) */
115#define FCR_RTM 0x8000 /* Receiver triger (MSB) */
116
117/* Line Control Register */
118
119#define LCR_WLS0 0x0100 /* Word Length Select Bit 0 */
120#define LCR_WLS1 0x0200 /* Word Length Select Bit 1 */
121#define LCR_STB 0x0400 /* Number of Stop Bits */
122#define LCR_PEN 0x0800 /* Parity Enable */
123#define LCR_EPS 0x1000 /* Even Parity Select */
124#define LCR_SP 0x2000 /* Stick Parity */
125#define LCR_SB 0x4000 /* Set Break */
126#define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */
127
128/* MODEM Control Register */
129
130#define MCR_DTR 0x0100 /* Data Terminal Ready */
131#define MCR_RTS 0x0200 /* Request to Send */
132#define MCR_OUT1 0x0400 /* Out 1 */
133#define MCR_IRQEN 0x0800 /* IRQ Enable */
134#define MCR_LOOP 0x1000 /* Loop */
135
136/* Line Status Register */
137
138#define LSR_DR 0x0100 /* Data Ready */
139#define LSR_OE 0x0200 /* Overrun Error */
140#define LSR_PE 0x0400 /* Parity Error */
141#define LSR_FE 0x0800 /* Framing Error */
142#define LSR_BI 0x1000 /* Break Interrupt */
143#define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */
144#define LSR_TEMT 0x4000 /* Transmitter Empty */
145#define LSR_FIFOE 0x8000 /* Receiver FIFO error */
146
147/* MODEM Status Register */
148
149#define MSR_DCTS 0x0100 /* Delta Clear to Send */
150#define MSR_DDSR 0x0200 /* Delta Data Set Ready */
151#define MSR_TERI 0x0400 /* Trailing Edge Ring Indicator */
152#define MSR_DDCD 0x0800 /* Delta Data Carrier Detect */
153#define MSR_CTS 0x1000 /* Clear to Send */
154#define MSR_DSR 0x2000 /* Data Set Ready */
155#define MSR_RI 0x4000 /* Ring Indicator */
156#define MSR_DCD 0x8000 /* Data Carrier Detect */
157
158/* Baud Rate Divisor */
159
160#define UART_CLK (1843200) /* 1.8432 MHz */
161#define UART_BAUD(x) (UART_CLK / (16 * (x)))
162
163/* RTC register definition */
164#define RTC_SECONDS 0
165#define RTC_SECONDS_ALARM 1
166#define RTC_MINUTES 2
167#define RTC_MINUTES_ALARM 3
168#define RTC_HOURS 4
169#define RTC_HOURS_ALARM 5
170#define RTC_DAY_OF_WEEK 6
171#define RTC_DAY_OF_MONTH 7
172#define RTC_MONTH 8
173#define RTC_YEAR 9
174#define RTC_FREQ_SELECT 10
175# define RTC_UIP 0x80
176# define RTC_DIV_CTL 0x70
177/* This RTC can work under 32.768KHz clock only. */
178# define RTC_OSC_ENABLE 0x20
179# define RTC_OSC_DISABLE 0x00
180#define RTC_CONTROL 11
181# define RTC_SET 0x80
182# define RTC_PIE 0x40
183# define RTC_AIE 0x20
184# define RTC_UIE 0x10
185# define RTC_SQWE 0x08
186# define RTC_DM_BINARY 0x04
187# define RTC_24H 0x02
188# define RTC_DST_EN 0x01
189
190#endif /* __ASM_SH_SMC37C93X_H */
diff --git a/include/asm-sh/se7300/io.h b/include/asm-sh/se7300/io.h
new file mode 100644
index 000000000000..c6af85529714
--- /dev/null
+++ b/include/asm-sh/se7300/io.h
@@ -0,0 +1,29 @@
1/*
2 * include/asm-sh/se7300/io.h
3 *
4 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
5 * IO functions for SH-Mobile(SH7300) SolutionEngine
6 */
7
8#ifndef _ASM_SH_IO_7300SE_H
9#define _ASM_SH_IO_7300SE_H
10
11extern unsigned char sh7300se_inb(unsigned long port);
12extern unsigned short sh7300se_inw(unsigned long port);
13extern unsigned int sh7300se_inl(unsigned long port);
14
15extern void sh7300se_outb(unsigned char value, unsigned long port);
16extern void sh7300se_outw(unsigned short value, unsigned long port);
17extern void sh7300se_outl(unsigned int value, unsigned long port);
18
19extern unsigned char sh7300se_inb_p(unsigned long port);
20extern void sh7300se_outb_p(unsigned char value, unsigned long port);
21
22extern void sh7300se_insb(unsigned long port, void *addr, unsigned long count);
23extern void sh7300se_insw(unsigned long port, void *addr, unsigned long count);
24extern void sh7300se_insl(unsigned long port, void *addr, unsigned long count);
25extern void sh7300se_outsb(unsigned long port, const void *addr, unsigned long count);
26extern void sh7300se_outsw(unsigned long port, const void *addr, unsigned long count);
27extern void sh7300se_outsl(unsigned long port, const void *addr, unsigned long count);
28
29#endif /* _ASM_SH_IO_7300SE_H */
diff --git a/include/asm-sh/se7300/se7300.h b/include/asm-sh/se7300/se7300.h
new file mode 100644
index 000000000000..3ec1ded86c97
--- /dev/null
+++ b/include/asm-sh/se7300/se7300.h
@@ -0,0 +1,61 @@
1#ifndef __ASM_SH_HITACHI_SE7300_H
2#define __ASM_SH_HITACHI_SE7300_H
3
4/*
5 * linux/include/asm-sh/se/se7300.h
6 *
7 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
8 *
9 * SH-Mobile SolutionEngine 7300 support
10 */
11
12/* Box specific addresses. */
13
14/* Area 0 */
15#define PA_ROM 0x00000000 /* EPROM */
16#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */
17#define PA_FROM 0x00400000 /* Flash ROM */
18#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */
19#define PA_SRAM 0x00800000 /* SRAM */
20#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */
21/* Area 1 */
22#define PA_EXT1 0x04000000
23#define PA_EXT1_SIZE 0x04000000
24/* Area 2 */
25#define PA_EXT2 0x08000000
26#define PA_EXT2_SIZE 0x04000000
27/* Area 3 */
28#define PA_SDRAM 0x0c000000
29#define PA_SDRAM_SIZE 0x04000000
30/* Area 4 */
31#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */
32#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */
33#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */
34#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */
35#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */
36#define MRSHPC_OPTION (PA_MRSHPC + 6)
37#define MRSHPC_CSR (PA_MRSHPC + 8)
38#define MRSHPC_ISR (PA_MRSHPC + 10)
39#define MRSHPC_ICR (PA_MRSHPC + 12)
40#define MRSHPC_CPWCR (PA_MRSHPC + 14)
41#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
42#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
43#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
44#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
45#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
46#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
47#define MRSHPC_CDCR (PA_MRSHPC + 28)
48#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
49#define PA_LED 0xb0800000 /* LED */
50#define PA_DIPSW 0xb0900000 /* Dip switch 31 */
51#define PA_EPLD_MODESET 0xb0a00000 /* FPGA Mode set register */
52#define PA_EPLD_ST1 0xb0a80000 /* FPGA Interrupt status register1 */
53#define PA_EPLD_ST2 0xb0ac0000 /* FPGA Interrupt status register2 */
54/* Area 5 */
55#define PA_EXT5 0x14000000
56#define PA_EXT5_SIZE 0x04000000
57/* Area 6 */
58#define PA_LCD1 0xb8000000
59#define PA_LCD2 0xb8800000
60
61#endif /* __ASM_SH_HITACHI_SE7300_H */
diff --git a/include/asm-sh/se73180/io.h b/include/asm-sh/se73180/io.h
new file mode 100644
index 000000000000..c9cb1b9412c6
--- /dev/null
+++ b/include/asm-sh/se73180/io.h
@@ -0,0 +1,32 @@
1/*
2 * include/asm-sh/se73180/io.h
3 *
4 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
5 * Based on include/asm-sh/se7300/io.h
6 *
7 * IO functions for SH-Mobile3(SH73180) SolutionEngine
8 *
9 */
10
11#ifndef _ASM_SH_IO_73180SE_H
12#define _ASM_SH_IO_73180SE_H
13
14extern unsigned char sh73180se_inb(unsigned long port);
15extern unsigned short sh73180se_inw(unsigned long port);
16extern unsigned int sh73180se_inl(unsigned long port);
17
18extern void sh73180se_outb(unsigned char value, unsigned long port);
19extern void sh73180se_outw(unsigned short value, unsigned long port);
20extern void sh73180se_outl(unsigned int value, unsigned long port);
21
22extern unsigned char sh73180se_inb_p(unsigned long port);
23extern void sh73180se_outb_p(unsigned char value, unsigned long port);
24
25extern void sh73180se_insb(unsigned long port, void *addr, unsigned long count);
26extern void sh73180se_insw(unsigned long port, void *addr, unsigned long count);
27extern void sh73180se_insl(unsigned long port, void *addr, unsigned long count);
28extern void sh73180se_outsb(unsigned long port, const void *addr, unsigned long count);
29extern void sh73180se_outsw(unsigned long port, const void *addr, unsigned long count);
30extern void sh73180se_outsl(unsigned long port, const void *addr, unsigned long count);
31
32#endif /* _ASM_SH_IO_73180SE_H */
diff --git a/include/asm-sh/se73180/se73180.h b/include/asm-sh/se73180/se73180.h
new file mode 100644
index 000000000000..f5b93e39e768
--- /dev/null
+++ b/include/asm-sh/se73180/se73180.h
@@ -0,0 +1,62 @@
1#ifndef __ASM_SH_HITACHI_SE73180_H
2#define __ASM_SH_HITACHI_SE73180_H
3
4/*
5 * include/asm-sh/se/se73180.h
6 *
7 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
8 *
9 * SH-Mobile SolutionEngine 73180 support
10 */
11
12/* Box specific addresses. */
13
14/* Area 0 */
15#define PA_ROM 0x00000000 /* EPROM */
16#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */
17#define PA_FROM 0x00400000 /* Flash ROM */
18#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */
19#define PA_SRAM 0x00800000 /* SRAM */
20#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */
21/* Area 1 */
22#define PA_EXT1 0x04000000
23#define PA_EXT1_SIZE 0x04000000
24/* Area 2 */
25#define PA_EXT2 0x08000000
26#define PA_EXT2_SIZE 0x04000000
27/* Area 3 */
28#define PA_SDRAM 0x0c000000
29#define PA_SDRAM_SIZE 0x04000000
30/* Area 4 */
31#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */
32#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */
33#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */
34#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */
35#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */
36#define MRSHPC_OPTION (PA_MRSHPC + 6)
37#define MRSHPC_CSR (PA_MRSHPC + 8)
38#define MRSHPC_ISR (PA_MRSHPC + 10)
39#define MRSHPC_ICR (PA_MRSHPC + 12)
40#define MRSHPC_CPWCR (PA_MRSHPC + 14)
41#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
42#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
43#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
44#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
45#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
46#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
47#define MRSHPC_CDCR (PA_MRSHPC + 28)
48#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
49#define PA_LED 0xb0C00000 /* LED */
50#define LED_SHIFT 0
51#define PA_DIPSW 0xb0900000 /* Dip switch 31 */
52#define PA_EPLD_MODESET 0xb0a00000 /* FPGA Mode set register */
53#define PA_EPLD_ST1 0xb0a80000 /* FPGA Interrupt status register1 */
54#define PA_EPLD_ST2 0xb0ac0000 /* FPGA Interrupt status register2 */
55/* Area 5 */
56#define PA_EXT5 0x14000000
57#define PA_EXT5_SIZE 0x04000000
58/* Area 6 */
59#define PA_LCD1 0xb8000000
60#define PA_LCD2 0xb8800000
61
62#endif /* __ASM_SH_HITACHI_SE73180_H */
diff --git a/include/asm-sh/se7751/io.h b/include/asm-sh/se7751/io.h
new file mode 100644
index 000000000000..78d8f5744bc5
--- /dev/null
+++ b/include/asm-sh/se7751/io.h
@@ -0,0 +1,42 @@
1/*
2 * include/asm-sh/io_7751se.h
3 *
4 * Modified version of io_se.h for the 7751se-specific functions.
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * IO functions for an Hitachi SolutionEngine
10 */
11
12#ifndef _ASM_SH_IO_7751SE_H
13#define _ASM_SH_IO_7751SE_H
14
15extern unsigned char sh7751se_inb(unsigned long port);
16extern unsigned short sh7751se_inw(unsigned long port);
17extern unsigned int sh7751se_inl(unsigned long port);
18
19extern void sh7751se_outb(unsigned char value, unsigned long port);
20extern void sh7751se_outw(unsigned short value, unsigned long port);
21extern void sh7751se_outl(unsigned int value, unsigned long port);
22
23extern unsigned char sh7751se_inb_p(unsigned long port);
24extern void sh7751se_outb_p(unsigned char value, unsigned long port);
25
26extern void sh7751se_insb(unsigned long port, void *addr, unsigned long count);
27extern void sh7751se_insw(unsigned long port, void *addr, unsigned long count);
28extern void sh7751se_insl(unsigned long port, void *addr, unsigned long count);
29extern void sh7751se_outsb(unsigned long port, const void *addr, unsigned long count);
30extern void sh7751se_outsw(unsigned long port, const void *addr, unsigned long count);
31extern void sh7751se_outsl(unsigned long port, const void *addr, unsigned long count);
32
33extern unsigned char sh7751se_readb(unsigned long addr);
34extern unsigned short sh7751se_readw(unsigned long addr);
35extern unsigned int sh7751se_readl(unsigned long addr);
36extern void sh7751se_writeb(unsigned char b, unsigned long addr);
37extern void sh7751se_writew(unsigned short b, unsigned long addr);
38extern void sh7751se_writel(unsigned int b, unsigned long addr);
39
40extern unsigned long sh7751se_isa_port2addr(unsigned long offset);
41
42#endif /* _ASM_SH_IO_7751SE_H */
diff --git a/include/asm-sh/se7751/se7751.h b/include/asm-sh/se7751/se7751.h
new file mode 100644
index 000000000000..738e22bebdfb
--- /dev/null
+++ b/include/asm-sh/se7751/se7751.h
@@ -0,0 +1,68 @@
1#ifndef __ASM_SH_HITACHI_7751SE_H
2#define __ASM_SH_HITACHI_7751SE_H
3
4/*
5 * linux/include/asm-sh/hitachi_7751se.h
6 *
7 * Copyright (C) 2000 Kazumoto Kojima
8 *
9 * Hitachi SolutionEngine support
10
11 * Modified for 7751 Solution Engine by
12 * Ian da Silva and Jeremy Siegel, 2001.
13 */
14
15/* Box specific addresses. */
16
17#define PA_ROM 0x00000000 /* EPROM */
18#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
19#define PA_FROM 0x01000000 /* EPROM */
20#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
21#define PA_EXT1 0x04000000
22#define PA_EXT1_SIZE 0x04000000
23#define PA_EXT2 0x08000000
24#define PA_EXT2_SIZE 0x04000000
25#define PA_SDRAM 0x0c000000
26#define PA_SDRAM_SIZE 0x04000000
27
28#define PA_EXT4 0x12000000
29#define PA_EXT4_SIZE 0x02000000
30#define PA_EXT5 0x14000000
31#define PA_EXT5_SIZE 0x04000000
32#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
33
34#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */
35#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */
36#define PA_LED 0xba000000 /* LED */
37#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */
38
39#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controler */
40#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
41#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
42#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
43#define MRSHPC_MODE (PA_MRSHPC + 4)
44#define MRSHPC_OPTION (PA_MRSHPC + 6)
45#define MRSHPC_CSR (PA_MRSHPC + 8)
46#define MRSHPC_ISR (PA_MRSHPC + 10)
47#define MRSHPC_ICR (PA_MRSHPC + 12)
48#define MRSHPC_CPWCR (PA_MRSHPC + 14)
49#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
50#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
51#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
52#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
53#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
54#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
55#define MRSHPC_CDCR (PA_MRSHPC + 28)
56#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
57
58#define BCR_ILCRA (PA_BCR + 0)
59#define BCR_ILCRB (PA_BCR + 2)
60#define BCR_ILCRC (PA_BCR + 4)
61#define BCR_ILCRD (PA_BCR + 6)
62#define BCR_ILCRE (PA_BCR + 8)
63#define BCR_ILCRF (PA_BCR + 10)
64#define BCR_ILCRG (PA_BCR + 12)
65
66#define IRQ_79C973 13
67
68#endif /* __ASM_SH_HITACHI_7751SE_H */
diff --git a/include/asm-sh/sections.h b/include/asm-sh/sections.h
new file mode 100644
index 000000000000..57abd708b236
--- /dev/null
+++ b/include/asm-sh/sections.h
@@ -0,0 +1,9 @@
1#ifndef __ASM_SH_SECTIONS_H
2#define __ASM_SH_SECTIONS_H
3
4#include <asm-generic/sections.h>
5
6extern char _end[];
7
8#endif /* __ASM_SH_SECTIONS_H */
9
diff --git a/include/asm-sh/segment.h b/include/asm-sh/segment.h
new file mode 100644
index 000000000000..e417eab4c7d7
--- /dev/null
+++ b/include/asm-sh/segment.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_SH_SEGMENT_H
2#define __ASM_SH_SEGMENT_H
3
4/* Only here because we have some old header files that expect it.. */
5
6#endif /* __ASM_SH_SEGMENT_H */
diff --git a/include/asm-sh/semaphore-helper.h b/include/asm-sh/semaphore-helper.h
new file mode 100644
index 000000000000..bd8230c369ca
--- /dev/null
+++ b/include/asm-sh/semaphore-helper.h
@@ -0,0 +1,89 @@
1#ifndef __ASM_SH_SEMAPHORE_HELPER_H
2#define __ASM_SH_SEMAPHORE_HELPER_H
3
4/*
5 * SMP- and interrupt-safe semaphores helper functions.
6 *
7 * (C) Copyright 1996 Linus Torvalds
8 * (C) Copyright 1999 Andrea Arcangeli
9 */
10
11/*
12 * These two _must_ execute atomically wrt each other.
13 *
14 * This is trivially done with load_locked/store_cond,
15 * which we have. Let the rest of the losers suck eggs.
16 */
17static __inline__ void wake_one_more(struct semaphore * sem)
18{
19 atomic_inc((atomic_t *)&sem->sleepers);
20}
21
22static __inline__ int waking_non_zero(struct semaphore *sem)
23{
24 unsigned long flags;
25 int ret = 0;
26
27 spin_lock_irqsave(&semaphore_wake_lock, flags);
28 if (sem->sleepers > 0) {
29 sem->sleepers--;
30 ret = 1;
31 }
32 spin_unlock_irqrestore(&semaphore_wake_lock, flags);
33 return ret;
34}
35
36/*
37 * waking_non_zero_interruptible:
38 * 1 got the lock
39 * 0 go to sleep
40 * -EINTR interrupted
41 *
42 * We must undo the sem->count down_interruptible() increment while we are
43 * protected by the spinlock in order to make atomic this atomic_inc() with the
44 * atomic_read() in wake_one_more(), otherwise we can race. -arca
45 */
46static __inline__ int waking_non_zero_interruptible(struct semaphore *sem,
47 struct task_struct *tsk)
48{
49 unsigned long flags;
50 int ret = 0;
51
52 spin_lock_irqsave(&semaphore_wake_lock, flags);
53 if (sem->sleepers > 0) {
54 sem->sleepers--;
55 ret = 1;
56 } else if (signal_pending(tsk)) {
57 atomic_inc(&sem->count);
58 ret = -EINTR;
59 }
60 spin_unlock_irqrestore(&semaphore_wake_lock, flags);
61 return ret;
62}
63
64/*
65 * waking_non_zero_trylock:
66 * 1 failed to lock
67 * 0 got the lock
68 *
69 * We must undo the sem->count down_trylock() increment while we are
70 * protected by the spinlock in order to make atomic this atomic_inc() with the
71 * atomic_read() in wake_one_more(), otherwise we can race. -arca
72 */
73static __inline__ int waking_non_zero_trylock(struct semaphore *sem)
74{
75 unsigned long flags;
76 int ret = 1;
77
78 spin_lock_irqsave(&semaphore_wake_lock, flags);
79 if (sem->sleepers <= 0)
80 atomic_inc(&sem->count);
81 else {
82 sem->sleepers--;
83 ret = 0;
84 }
85 spin_unlock_irqrestore(&semaphore_wake_lock, flags);
86 return ret;
87}
88
89#endif /* __ASM_SH_SEMAPHORE_HELPER_H */
diff --git a/include/asm-sh/semaphore.h b/include/asm-sh/semaphore.h
new file mode 100644
index 000000000000..b923a77a8a7e
--- /dev/null
+++ b/include/asm-sh/semaphore.h
@@ -0,0 +1,119 @@
1#ifndef __ASM_SH_SEMAPHORE_H
2#define __ASM_SH_SEMAPHORE_H
3
4#include <linux/linkage.h>
5
6#ifdef __KERNEL__
7/*
8 * SMP- and interrupt-safe semaphores.
9 *
10 * (C) Copyright 1996 Linus Torvalds
11 *
12 * SuperH verison by Niibe Yutaka
13 * (Currently no asm implementation but generic C code...)
14 */
15
16#include <linux/spinlock.h>
17#include <linux/rwsem.h>
18#include <linux/wait.h>
19
20#include <asm/system.h>
21#include <asm/atomic.h>
22
23struct semaphore {
24 atomic_t count;
25 int sleepers;
26 wait_queue_head_t wait;
27};
28
29#define __SEMAPHORE_INITIALIZER(name, n) \
30{ \
31 .count = ATOMIC_INIT(n), \
32 .sleepers = 0, \
33 .wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \
34}
35
36#define __MUTEX_INITIALIZER(name) \
37 __SEMAPHORE_INITIALIZER(name,1)
38
39#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
40 struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
41
42#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name,1)
43#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name,0)
44
45static inline void sema_init (struct semaphore *sem, int val)
46{
47/*
48 * *sem = (struct semaphore)__SEMAPHORE_INITIALIZER((*sem),val);
49 *
50 * i'd rather use the more flexible initialization above, but sadly
51 * GCC 2.7.2.3 emits a bogus warning. EGCS doesn't. Oh well.
52 */
53 atomic_set(&sem->count, val);
54 sem->sleepers = 0;
55 init_waitqueue_head(&sem->wait);
56}
57
58static inline void init_MUTEX (struct semaphore *sem)
59{
60 sema_init(sem, 1);
61}
62
63static inline void init_MUTEX_LOCKED (struct semaphore *sem)
64{
65 sema_init(sem, 0);
66}
67
68#if 0
69asmlinkage void __down_failed(void /* special register calling convention */);
70asmlinkage int __down_failed_interruptible(void /* params in registers */);
71asmlinkage int __down_failed_trylock(void /* params in registers */);
72asmlinkage void __up_wakeup(void /* special register calling convention */);
73#endif
74
75asmlinkage void __down(struct semaphore * sem);
76asmlinkage int __down_interruptible(struct semaphore * sem);
77asmlinkage int __down_trylock(struct semaphore * sem);
78asmlinkage void __up(struct semaphore * sem);
79
80extern spinlock_t semaphore_wake_lock;
81
82static inline void down(struct semaphore * sem)
83{
84 might_sleep();
85 if (atomic_dec_return(&sem->count) < 0)
86 __down(sem);
87}
88
89static inline int down_interruptible(struct semaphore * sem)
90{
91 int ret = 0;
92
93 might_sleep();
94 if (atomic_dec_return(&sem->count) < 0)
95 ret = __down_interruptible(sem);
96 return ret;
97}
98
99static inline int down_trylock(struct semaphore * sem)
100{
101 int ret = 0;
102
103 if (atomic_dec_return(&sem->count) < 0)
104 ret = __down_trylock(sem);
105 return ret;
106}
107
108/*
109 * Note! This is subtle. We jump to wake people up only if
110 * the semaphore was negative (== somebody was waiting on it).
111 */
112static inline void up(struct semaphore * sem)
113{
114 if (atomic_inc_return(&sem->count) <= 0)
115 __up(sem);
116}
117
118#endif
119#endif /* __ASM_SH_SEMAPHORE_H */
diff --git a/include/asm-sh/sembuf.h b/include/asm-sh/sembuf.h
new file mode 100644
index 000000000000..d79f3bd570b2
--- /dev/null
+++ b/include/asm-sh/sembuf.h
@@ -0,0 +1,25 @@
1#ifndef __ASM_SH_SEMBUF_H
2#define __ASM_SH_SEMBUF_H
3
4/*
5 * The semid64_ds structure for i386 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct semid64_ds {
15 struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
16 __kernel_time_t sem_otime; /* last semop time */
17 unsigned long __unused1;
18 __kernel_time_t sem_ctime; /* last change time */
19 unsigned long __unused2;
20 unsigned long sem_nsems; /* no. of semaphores in array */
21 unsigned long __unused3;
22 unsigned long __unused4;
23};
24
25#endif /* __ASM_SH_SEMBUF_H */
diff --git a/include/asm-sh/serial.h b/include/asm-sh/serial.h
new file mode 100644
index 000000000000..5474dbdbaa86
--- /dev/null
+++ b/include/asm-sh/serial.h
@@ -0,0 +1,48 @@
1/*
2 * include/asm-sh/serial.h
3 *
4 * Configuration details for 8250, 16450, 16550, etc. serial ports
5 */
6
7#ifndef _ASM_SERIAL_H
8#define _ASM_SERIAL_H
9
10#include <linux/config.h>
11#include <linux/kernel.h>
12
13#ifdef CONFIG_SH_EC3104
14#include <asm/serial-ec3104.h>
15#elif defined (CONFIG_SH_BIGSUR)
16#include <asm/serial-bigsur.h>
17#else
18/*
19 * This assumes you have a 1.8432 MHz clock for your UART.
20 *
21 * It'd be nice if someone built a serial card with a 24.576 MHz
22 * clock, since the 16550A is capable of handling a top speed of 1.5
23 * megabits/second; but this requires the faster clock.
24 */
25#define BASE_BAUD ( 1843200 / 16 )
26
27#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
28
29#ifdef CONFIG_HD64465
30#include <asm/hd64465.h>
31
32#define STD_SERIAL_PORT_DEFNS \
33 /* UART CLK PORT IRQ FLAGS */ \
34 { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */
35
36#else
37
38#define STD_SERIAL_PORT_DEFNS \
39 /* UART CLK PORT IRQ FLAGS */ \
40 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
41 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS } /* ttyS1 */
42
43#endif
44
45#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS
46
47#endif
48#endif /* _ASM_SERIAL_H */
diff --git a/include/asm-sh/setup.h b/include/asm-sh/setup.h
new file mode 100644
index 000000000000..d19de7c8df4e
--- /dev/null
+++ b/include/asm-sh/setup.h
@@ -0,0 +1,8 @@
1#ifdef __KERNEL__
2#ifndef _SH_SETUP_H
3#define _SH_SETUP_H
4
5#define COMMAND_LINE_SIZE 256
6
7#endif /* _SH_SETUP_H */
8#endif /* __KERNEL__ */
diff --git a/include/asm-sh/sh03/ide.h b/include/asm-sh/sh03/ide.h
new file mode 100644
index 000000000000..73ee92e5c79e
--- /dev/null
+++ b/include/asm-sh/sh03/ide.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_SH_SH03_IDE_H
2#define __ASM_SH_SH03_IDE_H
3
4#define IRQ_CFCARD 8
5#define IRQ_PCMCIA 8
6
7#endif /* __ASM_SH_SH03_IDE_H */
diff --git a/include/asm-sh/sh03/io.h b/include/asm-sh/sh03/io.h
new file mode 100644
index 000000000000..25792e9831ea
--- /dev/null
+++ b/include/asm-sh/sh03/io.h
@@ -0,0 +1,46 @@
1/*
2 * include/asm-sh/sh03/io.h
3 *
4 * Copyright 2004 Interface Co.,Ltd. Saito.K
5 *
6 * IO functions for an Interface CTP/PCI-SH03
7 */
8
9#ifndef _ASM_SH_IO_SH03_H
10#define _ASM_SH_IO_SH03_H
11
12#include <linux/time.h>
13
14#define INTC_IPRD 0xffd00010UL
15
16#define IRL0_IRQ 2
17#define IRL0_IPR_ADDR INTC_IPRD
18#define IRL0_IPR_POS 3
19#define IRL0_PRIORITY 13
20
21#define IRL1_IRQ 5
22#define IRL1_IPR_ADDR INTC_IPRD
23#define IRL1_IPR_POS 2
24#define IRL1_PRIORITY 10
25
26#define IRL2_IRQ 8
27#define IRL2_IPR_ADDR INTC_IPRD
28#define IRL2_IPR_POS 1
29#define IRL2_PRIORITY 7
30
31#define IRL3_IRQ 11
32#define IRL3_IPR_ADDR INTC_IPRD
33#define IRL3_IPR_POS 0
34#define IRL3_PRIORITY 4
35
36
37extern unsigned long sh03_isa_port2addr(unsigned long offset);
38
39extern void setup_sh03(void);
40extern void init_sh03_IRQ(void);
41extern void heartbeat_sh03(void);
42
43extern void sh03_rtc_gettimeofday(struct timeval *tv);
44extern int sh03_rtc_settimeofday(const struct timeval *tv);
45
46#endif /* _ASM_SH_IO_SH03_H */
diff --git a/include/asm-sh/sh03/sh03.h b/include/asm-sh/sh03/sh03.h
new file mode 100644
index 000000000000..19c40b80428d
--- /dev/null
+++ b/include/asm-sh/sh03/sh03.h
@@ -0,0 +1,18 @@
1#ifndef __ASM_SH_SH03_H
2#define __ASM_SH_SH03_H
3
4/*
5 * linux/include/asm-sh/sh03/sh03.h
6 *
7 * Copyright (C) 2004 Interface Co., Ltd. Saito.K
8 *
9 * Interface CTP/PCI-SH03 support
10 */
11
12#define PA_PCI_IO (0xbe240000) /* PCI I/O space */
13#define PA_PCI_MEM (0xbd000000) /* PCI MEM space */
14
15#define PCIPAR (0xa4000cf8) /* PCI Config address */
16#define PCIPDR (0xa4000cfc) /* PCI Config data */
17
18#endif /* __ASM_SH_SH03_H */
diff --git a/include/asm-sh/sh2000/sh2000.h b/include/asm-sh/sh2000/sh2000.h
new file mode 100644
index 000000000000..8d547324d59a
--- /dev/null
+++ b/include/asm-sh/sh2000/sh2000.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_SH_SH2000_SH2000_H
2#define __ASM_SH_SH2000_SH2000_H
3
4/* arch/sh/boards/sh2000/setup.c */
5extern int setup_sh2000(void);
6
7#endif /* __ASM_SH_SH2000_SH2000_H */
8
diff --git a/include/asm-sh/sh_bios.h b/include/asm-sh/sh_bios.h
new file mode 100644
index 000000000000..0ca261956e3d
--- /dev/null
+++ b/include/asm-sh/sh_bios.h
@@ -0,0 +1,19 @@
1#ifndef __ASM_SH_BIOS_H
2#define __ASM_SH_BIOS_H
3
4/*
5 * Copyright (C) 2000 Greg Banks, Mitch Davis
6 * C API to interface to the standard LinuxSH BIOS
7 * usually from within the early stages of kernel boot.
8 */
9
10
11extern void sh_bios_console_write(const char *buf, unsigned int len);
12extern void sh_bios_char_out(char ch);
13extern int sh_bios_in_gdb_mode(void);
14extern void sh_bios_gdb_detach(void);
15
16extern void sh_bios_get_node_addr(unsigned char *node_addr);
17extern void sh_bios_shutdown(unsigned int how);
18
19#endif /* __ASM_SH_BIOS_H */
diff --git a/include/asm-sh/shmbuf.h b/include/asm-sh/shmbuf.h
new file mode 100644
index 000000000000..b2101f490521
--- /dev/null
+++ b/include/asm-sh/shmbuf.h
@@ -0,0 +1,42 @@
1#ifndef __ASM_SH_SHMBUF_H
2#define __ASM_SH_SHMBUF_H
3
4/*
5 * The shmid64_ds structure for i386 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct shmid64_ds {
15 struct ipc64_perm shm_perm; /* operation perms */
16 size_t shm_segsz; /* size of segment (bytes) */
17 __kernel_time_t shm_atime; /* last attach time */
18 unsigned long __unused1;
19 __kernel_time_t shm_dtime; /* last detach time */
20 unsigned long __unused2;
21 __kernel_time_t shm_ctime; /* last change time */
22 unsigned long __unused3;
23 __kernel_pid_t shm_cpid; /* pid of creator */
24 __kernel_pid_t shm_lpid; /* pid of last operator */
25 unsigned long shm_nattch; /* no. of current attaches */
26 unsigned long __unused4;
27 unsigned long __unused5;
28};
29
30struct shminfo64 {
31 unsigned long shmmax;
32 unsigned long shmmin;
33 unsigned long shmmni;
34 unsigned long shmseg;
35 unsigned long shmall;
36 unsigned long __unused1;
37 unsigned long __unused2;
38 unsigned long __unused3;
39 unsigned long __unused4;
40};
41
42#endif /* __ASM_SH_SHMBUF_H */
diff --git a/include/asm-sh/shmparam.h b/include/asm-sh/shmparam.h
new file mode 100644
index 000000000000..0a95604b9b66
--- /dev/null
+++ b/include/asm-sh/shmparam.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_SH_SHMPARAM_H
2#define __ASM_SH_SHMPARAM_H
3#ifdef __KERNEL__
4
5#include <asm/cpu/shmparam.h>
6
7#endif /* __KERNEL__ */
8#endif /* __ASM_SH_SHMPARAM_H */
diff --git a/include/asm-sh/sigcontext.h b/include/asm-sh/sigcontext.h
new file mode 100644
index 000000000000..eb8effba2e80
--- /dev/null
+++ b/include/asm-sh/sigcontext.h
@@ -0,0 +1,26 @@
1#ifndef __ASM_SH_SIGCONTEXT_H
2#define __ASM_SH_SIGCONTEXT_H
3
4struct sigcontext {
5 unsigned long oldmask;
6
7 /* CPU registers */
8 unsigned long sc_regs[16];
9 unsigned long sc_pc;
10 unsigned long sc_pr;
11 unsigned long sc_sr;
12 unsigned long sc_gbr;
13 unsigned long sc_mach;
14 unsigned long sc_macl;
15
16#if defined(__SH4__) || defined(CONFIG_CPU_SH4)
17 /* FPU registers */
18 unsigned long sc_fpregs[16];
19 unsigned long sc_xfpregs[16];
20 unsigned int sc_fpscr;
21 unsigned int sc_fpul;
22 unsigned int sc_ownedfp;
23#endif
24};
25
26#endif /* __ASM_SH_SIGCONTEXT_H */
diff --git a/include/asm-sh/siginfo.h b/include/asm-sh/siginfo.h
new file mode 100644
index 000000000000..813040ed68a9
--- /dev/null
+++ b/include/asm-sh/siginfo.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_SH_SIGINFO_H
2#define __ASM_SH_SIGINFO_H
3
4#include <asm-generic/siginfo.h>
5
6#endif /* __ASM_SH_SIGINFO_H */
diff --git a/include/asm-sh/signal.h b/include/asm-sh/signal.h
new file mode 100644
index 000000000000..0a7ff717c245
--- /dev/null
+++ b/include/asm-sh/signal.h
@@ -0,0 +1,185 @@
1#ifndef __ASM_SH_SIGNAL_H
2#define __ASM_SH_SIGNAL_H
3
4#include <linux/types.h>
5
6/* Avoid too many header ordering problems. */
7struct pt_regs;
8struct siginfo;
9
10#ifdef __KERNEL__
11/* Most things should be clean enough to redefine this at will, if care
12 is taken to make libc match. */
13
14#define _NSIG 64
15#define _NSIG_BPW 32
16#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
17
18typedef unsigned long old_sigset_t; /* at least 32 bits */
19
20typedef struct {
21 unsigned long sig[_NSIG_WORDS];
22} sigset_t;
23
24#else
25/* Here we must cater to libcs that poke about in kernel headers. */
26
27#define NSIG 32
28typedef unsigned long sigset_t;
29
30#endif /* __KERNEL__ */
31
32#define SIGHUP 1
33#define SIGINT 2
34#define SIGQUIT 3
35#define SIGILL 4
36#define SIGTRAP 5
37#define SIGABRT 6
38#define SIGIOT 6
39#define SIGBUS 7
40#define SIGFPE 8
41#define SIGKILL 9
42#define SIGUSR1 10
43#define SIGSEGV 11
44#define SIGUSR2 12
45#define SIGPIPE 13
46#define SIGALRM 14
47#define SIGTERM 15
48#define SIGSTKFLT 16
49#define SIGCHLD 17
50#define SIGCONT 18
51#define SIGSTOP 19
52#define SIGTSTP 20
53#define SIGTTIN 21
54#define SIGTTOU 22
55#define SIGURG 23
56#define SIGXCPU 24
57#define SIGXFSZ 25
58#define SIGVTALRM 26
59#define SIGPROF 27
60#define SIGWINCH 28
61#define SIGIO 29
62#define SIGPOLL SIGIO
63/*
64#define SIGLOST 29
65*/
66#define SIGPWR 30
67#define SIGSYS 31
68#define SIGUNUSED 31
69
70/* These should not be considered constants from userland. */
71#define SIGRTMIN 32
72#define SIGRTMAX _NSIG
73
74/*
75 * SA_FLAGS values:
76 *
77 * SA_ONSTACK indicates that a registered stack_t will be used.
78 * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the
79 * SA_RESTART flag to get restarting signals (which were the default long ago)
80 * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
81 * SA_RESETHAND clears the handler when the signal is delivered.
82 * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
83 * SA_NODEFER prevents the current signal from being masked in the handler.
84 *
85 * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
86 * Unix names RESETHAND and NODEFER respectively.
87 */
88#define SA_NOCLDSTOP 0x00000001
89#define SA_NOCLDWAIT 0x00000002
90#define SA_SIGINFO 0x00000004
91#define SA_ONSTACK 0x08000000
92#define SA_RESTART 0x10000000
93#define SA_NODEFER 0x40000000
94#define SA_RESETHAND 0x80000000
95
96#define SA_NOMASK SA_NODEFER
97#define SA_ONESHOT SA_RESETHAND
98#define SA_INTERRUPT 0x20000000 /* dummy -- ignored */
99
100#define SA_RESTORER 0x04000000
101
102/*
103 * sigaltstack controls
104 */
105#define SS_ONSTACK 1
106#define SS_DISABLE 2
107
108#define MINSIGSTKSZ 2048
109#define SIGSTKSZ 8192
110
111#ifdef __KERNEL__
112
113/*
114 * These values of sa_flags are used only by the kernel as part of the
115 * irq handling routines.
116 *
117 * SA_INTERRUPT is also used by the irq handling routines.
118 * SA_SHIRQ is for shared interrupt support on PCI and EISA.
119 */
120#define SA_PROBE SA_ONESHOT
121#define SA_SAMPLE_RANDOM SA_RESTART
122#define SA_SHIRQ 0x04000000
123#endif
124
125#define SIG_BLOCK 0 /* for blocking signals */
126#define SIG_UNBLOCK 1 /* for unblocking signals */
127#define SIG_SETMASK 2 /* for setting the signal mask */
128
129/* Type of a signal handler. */
130typedef void (*__sighandler_t)(int);
131
132#define SIG_DFL ((__sighandler_t)0) /* default signal handling */
133#define SIG_IGN ((__sighandler_t)1) /* ignore signal */
134#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */
135
136#ifdef __KERNEL__
137struct old_sigaction {
138 __sighandler_t sa_handler;
139 old_sigset_t sa_mask;
140 unsigned long sa_flags;
141 void (*sa_restorer)(void);
142};
143
144struct sigaction {
145 __sighandler_t sa_handler;
146 unsigned long sa_flags;
147 void (*sa_restorer)(void);
148 sigset_t sa_mask; /* mask last for extensibility */
149};
150
151struct k_sigaction {
152 struct sigaction sa;
153};
154#else
155/* Here we must cater to libcs that poke about in kernel headers. */
156
157struct sigaction {
158 union {
159 __sighandler_t _sa_handler;
160 void (*_sa_sigaction)(int, struct siginfo *, void *);
161 } _u;
162 sigset_t sa_mask;
163 unsigned long sa_flags;
164 void (*sa_restorer)(void);
165};
166
167#define sa_handler _u._sa_handler
168#define sa_sigaction _u._sa_sigaction
169
170#endif /* __KERNEL__ */
171
172typedef struct sigaltstack {
173 void *ss_sp;
174 int ss_flags;
175 size_t ss_size;
176} stack_t;
177
178#ifdef __KERNEL__
179#include <asm/sigcontext.h>
180
181#define ptrace_signal_deliver(regs, cookie) do { } while (0)
182
183#endif /* __KERNEL__ */
184
185#endif /* __ASM_SH_SIGNAL_H */
diff --git a/include/asm-sh/smp.h b/include/asm-sh/smp.h
new file mode 100644
index 000000000000..38b54469d7d1
--- /dev/null
+++ b/include/asm-sh/smp.h
@@ -0,0 +1,48 @@
1/*
2 * include/asm-sh/smp.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive for
8 * more details.
9 */
10#ifndef __ASM_SH_SMP_H
11#define __ASM_SH_SMP_H
12
13#include <linux/config.h>
14#include <linux/bitops.h>
15#include <linux/cpumask.h>
16
17#ifdef CONFIG_SMP
18
19#include <asm/spinlock.h>
20#include <asm/atomic.h>
21#include <asm/current.h>
22
23extern cpumask_t cpu_online_map;
24extern cpumask_t cpu_possible_map;
25
26#define cpu_online(cpu) cpu_isset(cpu, cpu_online_map)
27
28#define smp_processor_id() (current_thread_info()->cpu)
29
30/* I've no idea what the real meaning of this is */
31#define PROC_CHANGE_PENALTY 20
32
33#define NO_PROC_ID (-1)
34
35struct smp_fn_call_struct {
36 spinlock_t lock;
37 atomic_t finished;
38 void (*fn)(void *);
39 void *data;
40};
41
42extern struct smp_fn_call_struct smp_fn_call;
43
44#define SMP_MSG_RESCHEDULE 0x0001
45
46#endif /* CONFIG_SMP */
47
48#endif /* __ASM_SH_SMP_H */
diff --git a/include/asm-sh/snapgear/io.h b/include/asm-sh/snapgear/io.h
new file mode 100644
index 000000000000..bfa97ac06280
--- /dev/null
+++ b/include/asm-sh/snapgear/io.h
@@ -0,0 +1,92 @@
1/*
2 * include/asm-sh/snapgear/io.h
3 *
4 * Modified version of io_se.h for the snapgear-specific functions.
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * IO functions for a SnapGear
10 */
11
12#ifndef _ASM_SH_IO_SNAPGEAR_H
13#define _ASM_SH_IO_SNAPGEAR_H
14
15#if defined(CONFIG_CPU_SH4)
16/*
17 * The external interrupt lines, these take up ints 0 - 15 inclusive
18 * depending on the priority for the interrupt. In fact the priority
19 * is the interrupt :-)
20 */
21
22#define IRL0_IRQ 2
23#define IRL0_IPR_ADDR INTC_IPRD
24#define IRL0_IPR_POS 3
25#define IRL0_PRIORITY 13
26
27#define IRL1_IRQ 5
28#define IRL1_IPR_ADDR INTC_IPRD
29#define IRL1_IPR_POS 2
30#define IRL1_PRIORITY 10
31
32#define IRL2_IRQ 8
33#define IRL2_IPR_ADDR INTC_IPRD
34#define IRL2_IPR_POS 1
35#define IRL2_PRIORITY 7
36
37#define IRL3_IRQ 11
38#define IRL3_IPR_ADDR INTC_IPRD
39#define IRL3_IPR_POS 0
40#define IRL3_PRIORITY 4
41#endif
42
43extern unsigned char snapgear_inb(unsigned long port);
44extern unsigned short snapgear_inw(unsigned long port);
45extern unsigned int snapgear_inl(unsigned long port);
46
47extern void snapgear_outb(unsigned char value, unsigned long port);
48extern void snapgear_outw(unsigned short value, unsigned long port);
49extern void snapgear_outl(unsigned int value, unsigned long port);
50
51extern unsigned char snapgear_inb_p(unsigned long port);
52extern void snapgear_outb_p(unsigned char value, unsigned long port);
53
54extern void snapgear_insl(unsigned long port, void *addr, unsigned long count);
55extern void snapgear_outsl(unsigned long port, const void *addr, unsigned long count);
56
57extern unsigned long snapgear_isa_port2addr(unsigned long offset);
58
59#ifdef CONFIG_SH_SECUREEDGE5410
60/*
61 * We need to remember what was written to the ioport as some bits
62 * are shared with other functions and you cannot read back what was
63 * written :-|
64 *
65 * Bit Read Write
66 * -----------------------------------------------
67 * D0 DCD on ttySC1 power
68 * D1 Reset Switch heatbeat
69 * D2 ttySC0 CTS (7100) LAN
70 * D3 - WAN
71 * D4 ttySC0 DCD (7100) CONSOLE
72 * D5 - ONLINE
73 * D6 - VPN
74 * D7 - DTR on ttySC1
75 * D8 - ttySC0 RTS (7100)
76 * D9 - ttySC0 DTR (7100)
77 * D10 - RTC SCLK
78 * D11 RTC DATA RTC DATA
79 * D12 - RTS RESET
80 */
81
82 #define SECUREEDGE_IOPORT_ADDR ((volatile short *) 0xb0000000)
83 extern unsigned short secureedge5410_ioport;
84
85 #define SECUREEDGE_WRITE_IOPORT(val, mask) (*SECUREEDGE_IOPORT_ADDR = \
86 (secureedge5410_ioport = \
87 ((secureedge5410_ioport & ~(mask)) | ((val) & (mask)))))
88 #define SECUREEDGE_READ_IOPORT() \
89 ((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817))
90#endif
91
92#endif /* _ASM_SH_IO_SNAPGEAR_H */
diff --git a/include/asm-sh/socket.h b/include/asm-sh/socket.h
new file mode 100644
index 000000000000..dde696c3b4c7
--- /dev/null
+++ b/include/asm-sh/socket.h
@@ -0,0 +1,50 @@
1#ifndef __ASM_SH_SOCKET_H
2#define __ASM_SH_SOCKET_H
3
4#include <asm/sockios.h>
5
6/* For setsockopt(2) */
7#define SOL_SOCKET 1
8
9#define SO_DEBUG 1
10#define SO_REUSEADDR 2
11#define SO_TYPE 3
12#define SO_ERROR 4
13#define SO_DONTROUTE 5
14#define SO_BROADCAST 6
15#define SO_SNDBUF 7
16#define SO_RCVBUF 8
17#define SO_KEEPALIVE 9
18#define SO_OOBINLINE 10
19#define SO_NO_CHECK 11
20#define SO_PRIORITY 12
21#define SO_LINGER 13
22#define SO_BSDCOMPAT 14
23/* To add :#define SO_REUSEPORT 15 */
24#define SO_PASSCRED 16
25#define SO_PEERCRED 17
26#define SO_RCVLOWAT 18
27#define SO_SNDLOWAT 19
28#define SO_RCVTIMEO 20
29#define SO_SNDTIMEO 21
30
31/* Security levels - as per NRL IPv6 - don't actually do anything */
32#define SO_SECURITY_AUTHENTICATION 22
33#define SO_SECURITY_ENCRYPTION_TRANSPORT 23
34#define SO_SECURITY_ENCRYPTION_NETWORK 24
35
36#define SO_BINDTODEVICE 25
37
38/* Socket filtering */
39#define SO_ATTACH_FILTER 26
40#define SO_DETACH_FILTER 27
41
42#define SO_PEERNAME 28
43#define SO_TIMESTAMP 29
44#define SCM_TIMESTAMP SO_TIMESTAMP
45
46#define SO_ACCEPTCONN 30
47
48#define SO_PEERSEC 31
49
50#endif /* __ASM_SH_SOCKET_H */
diff --git a/include/asm-sh/sockios.h b/include/asm-sh/sockios.h
new file mode 100644
index 000000000000..08a71df8a8be
--- /dev/null
+++ b/include/asm-sh/sockios.h
@@ -0,0 +1,13 @@
1#ifndef __ASM_SH_SOCKIOS_H
2#define __ASM_SH_SOCKIOS_H
3
4/* Socket-level I/O control calls. */
5#define FIOGETOWN _IOR('f', 123, int)
6#define FIOSETOWN _IOW('f', 124, int)
7
8#define SIOCATMARK _IOR('s', 7, int)
9#define SIOCSPGRP _IOW('s', 8, pid_t)
10#define SIOCGPGRP _IOR('s', 9, pid_t)
11
12#define SIOCGSTAMP _IOR('s', 100, struct timeval) /* Get stamp - linux-specific */
13#endif /* __ASM_SH_SOCKIOS_H */
diff --git a/include/asm-sh/spinlock.h b/include/asm-sh/spinlock.h
new file mode 100644
index 000000000000..e770b55649eb
--- /dev/null
+++ b/include/asm-sh/spinlock.h
@@ -0,0 +1,124 @@
1/*
2 * include/asm-sh/spinlock.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_SH_SPINLOCK_H
11#define __ASM_SH_SPINLOCK_H
12
13#include <asm/atomic.h>
14
15/*
16 * Your basic SMP spinlocks, allowing only a single CPU anywhere
17 */
18typedef struct {
19 volatile unsigned long lock;
20#ifdef CONFIG_PREEMPT
21 unsigned int break_lock;
22#endif
23} spinlock_t;
24
25#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 }
26
27#define spin_lock_init(x) do { *(x) = SPIN_LOCK_UNLOCKED; } while(0)
28
29#define spin_is_locked(x) ((x)->lock != 0)
30#define spin_unlock_wait(x) do { barrier(); } while (spin_is_locked(x))
31#define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
32
33/*
34 * Simple spin lock operations. There are two variants, one clears IRQ's
35 * on the local processor, one does not.
36 *
37 * We make no fairness assumptions. They have a cost.
38 */
39static inline void _raw_spin_lock(spinlock_t *lock)
40{
41 __asm__ __volatile__ (
42 "1:\n\t"
43 "tas.b @%0\n\t"
44 "bf/s 1b\n\t"
45 "nop\n\t"
46 : "=r" (lock->lock)
47 : "r" (&lock->lock)
48 : "t", "memory"
49 );
50}
51
52static inline void _raw_spin_unlock(spinlock_t *lock)
53{
54 assert_spin_locked(lock);
55
56 lock->lock = 0;
57}
58
59#define _raw_spin_trylock(x) (!test_and_set_bit(0, &(x)->lock))
60
61/*
62 * Read-write spinlocks, allowing multiple readers but only one writer.
63 *
64 * NOTE! it is quite common to have readers in interrupts but no interrupt
65 * writers. For those circumstances we can "mix" irq-safe locks - any writer
66 * needs to get a irq-safe write-lock, but readers can get non-irqsafe
67 * read-locks.
68 */
69typedef struct {
70 spinlock_t lock;
71 atomic_t counter;
72#ifdef CONFIG_PREEMPT
73 unsigned int break_lock;
74#endif
75} rwlock_t;
76
77#define RW_LOCK_BIAS 0x01000000
78#define RW_LOCK_UNLOCKED (rwlock_t) { { 0 }, { RW_LOCK_BIAS } }
79#define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while (0)
80
81static inline void _raw_read_lock(rwlock_t *rw)
82{
83 _raw_spin_lock(&rw->lock);
84
85 atomic_inc(&rw->counter);
86
87 _raw_spin_unlock(&rw->lock);
88}
89
90static inline void _raw_read_unlock(rwlock_t *rw)
91{
92 _raw_spin_lock(&rw->lock);
93
94 atomic_dec(&rw->counter);
95
96 _raw_spin_unlock(&rw->lock);
97}
98
99static inline void _raw_write_lock(rwlock_t *rw)
100{
101 _raw_spin_lock(&rw->lock);
102 atomic_set(&rw->counter, -1);
103}
104
105static inline void _raw_write_unlock(rwlock_t *rw)
106{
107 atomic_set(&rw->counter, 0);
108 _raw_spin_unlock(&rw->lock);
109}
110
111#define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
112
113static inline int _raw_write_trylock(rwlock_t *rw)
114{
115 if (atomic_sub_and_test(RW_LOCK_BIAS, &rw->counter))
116 return 1;
117
118 atomic_add(RW_LOCK_BIAS, &rw->counter);
119
120 return 0;
121}
122
123#endif /* __ASM_SH_SPINLOCK_H */
124
diff --git a/include/asm-sh/stat.h b/include/asm-sh/stat.h
new file mode 100644
index 000000000000..914e3fcbbd37
--- /dev/null
+++ b/include/asm-sh/stat.h
@@ -0,0 +1,84 @@
1#ifndef __ASM_SH_STAT_H
2#define __ASM_SH_STAT_H
3
4struct __old_kernel_stat {
5 unsigned short st_dev;
6 unsigned short st_ino;
7 unsigned short st_mode;
8 unsigned short st_nlink;
9 unsigned short st_uid;
10 unsigned short st_gid;
11 unsigned short st_rdev;
12 unsigned long st_size;
13 unsigned long st_atime;
14 unsigned long st_mtime;
15 unsigned long st_ctime;
16};
17
18struct stat {
19 unsigned short st_dev;
20 unsigned short __pad1;
21 unsigned long st_ino;
22 unsigned short st_mode;
23 unsigned short st_nlink;
24 unsigned short st_uid;
25 unsigned short st_gid;
26 unsigned short st_rdev;
27 unsigned short __pad2;
28 unsigned long st_size;
29 unsigned long st_blksize;
30 unsigned long st_blocks;
31 unsigned long st_atime;
32 unsigned long st_atime_nsec;
33 unsigned long st_mtime;
34 unsigned long st_mtime_nsec;
35 unsigned long st_ctime;
36 unsigned long st_ctime_nsec;
37 unsigned long __unused4;
38 unsigned long __unused5;
39};
40
41#define STAT_HAVE_NSEC 1
42
43/* This matches struct stat64 in glibc2.1, hence the absolutely
44 * insane amounts of padding around dev_t's.
45 */
46struct stat64 {
47 unsigned long long st_dev;
48 unsigned char __pad0[4];
49
50 unsigned long st_ino;
51 unsigned int st_mode;
52 unsigned int st_nlink;
53
54 unsigned long st_uid;
55 unsigned long st_gid;
56
57 unsigned long long st_rdev;
58 unsigned char __pad3[4];
59
60 long long st_size;
61 unsigned long st_blksize;
62
63#if defined(__BIG_ENDIAN__)
64 unsigned long __pad4; /* Future possible st_blocks hi bits */
65 unsigned long st_blocks; /* Number 512-byte blocks allocated. */
66#else /* Must be little */
67 unsigned long st_blocks; /* Number 512-byte blocks allocated. */
68 unsigned long __pad4; /* Future possible st_blocks hi bits */
69#endif
70
71 unsigned long st_atime;
72 unsigned long st_atime_nsec;
73
74 unsigned long st_mtime;
75 unsigned long st_mtime_nsec;
76
77 unsigned long st_ctime;
78 unsigned long st_ctime_nsec;
79
80 unsigned long __unused1;
81 unsigned long __unused2;
82};
83
84#endif /* __ASM_SH_STAT_H */
diff --git a/include/asm-sh/statfs.h b/include/asm-sh/statfs.h
new file mode 100644
index 000000000000..9202a023328f
--- /dev/null
+++ b/include/asm-sh/statfs.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_SH_STATFS_H
2#define __ASM_SH_STATFS_H
3
4#include <asm-generic/statfs.h>
5
6#endif /* __ASM_SH_STATFS_H */
diff --git a/include/asm-sh/string.h b/include/asm-sh/string.h
new file mode 100644
index 000000000000..3e0cff04caec
--- /dev/null
+++ b/include/asm-sh/string.h
@@ -0,0 +1,127 @@
1#ifndef __ASM_SH_STRING_H
2#define __ASM_SH_STRING_H
3
4/*
5 * Copyright (C) 1999 Niibe Yutaka
6 * But consider these trivial functions to be public domain.
7 */
8
9#define __HAVE_ARCH_STRCPY
10static __inline__ char *strcpy(char *__dest, const char *__src)
11{
12 register char *__xdest = __dest;
13 unsigned long __dummy;
14
15 __asm__ __volatile__("1:\n\t"
16 "mov.b @%1+, %2\n\t"
17 "mov.b %2, @%0\n\t"
18 "cmp/eq #0, %2\n\t"
19 "bf/s 1b\n\t"
20 " add #1, %0\n\t"
21 : "=r" (__dest), "=r" (__src), "=&z" (__dummy)
22 : "0" (__dest), "1" (__src)
23 : "memory", "t");
24
25 return __xdest;
26}
27
28#define __HAVE_ARCH_STRNCPY
29static __inline__ char *strncpy(char *__dest, const char *__src, size_t __n)
30{
31 register char *__xdest = __dest;
32 unsigned long __dummy;
33
34 if (__n == 0)
35 return __xdest;
36
37 __asm__ __volatile__(
38 "1:\n"
39 "mov.b @%1+, %2\n\t"
40 "mov.b %2, @%0\n\t"
41 "cmp/eq #0, %2\n\t"
42 "bt/s 2f\n\t"
43 " cmp/eq %5,%1\n\t"
44 "bf/s 1b\n\t"
45 " add #1, %0\n"
46 "2:"
47 : "=r" (__dest), "=r" (__src), "=&z" (__dummy)
48 : "0" (__dest), "1" (__src), "r" (__src+__n)
49 : "memory", "t");
50
51 return __xdest;
52}
53
54#define __HAVE_ARCH_STRCMP
55static __inline__ int strcmp(const char *__cs, const char *__ct)
56{
57 register int __res;
58 unsigned long __dummy;
59
60 __asm__ __volatile__(
61 "mov.b @%1+, %3\n"
62 "1:\n\t"
63 "mov.b @%0+, %2\n\t"
64 "cmp/eq #0, %3\n\t"
65 "bt 2f\n\t"
66 "cmp/eq %2, %3\n\t"
67 "bt/s 1b\n\t"
68 " mov.b @%1+, %3\n\t"
69 "add #-2, %1\n\t"
70 "mov.b @%1, %3\n\t"
71 "sub %3, %2\n"
72 "2:"
73 : "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy)
74 : "0" (__cs), "1" (__ct)
75 : "t");
76
77 return __res;
78}
79
80#define __HAVE_ARCH_STRNCMP
81static __inline__ int strncmp(const char *__cs, const char *__ct, size_t __n)
82{
83 register int __res;
84 unsigned long __dummy;
85
86 if (__n == 0)
87 return 0;
88
89 __asm__ __volatile__(
90 "mov.b @%1+, %3\n"
91 "1:\n\t"
92 "mov.b @%0+, %2\n\t"
93 "cmp/eq %6, %0\n\t"
94 "bt/s 2f\n\t"
95 " cmp/eq #0, %3\n\t"
96 "bt/s 3f\n\t"
97 " cmp/eq %3, %2\n\t"
98 "bt/s 1b\n\t"
99 " mov.b @%1+, %3\n\t"
100 "add #-2, %1\n\t"
101 "mov.b @%1, %3\n"
102 "2:\n\t"
103 "sub %3, %2\n"
104 "3:"
105 :"=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy)
106 : "0" (__cs), "1" (__ct), "r" (__cs+__n)
107 : "t");
108
109 return __res;
110}
111
112#define __HAVE_ARCH_MEMSET
113extern void *memset(void *__s, int __c, size_t __count);
114
115#define __HAVE_ARCH_MEMCPY
116extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
117
118#define __HAVE_ARCH_MEMMOVE
119extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
120
121#define __HAVE_ARCH_MEMCHR
122extern void *memchr(const void *__s, int __c, size_t __n);
123
124#define __HAVE_ARCH_STRLEN
125extern size_t strlen(const char *);
126
127#endif /* __ASM_SH_STRING_H */
diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h
new file mode 100644
index 000000000000..28a3c2d8bcd7
--- /dev/null
+++ b/include/asm-sh/system.h
@@ -0,0 +1,264 @@
1#ifndef __ASM_SH_SYSTEM_H
2#define __ASM_SH_SYSTEM_H
3
4/*
5 * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
6 * Copyright (C) 2002 Paul Mundt
7 */
8
9#include <linux/config.h>
10
11/*
12 * switch_to() should switch tasks to task nr n, first
13 */
14
15#define switch_to(prev, next, last) do { \
16 task_t *__last; \
17 register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp; \
18 register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc; \
19 register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev; \
20 register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next; \
21 register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \
22 register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \
23 __asm__ __volatile__ (".balign 4\n\t" \
24 "stc.l gbr, @-r15\n\t" \
25 "sts.l pr, @-r15\n\t" \
26 "mov.l r8, @-r15\n\t" \
27 "mov.l r9, @-r15\n\t" \
28 "mov.l r10, @-r15\n\t" \
29 "mov.l r11, @-r15\n\t" \
30 "mov.l r12, @-r15\n\t" \
31 "mov.l r13, @-r15\n\t" \
32 "mov.l r14, @-r15\n\t" \
33 "mov.l r15, @r1 ! save SP\n\t" \
34 "mov.l @r6, r15 ! change to new stack\n\t" \
35 "mova 1f, %0\n\t" \
36 "mov.l %0, @r2 ! save PC\n\t" \
37 "mov.l 2f, %0\n\t" \
38 "jmp @%0 ! call __switch_to\n\t" \
39 " lds r7, pr ! with return to new PC\n\t" \
40 ".balign 4\n" \
41 "2:\n\t" \
42 ".long __switch_to\n" \
43 "1:\n\t" \
44 "mov.l @r15+, r14\n\t" \
45 "mov.l @r15+, r13\n\t" \
46 "mov.l @r15+, r12\n\t" \
47 "mov.l @r15+, r11\n\t" \
48 "mov.l @r15+, r10\n\t" \
49 "mov.l @r15+, r9\n\t" \
50 "mov.l @r15+, r8\n\t" \
51 "lds.l @r15+, pr\n\t" \
52 "ldc.l @r15+, gbr\n\t" \
53 : "=z" (__last) \
54 : "r" (__ts1), "r" (__ts2), "r" (__ts4), \
55 "r" (__ts5), "r" (__ts6), "r" (__ts7) \
56 : "r3", "t"); \
57 last = __last; \
58} while (0)
59
60#define nop() __asm__ __volatile__ ("nop")
61
62
63#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
64
65static __inline__ unsigned long tas(volatile int *m)
66{ /* #define tas(ptr) (xchg((ptr),1)) */
67 unsigned long retval;
68
69 __asm__ __volatile__ ("tas.b @%1\n\t"
70 "movt %0"
71 : "=r" (retval): "r" (m): "t", "memory");
72 return retval;
73}
74
75extern void __xchg_called_with_bad_pointer(void);
76
77#define mb() __asm__ __volatile__ ("": : :"memory")
78#define rmb() mb()
79#define wmb() __asm__ __volatile__ ("": : :"memory")
80#define read_barrier_depends() do { } while(0)
81
82#ifdef CONFIG_SMP
83#define smp_mb() mb()
84#define smp_rmb() rmb()
85#define smp_wmb() wmb()
86#define smp_read_barrier_depends() read_barrier_depends()
87#else
88#define smp_mb() barrier()
89#define smp_rmb() barrier()
90#define smp_wmb() barrier()
91#define smp_read_barrier_depends() do { } while(0)
92#endif
93
94#define set_mb(var, value) do { xchg(&var, value); } while (0)
95#define set_wmb(var, value) do { var = value; wmb(); } while (0)
96
97/* Interrupt Control */
98static __inline__ void local_irq_enable(void)
99{
100 unsigned long __dummy0, __dummy1;
101
102 __asm__ __volatile__("stc sr, %0\n\t"
103 "and %1, %0\n\t"
104 "stc r6_bank, %1\n\t"
105 "or %1, %0\n\t"
106 "ldc %0, sr"
107 : "=&r" (__dummy0), "=r" (__dummy1)
108 : "1" (~0x000000f0)
109 : "memory");
110}
111
112static __inline__ void local_irq_disable(void)
113{
114 unsigned long __dummy;
115 __asm__ __volatile__("stc sr, %0\n\t"
116 "or #0xf0, %0\n\t"
117 "ldc %0, sr"
118 : "=&z" (__dummy)
119 : /* no inputs */
120 : "memory");
121}
122
123#define local_save_flags(x) \
124 __asm__("stc sr, %0; and #0xf0, %0" : "=&z" (x) :/**/: "memory" )
125
126#define irqs_disabled() \
127({ \
128 unsigned long flags; \
129 local_save_flags(flags); \
130 (flags != 0); \
131})
132
133static __inline__ unsigned long local_irq_save(void)
134{
135 unsigned long flags, __dummy;
136
137 __asm__ __volatile__("stc sr, %1\n\t"
138 "mov %1, %0\n\t"
139 "or #0xf0, %0\n\t"
140 "ldc %0, sr\n\t"
141 "mov %1, %0\n\t"
142 "and #0xf0, %0"
143 : "=&z" (flags), "=&r" (__dummy)
144 :/**/
145 : "memory" );
146 return flags;
147}
148
149#ifdef DEBUG_CLI_STI
150static __inline__ void local_irq_restore(unsigned long x)
151{
152 if ((x & 0x000000f0) != 0x000000f0)
153 local_irq_enable();
154 else {
155 unsigned long flags;
156 local_save_flags(flags);
157
158 if (flags == 0) {
159 extern void dump_stack(void);
160 printk(KERN_ERR "BUG!\n");
161 dump_stack();
162 local_irq_disable();
163 }
164 }
165}
166#else
167#define local_irq_restore(x) do { \
168 if ((x & 0x000000f0) != 0x000000f0) \
169 local_irq_enable(); \
170} while (0)
171#endif
172
173#define really_restore_flags(x) do { \
174 if ((x & 0x000000f0) != 0x000000f0) \
175 local_irq_enable(); \
176 else \
177 local_irq_disable(); \
178} while (0)
179
180/*
181 * Jump to P2 area.
182 * When handling TLB or caches, we need to do it from P2 area.
183 */
184#define jump_to_P2() \
185do { \
186 unsigned long __dummy; \
187 __asm__ __volatile__( \
188 "mov.l 1f, %0\n\t" \
189 "or %1, %0\n\t" \
190 "jmp @%0\n\t" \
191 " nop\n\t" \
192 ".balign 4\n" \
193 "1: .long 2f\n" \
194 "2:" \
195 : "=&r" (__dummy) \
196 : "r" (0x20000000)); \
197} while (0)
198
199/*
200 * Back to P1 area.
201 */
202#define back_to_P1() \
203do { \
204 unsigned long __dummy; \
205 __asm__ __volatile__( \
206 "nop;nop;nop;nop;nop;nop;nop\n\t" \
207 "mov.l 1f, %0\n\t" \
208 "jmp @%0\n\t" \
209 " nop\n\t" \
210 ".balign 4\n" \
211 "1: .long 2f\n" \
212 "2:" \
213 : "=&r" (__dummy)); \
214} while (0)
215
216/* For spinlocks etc */
217#define local_irq_save(x) x = local_irq_save()
218
219static __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
220{
221 unsigned long flags, retval;
222
223 local_irq_save(flags);
224 retval = *m;
225 *m = val;
226 local_irq_restore(flags);
227 return retval;
228}
229
230static __inline__ unsigned long xchg_u8(volatile unsigned char * m, unsigned long val)
231{
232 unsigned long flags, retval;
233
234 local_irq_save(flags);
235 retval = *m;
236 *m = val & 0xff;
237 local_irq_restore(flags);
238 return retval;
239}
240
241static __inline__ unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
242{
243 switch (size) {
244 case 4:
245 return xchg_u32(ptr, x);
246 break;
247 case 1:
248 return xchg_u8(ptr, x);
249 break;
250 }
251 __xchg_called_with_bad_pointer();
252 return x;
253}
254
255/* XXX
256 * disable hlt during certain critical i/o operations
257 */
258#define HAVE_DISABLE_HLT
259void disable_hlt(void);
260void enable_hlt(void);
261
262#define arch_align_stack(x) (x)
263
264#endif
diff --git a/include/asm-sh/systemh/7751systemh.h b/include/asm-sh/systemh/7751systemh.h
new file mode 100644
index 000000000000..4170531bdbd9
--- /dev/null
+++ b/include/asm-sh/systemh/7751systemh.h
@@ -0,0 +1,68 @@
1#ifndef __ASM_SH_SYSTEMH_7751SYSTEMH_H
2#define __ASM_SH_SYSTEMH_7751SYSTEMH_H
3
4/*
5 * linux/include/asm-sh/systemh/7751systemh.h
6 *
7 * Copyright (C) 2000 Kazumoto Kojima
8 *
9 * Hitachi SystemH support
10
11 * Modified for 7751 SystemH by
12 * Jonathan Short, 2002.
13 */
14
15/* Box specific addresses. */
16
17#define PA_ROM 0x00000000 /* EPROM */
18#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
19#define PA_FROM 0x01000000 /* EPROM */
20#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
21#define PA_EXT1 0x04000000
22#define PA_EXT1_SIZE 0x04000000
23#define PA_EXT2 0x08000000
24#define PA_EXT2_SIZE 0x04000000
25#define PA_SDRAM 0x0c000000
26#define PA_SDRAM_SIZE 0x04000000
27
28#define PA_EXT4 0x12000000
29#define PA_EXT4_SIZE 0x02000000
30#define PA_EXT5 0x14000000
31#define PA_EXT5_SIZE 0x04000000
32#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
33
34#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */
35#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */
36#define PA_LED 0xba000000 /* LED */
37#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */
38
39#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controler */
40#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
41#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
42#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
43#define MRSHPC_MODE (PA_MRSHPC + 4)
44#define MRSHPC_OPTION (PA_MRSHPC + 6)
45#define MRSHPC_CSR (PA_MRSHPC + 8)
46#define MRSHPC_ISR (PA_MRSHPC + 10)
47#define MRSHPC_ICR (PA_MRSHPC + 12)
48#define MRSHPC_CPWCR (PA_MRSHPC + 14)
49#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
50#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
51#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
52#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
53#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
54#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
55#define MRSHPC_CDCR (PA_MRSHPC + 28)
56#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
57
58#define BCR_ILCRA (PA_BCR + 0)
59#define BCR_ILCRB (PA_BCR + 2)
60#define BCR_ILCRC (PA_BCR + 4)
61#define BCR_ILCRD (PA_BCR + 6)
62#define BCR_ILCRE (PA_BCR + 8)
63#define BCR_ILCRF (PA_BCR + 10)
64#define BCR_ILCRG (PA_BCR + 12)
65
66#define IRQ_79C973 13
67
68#endif /* __ASM_SH_SYSTEMH_7751SYSTEMH_H */
diff --git a/include/asm-sh/systemh/io.h b/include/asm-sh/systemh/io.h
new file mode 100644
index 000000000000..327849b49db8
--- /dev/null
+++ b/include/asm-sh/systemh/io.h
@@ -0,0 +1,43 @@
1/*
2 * include/asm-sh/systemh/io.h
3 *
4 * Stupid I/O definitions for SystemH, cloned from SE7751.
5 *
6 * Copyright (C) 2003 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#ifndef __ASM_SH_SYSTEMH_IO_H
13#define __ASM_SH_SYSTEMH_IO_H
14
15extern unsigned char sh7751systemh_inb(unsigned long port);
16extern unsigned short sh7751systemh_inw(unsigned long port);
17extern unsigned int sh7751systemh_inl(unsigned long port);
18
19extern void sh7751systemh_outb(unsigned char value, unsigned long port);
20extern void sh7751systemh_outw(unsigned short value, unsigned long port);
21extern void sh7751systemh_outl(unsigned int value, unsigned long port);
22
23extern unsigned char sh7751systemh_inb_p(unsigned long port);
24extern void sh7751systemh_outb_p(unsigned char value, unsigned long port);
25
26extern void sh7751systemh_insb(unsigned long port, void *addr, unsigned long count);
27extern void sh7751systemh_insw(unsigned long port, void *addr, unsigned long count);
28extern void sh7751systemh_insl(unsigned long port, void *addr, unsigned long count);
29extern void sh7751systemh_outsb(unsigned long port, const void *addr, unsigned long count);
30extern void sh7751systemh_outsw(unsigned long port, const void *addr, unsigned long count);
31extern void sh7751systemh_outsl(unsigned long port, const void *addr, unsigned long count);
32
33extern unsigned char sh7751systemh_readb(unsigned long addr);
34extern unsigned short sh7751systemh_readw(unsigned long addr);
35extern unsigned int sh7751systemh_readl(unsigned long addr);
36extern void sh7751systemh_writeb(unsigned char b, unsigned long addr);
37extern void sh7751systemh_writew(unsigned short b, unsigned long addr);
38extern void sh7751systemh_writel(unsigned int b, unsigned long addr);
39
40extern unsigned long sh7751systemh_isa_port2addr(unsigned long offset);
41
42#endif /* __ASM_SH_SYSTEMH_IO_H */
43
diff --git a/include/asm-sh/termbits.h b/include/asm-sh/termbits.h
new file mode 100644
index 000000000000..4f9822a8e7b4
--- /dev/null
+++ b/include/asm-sh/termbits.h
@@ -0,0 +1,173 @@
1#ifndef __ASM_SH_TERMBITS_H
2#define __ASM_SH_TERMBITS_H
3
4#include <linux/posix_types.h>
5
6typedef unsigned char cc_t;
7typedef unsigned int speed_t;
8typedef unsigned int tcflag_t;
9
10#define NCCS 19
11struct termios {
12 tcflag_t c_iflag; /* input mode flags */
13 tcflag_t c_oflag; /* output mode flags */
14 tcflag_t c_cflag; /* control mode flags */
15 tcflag_t c_lflag; /* local mode flags */
16 cc_t c_line; /* line discipline */
17 cc_t c_cc[NCCS]; /* control characters */
18};
19
20/* c_cc characters */
21#define VINTR 0
22#define VQUIT 1
23#define VERASE 2
24#define VKILL 3
25#define VEOF 4
26#define VTIME 5
27#define VMIN 6
28#define VSWTC 7
29#define VSTART 8
30#define VSTOP 9
31#define VSUSP 10
32#define VEOL 11
33#define VREPRINT 12
34#define VDISCARD 13
35#define VWERASE 14
36#define VLNEXT 15
37#define VEOL2 16
38
39/* c_iflag bits */
40#define IGNBRK 0000001
41#define BRKINT 0000002
42#define IGNPAR 0000004
43#define PARMRK 0000010
44#define INPCK 0000020
45#define ISTRIP 0000040
46#define INLCR 0000100
47#define IGNCR 0000200
48#define ICRNL 0000400
49#define IUCLC 0001000
50#define IXON 0002000
51#define IXANY 0004000
52#define IXOFF 0010000
53#define IMAXBEL 0020000
54#define IUTF8 0040000
55
56/* c_oflag bits */
57#define OPOST 0000001
58#define OLCUC 0000002
59#define ONLCR 0000004
60#define OCRNL 0000010
61#define ONOCR 0000020
62#define ONLRET 0000040
63#define OFILL 0000100
64#define OFDEL 0000200
65#define NLDLY 0000400
66#define NL0 0000000
67#define NL1 0000400
68#define CRDLY 0003000
69#define CR0 0000000
70#define CR1 0001000
71#define CR2 0002000
72#define CR3 0003000
73#define TABDLY 0014000
74#define TAB0 0000000
75#define TAB1 0004000
76#define TAB2 0010000
77#define TAB3 0014000
78#define XTABS 0014000
79#define BSDLY 0020000
80#define BS0 0000000
81#define BS1 0020000
82#define VTDLY 0040000
83#define VT0 0000000
84#define VT1 0040000
85#define FFDLY 0100000
86#define FF0 0000000
87#define FF1 0100000
88
89/* c_cflag bit meaning */
90#define CBAUD 0010017
91#define B0 0000000 /* hang up */
92#define B50 0000001
93#define B75 0000002
94#define B110 0000003
95#define B134 0000004
96#define B150 0000005
97#define B200 0000006
98#define B300 0000007
99#define B600 0000010
100#define B1200 0000011
101#define B1800 0000012
102#define B2400 0000013
103#define B4800 0000014
104#define B9600 0000015
105#define B19200 0000016
106#define B38400 0000017
107#define EXTA B19200
108#define EXTB B38400
109#define CSIZE 0000060
110#define CS5 0000000
111#define CS6 0000020
112#define CS7 0000040
113#define CS8 0000060
114#define CSTOPB 0000100
115#define CREAD 0000200
116#define PARENB 0000400
117#define PARODD 0001000
118#define HUPCL 0002000
119#define CLOCAL 0004000
120#define CBAUDEX 0010000
121#define B57600 0010001
122#define B115200 0010002
123#define B230400 0010003
124#define B460800 0010004
125#define B500000 0010005
126#define B576000 0010006
127#define B921600 0010007
128#define B1000000 0010010
129#define B1152000 0010011
130#define B1500000 0010012
131#define B2000000 0010013
132#define B2500000 0010014
133#define B3000000 0010015
134#define B3500000 0010016
135#define B4000000 0010017
136#define CIBAUD 002003600000 /* input baud rate (not used) */
137#define CMSPAR 010000000000 /* mark or space (stick) parity */
138#define CRTSCTS 020000000000 /* flow control */
139
140/* c_lflag bits */
141#define ISIG 0000001
142#define ICANON 0000002
143#define XCASE 0000004
144#define ECHO 0000010
145#define ECHOE 0000020
146#define ECHOK 0000040
147#define ECHONL 0000100
148#define NOFLSH 0000200
149#define TOSTOP 0000400
150#define ECHOCTL 0001000
151#define ECHOPRT 0002000
152#define ECHOKE 0004000
153#define FLUSHO 0010000
154#define PENDIN 0040000
155#define IEXTEN 0100000
156
157/* tcflow() and TCXONC use these */
158#define TCOOFF 0
159#define TCOON 1
160#define TCIOFF 2
161#define TCION 3
162
163/* tcflush() and TCFLSH use these */
164#define TCIFLUSH 0
165#define TCOFLUSH 1
166#define TCIOFLUSH 2
167
168/* tcsetattr uses these */
169#define TCSANOW 0
170#define TCSADRAIN 1
171#define TCSAFLUSH 2
172
173#endif /* __ASM_SH_TERMBITS_H */
diff --git a/include/asm-sh/termios.h b/include/asm-sh/termios.h
new file mode 100644
index 000000000000..44edfd471443
--- /dev/null
+++ b/include/asm-sh/termios.h
@@ -0,0 +1,106 @@
1#ifndef __ASM_SH_TERMIOS_H
2#define __ASM_SH_TERMIOS_H
3
4#include <asm/termbits.h>
5#include <asm/ioctls.h>
6
7struct winsize {
8 unsigned short ws_row;
9 unsigned short ws_col;
10 unsigned short ws_xpixel;
11 unsigned short ws_ypixel;
12};
13
14#define NCC 8
15struct termio {
16 unsigned short c_iflag; /* input mode flags */
17 unsigned short c_oflag; /* output mode flags */
18 unsigned short c_cflag; /* control mode flags */
19 unsigned short c_lflag; /* local mode flags */
20 unsigned char c_line; /* line discipline */
21 unsigned char c_cc[NCC]; /* control characters */
22};
23
24/* modem lines */
25#define TIOCM_LE 0x001
26#define TIOCM_DTR 0x002
27#define TIOCM_RTS 0x004
28#define TIOCM_ST 0x008
29#define TIOCM_SR 0x010
30#define TIOCM_CTS 0x020
31#define TIOCM_CAR 0x040
32#define TIOCM_RNG 0x080
33#define TIOCM_DSR 0x100
34#define TIOCM_CD TIOCM_CAR
35#define TIOCM_RI TIOCM_RNG
36#define TIOCM_OUT1 0x2000
37#define TIOCM_OUT2 0x4000
38#define TIOCM_LOOP 0x8000
39
40/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
41
42/* line disciplines */
43#define N_TTY 0
44#define N_SLIP 1
45#define N_MOUSE 2
46#define N_PPP 3
47#define N_STRIP 4
48#define N_AX25 5
49#define N_X25 6 /* X.25 async */
50#define N_6PACK 7
51#define N_MASC 8 /* Reserved for Mobitex module <kaz@cafe.net> */
52#define N_R3964 9 /* Reserved for Simatic R3964 module */
53#define N_PROFIBUS_FDL 10 /* Reserved for Profibus <Dave@mvhi.com> */
54#define N_IRDA 11 /* Linux IR - http://irda.sourceforge.net/ */
55#define N_SMSBLOCK 12 /* SMS block mode - for talking to GSM data cards about SMS messages */
56#define N_HDLC 13 /* synchronous HDLC */
57#define N_SYNC_PPP 14
58#define N_HCI 15 /* Bluetooth HCI UART */
59
60#ifdef __KERNEL__
61
62/* intr=^C quit=^\ erase=del kill=^U
63 eof=^D vtime=\0 vmin=\1 sxtc=\0
64 start=^Q stop=^S susp=^Z eol=\0
65 reprint=^R discard=^U werase=^W lnext=^V
66 eol2=\0
67*/
68#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
69
70/*
71 * Translate a "termio" structure into a "termios". Ugh.
72 */
73#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
74 unsigned short __tmp; \
75 get_user(__tmp,&(termio)->x); \
76 *(unsigned short *) &(termios)->x = __tmp; \
77}
78
79#define user_termio_to_kernel_termios(termios, termio) \
80({ \
81 SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
82 SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
83 SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
84 SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
85 copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
86})
87
88/*
89 * Translate a "termios" structure into a "termio". Ugh.
90 */
91#define kernel_termios_to_user_termio(termio, termios) \
92({ \
93 put_user((termios)->c_iflag, &(termio)->c_iflag); \
94 put_user((termios)->c_oflag, &(termio)->c_oflag); \
95 put_user((termios)->c_cflag, &(termio)->c_cflag); \
96 put_user((termios)->c_lflag, &(termio)->c_lflag); \
97 put_user((termios)->c_line, &(termio)->c_line); \
98 copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
99})
100
101#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios))
102#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios))
103
104#endif /* __KERNEL__ */
105
106#endif /* __ASM_SH_TERMIOS_H */
diff --git a/include/asm-sh/thread_info.h b/include/asm-sh/thread_info.h
new file mode 100644
index 000000000000..d82f883d8e6d
--- /dev/null
+++ b/include/asm-sh/thread_info.h
@@ -0,0 +1,102 @@
1#ifndef __ASM_SH_THREAD_INFO_H
2#define __ASM_SH_THREAD_INFO_H
3
4/* SuperH version
5 * Copyright (C) 2002 Niibe Yutaka
6 *
7 * The copyright of original i386 version is:
8 *
9 * Copyright (C) 2002 David Howells (dhowells@redhat.com)
10 * - Incorporating suggestions made by Linus Torvalds and Dave Miller
11 */
12
13#ifdef __KERNEL__
14
15#ifndef __ASSEMBLY__
16#include <asm/processor.h>
17
18struct thread_info {
19 struct task_struct *task; /* main task structure */
20 struct exec_domain *exec_domain; /* execution domain */
21 __u32 flags; /* low level flags */
22 __u32 cpu;
23 __s32 preempt_count; /* 0 => preemptable, <0 => BUG */
24 struct restart_block restart_block;
25 __u8 supervisor_stack[0];
26};
27
28#endif
29
30#define PREEMPT_ACTIVE 0x4000000
31
32/*
33 * macros/functions for gaining access to the thread information structure
34 */
35#ifndef __ASSEMBLY__
36#define INIT_THREAD_INFO(tsk) \
37{ \
38 .task = &tsk, \
39 .exec_domain = &default_exec_domain, \
40 .flags = 0, \
41 .cpu = 0, \
42 .preempt_count = 1, \
43 .restart_block = { \
44 .fn = do_no_restart_syscall, \
45 }, \
46}
47
48#define init_thread_info (init_thread_union.thread_info)
49#define init_stack (init_thread_union.stack)
50
51/* how to get the thread information struct from C */
52static inline struct thread_info *current_thread_info(void)
53{
54 struct thread_info *ti;
55 __asm__("stc r7_bank, %0" : "=r" (ti));
56 return ti;
57}
58
59/* thread information allocation */
60#define THREAD_SIZE (2*PAGE_SIZE)
61#define alloc_thread_info(ti) ((struct thread_info *) __get_free_pages(GFP_KERNEL,1))
62#define free_thread_info(ti) free_pages((unsigned long) (ti), 1)
63#define get_thread_info(ti) get_task_struct((ti)->task)
64#define put_thread_info(ti) put_task_struct((ti)->task)
65
66#else /* !__ASSEMBLY__ */
67
68/* how to get the thread information struct from ASM */
69#define GET_THREAD_INFO(reg) \
70 stc r7_bank, reg
71
72#endif
73
74/*
75 * thread information flags
76 * - these are process state flags that various assembly files may need to access
77 * - pending work-to-be-done flags are in LSW
78 * - other flags in MSW
79 */
80#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
81#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */
82#define TIF_SIGPENDING 2 /* signal pending */
83#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
84#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */
85#define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */
86#define TIF_MEMDIE 18
87#define TIF_USERSPACE 31 /* true if FS sets userspace */
88
89#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
90#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
91#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
92#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
93#define _TIF_USEDFPU (1<<TIF_USEDFPU)
94#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
95#define _TIF_USERSPACE (1<<TIF_USERSPACE)
96
97#define _TIF_WORK_MASK 0x000000FE /* work to do on interrupt/exception return */
98#define _TIF_ALLWORK_MASK 0x000000FF /* work to do on any return to u-space */
99
100#endif /* __KERNEL__ */
101
102#endif /* __ASM_SH_THREAD_INFO_H */
diff --git a/include/asm-sh/timex.h b/include/asm-sh/timex.h
new file mode 100644
index 000000000000..a873e24113cf
--- /dev/null
+++ b/include/asm-sh/timex.h
@@ -0,0 +1,18 @@
1/*
2 * linux/include/asm-sh/timex.h
3 *
4 * sh architecture timex specifications
5 */
6#ifndef __ASM_SH_TIMEX_H
7#define __ASM_SH_TIMEX_H
8
9#define CLOCK_TICK_RATE (CONFIG_SH_PCLK_FREQ / 4) /* Underlying HZ */
10
11typedef unsigned long long cycles_t;
12
13static __inline__ cycles_t get_cycles (void)
14{
15 return 0;
16}
17
18#endif /* __ASM_SH_TIMEX_H */
diff --git a/include/asm-sh/tlb.h b/include/asm-sh/tlb.h
new file mode 100644
index 000000000000..53d185bcf872
--- /dev/null
+++ b/include/asm-sh/tlb.h
@@ -0,0 +1,18 @@
1#ifndef __ASM_SH_TLB_H
2#define __ASM_SH_TLB_H
3
4#define tlb_start_vma(tlb, vma) \
5 flush_cache_range(vma, vma->vm_start, vma->vm_end)
6
7#define tlb_end_vma(tlb, vma) \
8 flush_tlb_range(vma, vma->vm_start, vma->vm_end)
9
10#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
11
12/*
13 * Flush whole TLBs for MM
14 */
15#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
16
17#include <asm-generic/tlb.h>
18#endif
diff --git a/include/asm-sh/tlbflush.h b/include/asm-sh/tlbflush.h
new file mode 100644
index 000000000000..28c073b0fbab
--- /dev/null
+++ b/include/asm-sh/tlbflush.h
@@ -0,0 +1,31 @@
1#ifndef __ASM_SH_TLBFLUSH_H
2#define __ASM_SH_TLBFLUSH_H
3
4/*
5 * TLB flushing:
6 *
7 * - flush_tlb() flushes the current mm struct TLBs
8 * - flush_tlb_all() flushes all processes TLBs
9 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
10 * - flush_tlb_page(vma, vmaddr) flushes one page
11 * - flush_tlb_range(vma, start, end) flushes a range of pages
12 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
13 * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
14 */
15
16extern void flush_tlb(void);
17extern void flush_tlb_all(void);
18extern void flush_tlb_mm(struct mm_struct *mm);
19extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
20 unsigned long end);
21extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
22extern void __flush_tlb_page(unsigned long asid, unsigned long page);
23
24static inline void flush_tlb_pgtables(struct mm_struct *mm,
25 unsigned long start, unsigned long end)
26{ /* Nothing to do */
27}
28
29extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
30
31#endif /* __ASM_SH_TLBFLUSH_H */
diff --git a/include/asm-sh/topology.h b/include/asm-sh/topology.h
new file mode 100644
index 000000000000..cff001c316fe
--- /dev/null
+++ b/include/asm-sh/topology.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_SH_TOPOLOGY_H
2#define _ASM_SH_TOPOLOGY_H
3
4#include <asm-generic/topology.h>
5
6#endif /* _ASM_SH_TOPOLOGY_H */
diff --git a/include/asm-sh/types.h b/include/asm-sh/types.h
new file mode 100644
index 000000000000..c4dc126c5621
--- /dev/null
+++ b/include/asm-sh/types.h
@@ -0,0 +1,67 @@
1#ifndef __ASM_SH_TYPES_H
2#define __ASM_SH_TYPES_H
3
4#ifndef __ASSEMBLY__
5
6typedef unsigned short umode_t;
7
8/*
9 * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
10 * header files exported to user space
11 */
12
13typedef __signed__ char __s8;
14typedef unsigned char __u8;
15
16typedef __signed__ short __s16;
17typedef unsigned short __u16;
18
19typedef __signed__ int __s32;
20typedef unsigned int __u32;
21
22#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
23typedef __signed__ long long __s64;
24typedef unsigned long long __u64;
25#endif
26
27#endif /* __ASSEMBLY__ */
28
29/*
30 * These aren't exported outside the kernel to avoid name space clashes
31 */
32#ifdef __KERNEL__
33
34#define BITS_PER_LONG 32
35
36#ifndef __ASSEMBLY__
37
38#include <linux/config.h>
39
40typedef __signed__ char s8;
41typedef unsigned char u8;
42
43typedef __signed__ short s16;
44typedef unsigned short u16;
45
46typedef __signed__ int s32;
47typedef unsigned int u32;
48
49typedef __signed__ long long s64;
50typedef unsigned long long u64;
51
52/* Dma addresses are 32-bits wide. */
53
54typedef u32 dma_addr_t;
55
56#ifdef CONFIG_LBD
57typedef u64 sector_t;
58#define HAVE_SECTOR_T
59#endif
60
61typedef unsigned int kmem_bufctl_t;
62
63#endif /* __ASSEMBLY__ */
64
65#endif /* __KERNEL__ */
66
67#endif /* __ASM_SH_TYPES_H */
diff --git a/include/asm-sh/uaccess.h b/include/asm-sh/uaccess.h
new file mode 100644
index 000000000000..fb9e334afa2b
--- /dev/null
+++ b/include/asm-sh/uaccess.h
@@ -0,0 +1,600 @@
1/* $Id: uaccess.h,v 1.11 2003/10/13 07:21:20 lethal Exp $
2 *
3 * User space memory access functions
4 *
5 * Copyright (C) 1999, 2002 Niibe Yutaka
6 * Copyright (C) 2003 Paul Mundt
7 *
8 * Based on:
9 * MIPS implementation version 1.15 by
10 * Copyright (C) 1996, 1997, 1998 by Ralf Baechle
11 * and i386 version.
12 */
13#ifndef __ASM_SH_UACCESS_H
14#define __ASM_SH_UACCESS_H
15
16#include <linux/errno.h>
17#include <linux/sched.h>
18
19/*
20 * NOTE: Macro/functions in this file depends on threads_info.h implementation.
21 * Assumes:
22 * TI_FLAGS == 8
23 * TIF_USERSPACE == 31
24 * USER_ADDR_LIMIT == 0x80000000
25 */
26
27#define VERIFY_READ 0
28#define VERIFY_WRITE 1
29
30typedef struct {
31 unsigned int is_user_space;
32} mm_segment_t;
33
34/*
35 * The fs value determines whether argument validity checking should be
36 * performed or not. If get_fs() == USER_DS, checking is performed, with
37 * get_fs() == KERNEL_DS, checking is bypassed.
38 *
39 * For historical reasons (Data Segment Register?), these macros are misnamed.
40 */
41
42#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
43#define segment_eq(a,b) ((a).is_user_space == (b).is_user_space)
44
45#define USER_ADDR_LIMIT 0x80000000
46
47#define KERNEL_DS MAKE_MM_SEG(0)
48#define USER_DS MAKE_MM_SEG(1)
49
50#define get_ds() (KERNEL_DS)
51
52#if !defined(CONFIG_MMU)
53static inline mm_segment_t get_fs(void)
54{
55 return USER_DS;
56}
57
58static inline void set_fs(mm_segment_t s)
59{
60}
61
62/*
63 * __access_ok: Check if address with size is OK or not.
64 *
65 * If we don't have an MMU (or if its disabled) the only thing we really have
66 * to look out for is if the address resides somewhere outside of what
67 * available RAM we have.
68 *
69 * TODO: This check could probably also stand to be restricted somewhat more..
70 * though it still does the Right Thing(tm) for the time being.
71 */
72static inline int __access_ok(unsigned long addr, unsigned long size)
73{
74 extern unsigned long memory_start, memory_end;
75
76 return ((addr >= memory_start) && ((addr + size) < memory_end));
77}
78#else /* CONFIG_MMU */
79static inline mm_segment_t get_fs(void)
80{
81 return MAKE_MM_SEG(test_thread_flag(TIF_USERSPACE));
82}
83
84static inline void set_fs(mm_segment_t s)
85{
86 unsigned long ti, flag;
87 __asm__ __volatile__(
88 "stc r7_bank, %0\n\t"
89 "mov.l @(8,%0), %1\n\t"
90 "shal %1\n\t"
91 "cmp/pl %2\n\t"
92 "rotcr %1\n\t"
93 "mov.l %1, @(8,%0)"
94 : "=&r" (ti), "=&r" (flag)
95 : "r" (s.is_user_space)
96 : "t");
97/****
98 if (s.is_user_space)
99 set_thread_flag(TIF_USERSPACE);
100 else
101 clear_thread_flag(TIF_USERSPACE);
102****/
103}
104
105/*
106 * __access_ok: Check if address with size is OK or not.
107 *
108 * We do three checks:
109 * (1) is it user space?
110 * (2) addr + size --> carry?
111 * (3) addr + size >= 0x80000000 (USER_ADDR_LIMIT)
112 *
113 * (1) (2) (3) | RESULT
114 * 0 0 0 | ok
115 * 0 0 1 | ok
116 * 0 1 0 | bad
117 * 0 1 1 | bad
118 * 1 0 0 | ok
119 * 1 0 1 | bad
120 * 1 1 0 | bad
121 * 1 1 1 | bad
122 */
123static inline int __access_ok(unsigned long addr, unsigned long size)
124{
125 unsigned long flag, tmp;
126
127 __asm__("stc r7_bank, %0\n\t"
128 "mov.l @(8,%0), %0\n\t"
129 "clrt\n\t"
130 "addc %2, %1\n\t"
131 "and %1, %0\n\t"
132 "rotcl %0\n\t"
133 "rotcl %0\n\t"
134 "and #3, %0"
135 : "=&z" (flag), "=r" (tmp)
136 : "r" (addr), "1" (size)
137 : "t");
138
139 return flag == 0;
140}
141#endif /* CONFIG_MMU */
142
143static inline int access_ok(int type, const void __user *p, unsigned long size)
144{
145 unsigned long addr = (unsigned long)p;
146 return __access_ok(addr, size);
147}
148
149/* this function will go away soon - use access_ok() instead */
150static inline int __deprecated verify_area(int type, const void __user * addr, unsigned long size)
151{
152 return access_ok(type,addr,size) ? 0 : -EFAULT;
153}
154
155/*
156 * Uh, these should become the main single-value transfer routines ...
157 * They automatically use the right size if we just have the right
158 * pointer type ...
159 *
160 * As SuperH uses the same address space for kernel and user data, we
161 * can just do these as direct assignments.
162 *
163 * Careful to not
164 * (a) re-use the arguments for side effects (sizeof is ok)
165 * (b) require any knowledge of processes at this stage
166 */
167#define put_user(x,ptr) __put_user_check((x),(ptr),sizeof(*(ptr)))
168#define get_user(x,ptr) __get_user_check((x),(ptr),sizeof(*(ptr)))
169
170/*
171 * The "__xxx" versions do not do address space checking, useful when
172 * doing multiple accesses to the same area (the user has to do the
173 * checks by hand with "access_ok()")
174 */
175#define __put_user(x,ptr) \
176 __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr)))
177#define __get_user(x,ptr) \
178 __get_user_nocheck((x),(ptr),sizeof(*(ptr)))
179
180struct __large_struct { unsigned long buf[100]; };
181#define __m(x) (*(struct __large_struct *)(x))
182
183#define __get_user_size(x,ptr,size,retval) \
184do { \
185 retval = 0; \
186 switch (size) { \
187 case 1: \
188 __get_user_asm(x, ptr, retval, "b"); \
189 break; \
190 case 2: \
191 __get_user_asm(x, ptr, retval, "w"); \
192 break; \
193 case 4: \
194 __get_user_asm(x, ptr, retval, "l"); \
195 break; \
196 default: \
197 __get_user_unknown(); \
198 break; \
199 } \
200} while (0)
201
202#define __get_user_nocheck(x,ptr,size) \
203({ \
204 long __gu_err, __gu_val; \
205 __get_user_size(__gu_val, (ptr), (size), __gu_err); \
206 (x) = (__typeof__(*(ptr)))__gu_val; \
207 __gu_err; \
208})
209
210#define __get_user_check(x,ptr,size) \
211({ \
212 long __gu_err, __gu_val; \
213 switch (size) { \
214 case 1: \
215 __get_user_1(__gu_val, (ptr), __gu_err); \
216 break; \
217 case 2: \
218 __get_user_2(__gu_val, (ptr), __gu_err); \
219 break; \
220 case 4: \
221 __get_user_4(__gu_val, (ptr), __gu_err); \
222 break; \
223 default: \
224 __get_user_unknown(); \
225 break; \
226 } \
227 \
228 (x) = (__typeof__(*(ptr)))__gu_val; \
229 __gu_err; \
230})
231
232#define __get_user_1(x,addr,err) ({ \
233__asm__("stc r7_bank, %1\n\t" \
234 "mov.l @(8,%1), %1\n\t" \
235 "and %2, %1\n\t" \
236 "cmp/pz %1\n\t" \
237 "bt/s 1f\n\t" \
238 " mov #0, %0\n\t" \
239 "0:\n" \
240 "mov #-14, %0\n\t" \
241 "bra 2f\n\t" \
242 " mov #0, %1\n" \
243 "1:\n\t" \
244 "mov.b @%2, %1\n\t" \
245 "extu.b %1, %1\n" \
246 "2:\n" \
247 ".section __ex_table,\"a\"\n\t" \
248 ".long 1b, 0b\n\t" \
249 ".previous" \
250 : "=&r" (err), "=&r" (x) \
251 : "r" (addr) \
252 : "t"); \
253})
254
255#define __get_user_2(x,addr,err) ({ \
256__asm__("stc r7_bank, %1\n\t" \
257 "mov.l @(8,%1), %1\n\t" \
258 "and %2, %1\n\t" \
259 "cmp/pz %1\n\t" \
260 "bt/s 1f\n\t" \
261 " mov #0, %0\n\t" \
262 "0:\n" \
263 "mov #-14, %0\n\t" \
264 "bra 2f\n\t" \
265 " mov #0, %1\n" \
266 "1:\n\t" \
267 "mov.w @%2, %1\n\t" \
268 "extu.w %1, %1\n" \
269 "2:\n" \
270 ".section __ex_table,\"a\"\n\t" \
271 ".long 1b, 0b\n\t" \
272 ".previous" \
273 : "=&r" (err), "=&r" (x) \
274 : "r" (addr) \
275 : "t"); \
276})
277
278#define __get_user_4(x,addr,err) ({ \
279__asm__("stc r7_bank, %1\n\t" \
280 "mov.l @(8,%1), %1\n\t" \
281 "and %2, %1\n\t" \
282 "cmp/pz %1\n\t" \
283 "bt/s 1f\n\t" \
284 " mov #0, %0\n\t" \
285 "0:\n" \
286 "mov #-14, %0\n\t" \
287 "bra 2f\n\t" \
288 " mov #0, %1\n" \
289 "1:\n\t" \
290 "mov.l @%2, %1\n\t" \
291 "2:\n" \
292 ".section __ex_table,\"a\"\n\t" \
293 ".long 1b, 0b\n\t" \
294 ".previous" \
295 : "=&r" (err), "=&r" (x) \
296 : "r" (addr) \
297 : "t"); \
298})
299
300#define __get_user_asm(x, addr, err, insn) \
301({ \
302__asm__ __volatile__( \
303 "1:\n\t" \
304 "mov." insn " %2, %1\n\t" \
305 "mov #0, %0\n" \
306 "2:\n" \
307 ".section .fixup,\"ax\"\n" \
308 "3:\n\t" \
309 "mov #0, %1\n\t" \
310 "mov.l 4f, %0\n\t" \
311 "jmp @%0\n\t" \
312 " mov %3, %0\n" \
313 "4: .long 2b\n\t" \
314 ".previous\n" \
315 ".section __ex_table,\"a\"\n\t" \
316 ".long 1b, 3b\n\t" \
317 ".previous" \
318 :"=&r" (err), "=&r" (x) \
319 :"m" (__m(addr)), "i" (-EFAULT)); })
320
321extern void __get_user_unknown(void);
322
323#define __put_user_size(x,ptr,size,retval) \
324do { \
325 retval = 0; \
326 switch (size) { \
327 case 1: \
328 __put_user_asm(x, ptr, retval, "b"); \
329 break; \
330 case 2: \
331 __put_user_asm(x, ptr, retval, "w"); \
332 break; \
333 case 4: \
334 __put_user_asm(x, ptr, retval, "l"); \
335 break; \
336 case 8: \
337 __put_user_u64(x, ptr, retval); \
338 break; \
339 default: \
340 __put_user_unknown(); \
341 } \
342} while (0)
343
344#define __put_user_nocheck(x,ptr,size) \
345({ \
346 long __pu_err; \
347 __put_user_size((x),(ptr),(size),__pu_err); \
348 __pu_err; \
349})
350
351#define __put_user_check(x,ptr,size) \
352({ \
353 long __pu_err = -EFAULT; \
354 __typeof__(*(ptr)) *__pu_addr = (ptr); \
355 \
356 if (__access_ok((unsigned long)__pu_addr,size)) \
357 __put_user_size((x),__pu_addr,(size),__pu_err); \
358 __pu_err; \
359})
360
361#define __put_user_asm(x, addr, err, insn) \
362({ \
363__asm__ __volatile__( \
364 "1:\n\t" \
365 "mov." insn " %1, %2\n\t" \
366 "mov #0, %0\n" \
367 "2:\n" \
368 ".section .fixup,\"ax\"\n" \
369 "3:\n\t" \
370 "nop\n\t" \
371 "mov.l 4f, %0\n\t" \
372 "jmp @%0\n\t" \
373 "mov %3, %0\n" \
374 "4: .long 2b\n\t" \
375 ".previous\n" \
376 ".section __ex_table,\"a\"\n\t" \
377 ".long 1b, 3b\n\t" \
378 ".previous" \
379 :"=&r" (err) \
380 :"r" (x), "m" (__m(addr)), "i" (-EFAULT) \
381 :"memory"); })
382
383#if defined(__LITTLE_ENDIAN__)
384#define __put_user_u64(val,addr,retval) \
385({ \
386__asm__ __volatile__( \
387 "1:\n\t" \
388 "mov.l %R1,%2\n\t" \
389 "mov.l %S1,%T2\n\t" \
390 "mov #0,%0\n" \
391 "2:\n" \
392 ".section .fixup,\"ax\"\n" \
393 "3:\n\t" \
394 "nop\n\t" \
395 "mov.l 4f,%0\n\t" \
396 "jmp @%0\n\t" \
397 " mov %3,%0\n" \
398 "4: .long 2b\n\t" \
399 ".previous\n" \
400 ".section __ex_table,\"a\"\n\t" \
401 ".long 1b, 3b\n\t" \
402 ".previous" \
403 : "=r" (retval) \
404 : "r" (val), "m" (__m(addr)), "i" (-EFAULT) \
405 : "memory"); })
406#else
407#define __put_user_u64(val,addr,retval) \
408({ \
409__asm__ __volatile__( \
410 "1:\n\t" \
411 "mov.l %S1,%2\n\t" \
412 "mov.l %R1,%T2\n\t" \
413 "mov #0,%0\n" \
414 "2:\n" \
415 ".section .fixup,\"ax\"\n" \
416 "3:\n\t" \
417 "nop\n\t" \
418 "mov.l 4f,%0\n\t" \
419 "jmp @%0\n\t" \
420 " mov %3,%0\n" \
421 "4: .long 2b\n\t" \
422 ".previous\n" \
423 ".section __ex_table,\"a\"\n\t" \
424 ".long 1b, 3b\n\t" \
425 ".previous" \
426 : "=r" (retval) \
427 : "r" (val), "m" (__m(addr)), "i" (-EFAULT) \
428 : "memory"); })
429#endif
430
431extern void __put_user_unknown(void);
432
433/* Generic arbitrary sized copy. */
434/* Return the number of bytes NOT copied */
435extern __kernel_size_t __copy_user(void *to, const void *from, __kernel_size_t n);
436
437#define copy_to_user(to,from,n) ({ \
438void *__copy_to = (void *) (to); \
439__kernel_size_t __copy_size = (__kernel_size_t) (n); \
440__kernel_size_t __copy_res; \
441if(__copy_size && __access_ok((unsigned long)__copy_to, __copy_size)) { \
442__copy_res = __copy_user(__copy_to, (void *) (from), __copy_size); \
443} else __copy_res = __copy_size; \
444__copy_res; })
445
446#define __copy_to_user(to,from,n) \
447 __copy_user((void *)(to), \
448 (void *)(from), n)
449
450#define __copy_to_user_inatomic __copy_to_user
451#define __copy_from_user_inatomic __copy_from_user
452
453
454#define copy_from_user(to,from,n) ({ \
455void *__copy_to = (void *) (to); \
456void *__copy_from = (void *) (from); \
457__kernel_size_t __copy_size = (__kernel_size_t) (n); \
458__kernel_size_t __copy_res; \
459if(__copy_size && __access_ok((unsigned long)__copy_from, __copy_size)) { \
460__copy_res = __copy_user(__copy_to, __copy_from, __copy_size); \
461} else __copy_res = __copy_size; \
462__copy_res; })
463
464#define __copy_from_user(to,from,n) \
465 __copy_user((void *)(to), \
466 (void *)(from), n)
467
468/*
469 * Clear the area and return remaining number of bytes
470 * (on failure. Usually it's 0.)
471 */
472extern __kernel_size_t __clear_user(void *addr, __kernel_size_t size);
473
474#define clear_user(addr,n) ({ \
475void * __cl_addr = (addr); \
476unsigned long __cl_size = (n); \
477if (__cl_size && __access_ok(((unsigned long)(__cl_addr)), __cl_size)) \
478__cl_size = __clear_user(__cl_addr, __cl_size); \
479__cl_size; })
480
481static __inline__ int
482__strncpy_from_user(unsigned long __dest, unsigned long __user __src, int __count)
483{
484 __kernel_size_t res;
485 unsigned long __dummy, _d, _s;
486
487 __asm__ __volatile__(
488 "9:\n"
489 "mov.b @%2+, %1\n\t"
490 "cmp/eq #0, %1\n\t"
491 "bt/s 2f\n"
492 "1:\n"
493 "mov.b %1, @%3\n\t"
494 "dt %7\n\t"
495 "bf/s 9b\n\t"
496 " add #1, %3\n\t"
497 "2:\n\t"
498 "sub %7, %0\n"
499 "3:\n"
500 ".section .fixup,\"ax\"\n"
501 "4:\n\t"
502 "mov.l 5f, %1\n\t"
503 "jmp @%1\n\t"
504 " mov %8, %0\n\t"
505 ".balign 4\n"
506 "5: .long 3b\n"
507 ".previous\n"
508 ".section __ex_table,\"a\"\n"
509 " .balign 4\n"
510 " .long 9b,4b\n"
511 ".previous"
512 : "=r" (res), "=&z" (__dummy), "=r" (_s), "=r" (_d)
513 : "0" (__count), "2" (__src), "3" (__dest), "r" (__count),
514 "i" (-EFAULT)
515 : "memory", "t");
516
517 return res;
518}
519
520#define strncpy_from_user(dest,src,count) ({ \
521unsigned long __sfu_src = (unsigned long) (src); \
522int __sfu_count = (int) (count); \
523long __sfu_res = -EFAULT; \
524if(__access_ok(__sfu_src, __sfu_count)) { \
525__sfu_res = __strncpy_from_user((unsigned long) (dest), __sfu_src, __sfu_count); \
526} __sfu_res; })
527
528/*
529 * Return the size of a string (including the ending 0!)
530 */
531static __inline__ long __strnlen_user(const char __user *__s, long __n)
532{
533 unsigned long res;
534 unsigned long __dummy;
535
536 __asm__ __volatile__(
537 "9:\n"
538 "cmp/eq %4, %0\n\t"
539 "bt 2f\n"
540 "1:\t"
541 "mov.b @(%0,%3), %1\n\t"
542 "tst %1, %1\n\t"
543 "bf/s 9b\n\t"
544 " add #1, %0\n"
545 "2:\n"
546 ".section .fixup,\"ax\"\n"
547 "3:\n\t"
548 "mov.l 4f, %1\n\t"
549 "jmp @%1\n\t"
550 " mov %5, %0\n"
551 ".balign 4\n"
552 "4: .long 2b\n"
553 ".previous\n"
554 ".section __ex_table,\"a\"\n"
555 " .balign 4\n"
556 " .long 1b,3b\n"
557 ".previous"
558 : "=z" (res), "=&r" (__dummy)
559 : "0" (0), "r" (__s), "r" (__n), "i" (-EFAULT)
560 : "t");
561 return res;
562}
563
564static __inline__ long strnlen_user(const char __user *s, long n)
565{
566 if (!access_ok(VERIFY_READ, s, n))
567 return 0;
568 else
569 return __strnlen_user(s, n);
570}
571
572static __inline__ long strlen_user(const char __user *s)
573{
574 if (!access_ok(VERIFY_READ, s, 0))
575 return 0;
576 else
577 return __strnlen_user(s, ~0UL >> 1);
578}
579
580/*
581 * The exception table consists of pairs of addresses: the first is the
582 * address of an instruction that is allowed to fault, and the second is
583 * the address at which the program should continue. No registers are
584 * modified, so it is entirely up to the continuation code to figure out
585 * what to do.
586 *
587 * All the routines below use bits of fixup code that are out of line
588 * with the main instruction path. This means when everything is well,
589 * we don't even have to jump over them. Further, they do not intrude
590 * on our cache or tlb entries.
591 */
592
593struct exception_table_entry
594{
595 unsigned long insn, fixup;
596};
597
598extern int fixup_exception(struct pt_regs *regs);
599
600#endif /* __ASM_SH_UACCESS_H */
diff --git a/include/asm-sh/ubc.h b/include/asm-sh/ubc.h
new file mode 100644
index 000000000000..694f51f47941
--- /dev/null
+++ b/include/asm-sh/ubc.h
@@ -0,0 +1,60 @@
1/*
2 * include/asm-sh/ubc.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2002, 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_SH_UBC_H
12#define __ASM_SH_UBC_H
13#ifdef __KERNEL__
14
15#include <asm/cpu/ubc.h>
16
17/* User Break Controller */
18#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
19 defined(CONFIG_CPU_SUBTYPE_SH7300)
20#define UBC_TYPE_SH7729 (cpu_data->type == CPU_SH7729)
21#else
22#define UBC_TYPE_SH7729 0
23#endif
24
25#define BAMR_ASID (1 << 2)
26#define BAMR_NONE 0
27#define BAMR_10 0x1
28#define BAMR_12 0x2
29#define BAMR_ALL 0x3
30#define BAMR_16 0x8
31#define BAMR_20 0x9
32
33#define BBR_INST (1 << 4)
34#define BBR_DATA (2 << 4)
35#define BBR_READ (1 << 2)
36#define BBR_WRITE (2 << 2)
37#define BBR_BYTE 0x1
38#define BBR_HALF 0x2
39#define BBR_LONG 0x3
40#define BBR_QUAD (1 << 6) /* SH7750 */
41#define BBR_CPU (1 << 6) /* SH7709A,SH7729 */
42#define BBR_DMA (2 << 6) /* SH7709A,SH7729 */
43
44#define BRCR_CMFA (1 << 15)
45#define BRCR_CMFB (1 << 14)
46#define BRCR_PCTE (1 << 11)
47#define BRCR_PCBA (1 << 10) /* 1: after execution */
48#define BRCR_DBEB (1 << 7)
49#define BRCR_PCBB (1 << 6)
50#define BRCR_SEQ (1 << 3)
51#define BRCR_UBDE (1 << 0)
52
53#ifndef __ASSEMBLY__
54/* arch/sh/kernel/ubc.S */
55extern void ubc_wakeup(void);
56extern void ubc_sleep(void);
57#endif
58
59#endif /* __KERNEL__ */
60#endif /* __ASM_SH_UBC_H */
diff --git a/include/asm-sh/ucontext.h b/include/asm-sh/ucontext.h
new file mode 100644
index 000000000000..202ef1d5a3c4
--- /dev/null
+++ b/include/asm-sh/ucontext.h
@@ -0,0 +1,12 @@
1#ifndef __ASM_SH_UCONTEXT_H
2#define __ASM_SH_UCONTEXT_H
3
4struct ucontext {
5 unsigned long uc_flags;
6 struct ucontext *uc_link;
7 stack_t uc_stack;
8 struct sigcontext uc_mcontext;
9 sigset_t uc_sigmask; /* mask last for extensibility */
10};
11
12#endif /* __ASM_SH_UCONTEXT_H */
diff --git a/include/asm-sh/unaligned.h b/include/asm-sh/unaligned.h
new file mode 100644
index 000000000000..5250e3063b42
--- /dev/null
+++ b/include/asm-sh/unaligned.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_SH_UNALIGNED_H
2#define __ASM_SH_UNALIGNED_H
3
4/* SH can't handle unaligned accesses. */
5#include <asm-generic/unaligned.h>
6
7#endif /* __ASM_SH_UNALIGNED_H */
diff --git a/include/asm-sh/unistd.h b/include/asm-sh/unistd.h
new file mode 100644
index 000000000000..245447081f0d
--- /dev/null
+++ b/include/asm-sh/unistd.h
@@ -0,0 +1,523 @@
1#ifndef __ASM_SH_UNISTD_H
2#define __ASM_SH_UNISTD_H
3
4/*
5 * Copyright (C) 1999 Niibe Yutaka
6 */
7
8/*
9 * This file contains the system call numbers.
10 */
11
12#define __NR_restart_syscall 0
13#define __NR_exit 1
14#define __NR_fork 2
15#define __NR_read 3
16#define __NR_write 4
17#define __NR_open 5
18#define __NR_close 6
19#define __NR_waitpid 7
20#define __NR_creat 8
21#define __NR_link 9
22#define __NR_unlink 10
23#define __NR_execve 11
24#define __NR_chdir 12
25#define __NR_time 13
26#define __NR_mknod 14
27#define __NR_chmod 15
28#define __NR_lchown 16
29#define __NR_break 17
30#define __NR_oldstat 18
31#define __NR_lseek 19
32#define __NR_getpid 20
33#define __NR_mount 21
34#define __NR_umount 22
35#define __NR_setuid 23
36#define __NR_getuid 24
37#define __NR_stime 25
38#define __NR_ptrace 26
39#define __NR_alarm 27
40#define __NR_oldfstat 28
41#define __NR_pause 29
42#define __NR_utime 30
43#define __NR_stty 31
44#define __NR_gtty 32
45#define __NR_access 33
46#define __NR_nice 34
47#define __NR_ftime 35
48#define __NR_sync 36
49#define __NR_kill 37
50#define __NR_rename 38
51#define __NR_mkdir 39
52#define __NR_rmdir 40
53#define __NR_dup 41
54#define __NR_pipe 42
55#define __NR_times 43
56#define __NR_prof 44
57#define __NR_brk 45
58#define __NR_setgid 46
59#define __NR_getgid 47
60#define __NR_signal 48
61#define __NR_geteuid 49
62#define __NR_getegid 50
63#define __NR_acct 51
64#define __NR_umount2 52
65#define __NR_lock 53
66#define __NR_ioctl 54
67#define __NR_fcntl 55
68#define __NR_mpx 56
69#define __NR_setpgid 57
70#define __NR_ulimit 58
71#define __NR_oldolduname 59
72#define __NR_umask 60
73#define __NR_chroot 61
74#define __NR_ustat 62
75#define __NR_dup2 63
76#define __NR_getppid 64
77#define __NR_getpgrp 65
78#define __NR_setsid 66
79#define __NR_sigaction 67
80#define __NR_sgetmask 68
81#define __NR_ssetmask 69
82#define __NR_setreuid 70
83#define __NR_setregid 71
84#define __NR_sigsuspend 72
85#define __NR_sigpending 73
86#define __NR_sethostname 74
87#define __NR_setrlimit 75
88#define __NR_getrlimit 76 /* Back compatible 2Gig limited rlimit */
89#define __NR_getrusage 77
90#define __NR_gettimeofday 78
91#define __NR_settimeofday 79
92#define __NR_getgroups 80
93#define __NR_setgroups 81
94#define __NR_select 82
95#define __NR_symlink 83
96#define __NR_oldlstat 84
97#define __NR_readlink 85
98#define __NR_uselib 86
99#define __NR_swapon 87
100#define __NR_reboot 88
101#define __NR_readdir 89
102#define __NR_mmap 90
103#define __NR_munmap 91
104#define __NR_truncate 92
105#define __NR_ftruncate 93
106#define __NR_fchmod 94
107#define __NR_fchown 95
108#define __NR_getpriority 96
109#define __NR_setpriority 97
110#define __NR_profil 98
111#define __NR_statfs 99
112#define __NR_fstatfs 100
113#define __NR_ioperm 101
114#define __NR_socketcall 102
115#define __NR_syslog 103
116#define __NR_setitimer 104
117#define __NR_getitimer 105
118#define __NR_stat 106
119#define __NR_lstat 107
120#define __NR_fstat 108
121#define __NR_olduname 109
122#define __NR_iopl 110
123#define __NR_vhangup 111
124#define __NR_idle 112
125#define __NR_vm86old 113
126#define __NR_wait4 114
127#define __NR_swapoff 115
128#define __NR_sysinfo 116
129#define __NR_ipc 117
130#define __NR_fsync 118
131#define __NR_sigreturn 119
132#define __NR_clone 120
133#define __NR_setdomainname 121
134#define __NR_uname 122
135#define __NR_modify_ldt 123
136#define __NR_adjtimex 124
137#define __NR_mprotect 125
138#define __NR_sigprocmask 126
139#define __NR_create_module 127
140#define __NR_init_module 128
141#define __NR_delete_module 129
142#define __NR_get_kernel_syms 130
143#define __NR_quotactl 131
144#define __NR_getpgid 132
145#define __NR_fchdir 133
146#define __NR_bdflush 134
147#define __NR_sysfs 135
148#define __NR_personality 136
149#define __NR_afs_syscall 137 /* Syscall for Andrew File System */
150#define __NR_setfsuid 138
151#define __NR_setfsgid 139
152#define __NR__llseek 140
153#define __NR_getdents 141
154#define __NR__newselect 142
155#define __NR_flock 143
156#define __NR_msync 144
157#define __NR_readv 145
158#define __NR_writev 146
159#define __NR_getsid 147
160#define __NR_fdatasync 148
161#define __NR__sysctl 149
162#define __NR_mlock 150
163#define __NR_munlock 151
164#define __NR_mlockall 152
165#define __NR_munlockall 153
166#define __NR_sched_setparam 154
167#define __NR_sched_getparam 155
168#define __NR_sched_setscheduler 156
169#define __NR_sched_getscheduler 157
170#define __NR_sched_yield 158
171#define __NR_sched_get_priority_max 159
172#define __NR_sched_get_priority_min 160
173#define __NR_sched_rr_get_interval 161
174#define __NR_nanosleep 162
175#define __NR_mremap 163
176#define __NR_setresuid 164
177#define __NR_getresuid 165
178#define __NR_vm86 166
179#define __NR_query_module 167
180#define __NR_poll 168
181#define __NR_nfsservctl 169
182#define __NR_setresgid 170
183#define __NR_getresgid 171
184#define __NR_prctl 172
185#define __NR_rt_sigreturn 173
186#define __NR_rt_sigaction 174
187#define __NR_rt_sigprocmask 175
188#define __NR_rt_sigpending 176
189#define __NR_rt_sigtimedwait 177
190#define __NR_rt_sigqueueinfo 178
191#define __NR_rt_sigsuspend 179
192#define __NR_pread64 180
193#define __NR_pwrite64 181
194#define __NR_chown 182
195#define __NR_getcwd 183
196#define __NR_capget 184
197#define __NR_capset 185
198#define __NR_sigaltstack 186
199#define __NR_sendfile 187
200#define __NR_streams1 188 /* some people actually want it */
201#define __NR_streams2 189 /* some people actually want it */
202#define __NR_vfork 190
203#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */
204#define __NR_mmap2 192
205#define __NR_truncate64 193
206#define __NR_ftruncate64 194
207#define __NR_stat64 195
208#define __NR_lstat64 196
209#define __NR_fstat64 197
210#define __NR_lchown32 198
211#define __NR_getuid32 199
212#define __NR_getgid32 200
213#define __NR_geteuid32 201
214#define __NR_getegid32 202
215#define __NR_setreuid32 203
216#define __NR_setregid32 204
217#define __NR_getgroups32 205
218#define __NR_setgroups32 206
219#define __NR_fchown32 207
220#define __NR_setresuid32 208
221#define __NR_getresuid32 209
222#define __NR_setresgid32 210
223#define __NR_getresgid32 211
224#define __NR_chown32 212
225#define __NR_setuid32 213
226#define __NR_setgid32 214
227#define __NR_setfsuid32 215
228#define __NR_setfsgid32 216
229#define __NR_pivot_root 217
230#define __NR_mincore 218
231#define __NR_madvise 219
232#define __NR_getdents64 220
233#define __NR_fcntl64 221
234/* 223 is unused */
235#define __NR_gettid 224
236#define __NR_setxattr 226
237#define __NR_lsetxattr 227
238#define __NR_fsetxattr 228
239#define __NR_getxattr 229
240#define __NR_lgetxattr 230
241#define __NR_fgetxattr 231
242#define __NR_listxattr 232
243#define __NR_llistxattr 233
244#define __NR_flistxattr 234
245#define __NR_removexattr 235
246#define __NR_lremovexattr 236
247#define __NR_fremovexattr 237
248#define __NR_tkill 238
249#define __NR_sendfile64 239
250#define __NR_futex 240
251#define __NR_sched_setaffinity 241
252#define __NR_sched_getaffinity 242
253#define __NR_set_thread_area 243
254#define __NR_get_thread_area 244
255#define __NR_io_setup 245
256#define __NR_io_destroy 246
257#define __NR_io_getevents 247
258#define __NR_io_submit 248
259#define __NR_io_cancel 249
260#define __NR_fadvise64 250
261
262#define __NR_exit_group 252
263#define __NR_lookup_dcookie 253
264#define __NR_epoll_create 254
265#define __NR_epoll_ctl 255
266#define __NR_epoll_wait 256
267#define __NR_remap_file_pages 257
268#define __NR_set_tid_address 258
269#define __NR_timer_create 259
270#define __NR_timer_settime (__NR_timer_create+1)
271#define __NR_timer_gettime (__NR_timer_create+2)
272#define __NR_timer_getoverrun (__NR_timer_create+3)
273#define __NR_timer_delete (__NR_timer_create+4)
274#define __NR_clock_settime (__NR_timer_create+5)
275#define __NR_clock_gettime (__NR_timer_create+6)
276#define __NR_clock_getres (__NR_timer_create+7)
277#define __NR_clock_nanosleep (__NR_timer_create+8)
278#define __NR_statfs64 268
279#define __NR_fstatfs64 269
280#define __NR_tgkill 270
281#define __NR_utimes 271
282#define __NR_fadvise64_64 272
283#define __NR_vserver 273
284#define __NR_mbind 274
285#define __NR_get_mempolicy 275
286#define __NR_set_mempolicy 276
287#define __NR_mq_open 277
288#define __NR_mq_unlink (__NR_mq_open+1)
289#define __NR_mq_timedsend (__NR_mq_open+2)
290#define __NR_mq_timedreceive (__NR_mq_open+3)
291#define __NR_mq_notify (__NR_mq_open+4)
292#define __NR_mq_getsetattr (__NR_mq_open+5)
293#define __NR_sys_kexec_load 283
294#define __NR_waitid 284
295#define __NR_add_key 285
296#define __NR_request_key 286
297#define __NR_keyctl 287
298
299#define NR_syscalls 288
300
301/* user-visible error numbers are in the range -1 - -124: see <asm-sh/errno.h> */
302
303#define __syscall_return(type, res) \
304do { \
305 if ((unsigned long)(res) >= (unsigned long)(-124)) { \
306 /* Avoid using "res" which is declared to be in register r0; \
307 errno might expand to a function call and clobber it. */ \
308 int __err = -(res); \
309 errno = __err; \
310 res = -1; \
311 } \
312 return (type) (res); \
313} while (0)
314
315/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
316#define _syscall0(type,name) \
317type name(void) \
318{ \
319register long __sc0 __asm__ ("r3") = __NR_##name; \
320__asm__ __volatile__ ("trapa #0x10" \
321 : "=z" (__sc0) \
322 : "0" (__sc0) \
323 : "memory" ); \
324__syscall_return(type,__sc0); \
325}
326
327#define _syscall1(type,name,type1,arg1) \
328type name(type1 arg1) \
329{ \
330register long __sc0 __asm__ ("r3") = __NR_##name; \
331register long __sc4 __asm__ ("r4") = (long) arg1; \
332__asm__ __volatile__ ("trapa #0x11" \
333 : "=z" (__sc0) \
334 : "0" (__sc0), "r" (__sc4) \
335 : "memory"); \
336__syscall_return(type,__sc0); \
337}
338
339#define _syscall2(type,name,type1,arg1,type2,arg2) \
340type name(type1 arg1,type2 arg2) \
341{ \
342register long __sc0 __asm__ ("r3") = __NR_##name; \
343register long __sc4 __asm__ ("r4") = (long) arg1; \
344register long __sc5 __asm__ ("r5") = (long) arg2; \
345__asm__ __volatile__ ("trapa #0x12" \
346 : "=z" (__sc0) \
347 : "0" (__sc0), "r" (__sc4), "r" (__sc5) \
348 : "memory"); \
349__syscall_return(type,__sc0); \
350}
351
352#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \
353type name(type1 arg1,type2 arg2,type3 arg3) \
354{ \
355register long __sc0 __asm__ ("r3") = __NR_##name; \
356register long __sc4 __asm__ ("r4") = (long) arg1; \
357register long __sc5 __asm__ ("r5") = (long) arg2; \
358register long __sc6 __asm__ ("r6") = (long) arg3; \
359__asm__ __volatile__ ("trapa #0x13" \
360 : "=z" (__sc0) \
361 : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6) \
362 : "memory"); \
363__syscall_return(type,__sc0); \
364}
365
366#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
367type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \
368{ \
369register long __sc0 __asm__ ("r3") = __NR_##name; \
370register long __sc4 __asm__ ("r4") = (long) arg1; \
371register long __sc5 __asm__ ("r5") = (long) arg2; \
372register long __sc6 __asm__ ("r6") = (long) arg3; \
373register long __sc7 __asm__ ("r7") = (long) arg4; \
374__asm__ __volatile__ ("trapa #0x14" \
375 : "=z" (__sc0) \
376 : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), \
377 "r" (__sc7) \
378 : "memory" ); \
379__syscall_return(type,__sc0); \
380}
381
382#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \
383type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) \
384{ \
385register long __sc3 __asm__ ("r3") = __NR_##name; \
386register long __sc4 __asm__ ("r4") = (long) arg1; \
387register long __sc5 __asm__ ("r5") = (long) arg2; \
388register long __sc6 __asm__ ("r6") = (long) arg3; \
389register long __sc7 __asm__ ("r7") = (long) arg4; \
390register long __sc0 __asm__ ("r0") = (long) arg5; \
391__asm__ __volatile__ ("trapa #0x15" \
392 : "=z" (__sc0) \
393 : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7), \
394 "r" (__sc3) \
395 : "memory" ); \
396__syscall_return(type,__sc0); \
397}
398
399#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5,type6,arg6) \
400type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6) \
401{ \
402register long __sc3 __asm__ ("r3") = __NR_##name; \
403register long __sc4 __asm__ ("r4") = (long) arg1; \
404register long __sc5 __asm__ ("r5") = (long) arg2; \
405register long __sc6 __asm__ ("r6") = (long) arg3; \
406register long __sc7 __asm__ ("r7") = (long) arg4; \
407register long __sc0 __asm__ ("r0") = (long) arg5; \
408register long __sc1 __asm__ ("r1") = (long) arg6; \
409__asm__ __volatile__ ("trapa #0x15" \
410 : "=z" (__sc0) \
411 : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7), \
412 "r" (__sc3), "r" (__sc1) \
413 : "memory" ); \
414__syscall_return(type,__sc0); \
415}
416
417#ifdef __KERNEL__
418#define __ARCH_WANT_IPC_PARSE_VERSION
419#define __ARCH_WANT_OLD_READDIR
420#define __ARCH_WANT_OLD_STAT
421#define __ARCH_WANT_STAT64
422#define __ARCH_WANT_SYS_ALARM
423#define __ARCH_WANT_SYS_GETHOSTNAME
424#define __ARCH_WANT_SYS_PAUSE
425#define __ARCH_WANT_SYS_SGETMASK
426#define __ARCH_WANT_SYS_SIGNAL
427#define __ARCH_WANT_SYS_TIME
428#define __ARCH_WANT_SYS_UTIME
429#define __ARCH_WANT_SYS_WAITPID
430#define __ARCH_WANT_SYS_SOCKETCALL
431#define __ARCH_WANT_SYS_FADVISE64
432#define __ARCH_WANT_SYS_GETPGRP
433#define __ARCH_WANT_SYS_LLSEEK
434#define __ARCH_WANT_SYS_NICE
435#define __ARCH_WANT_SYS_OLD_GETRLIMIT
436#define __ARCH_WANT_SYS_OLDUMOUNT
437#define __ARCH_WANT_SYS_SIGPENDING
438#define __ARCH_WANT_SYS_SIGPROCMASK
439#define __ARCH_WANT_SYS_RT_SIGACTION
440#endif
441
442#ifdef __KERNEL_SYSCALLS__
443
444#include <linux/compiler.h>
445#include <linux/types.h>
446#include <linux/linkage.h>
447#include <asm/ptrace.h>
448
449/*
450 * we need this inline - forking from kernel space will result
451 * in NO COPY ON WRITE (!!!), until an execve is executed. This
452 * is no problem, but for the stack. This is handled by not letting
453 * main() use the stack at all after fork(). Thus, no function
454 * calls - which means inline code for fork too, as otherwise we
455 * would use the stack upon exit from 'fork()'.
456 *
457 * Actually only pause and fork are needed inline, so that there
458 * won't be any messing with the stack from main(), but we define
459 * some others too.
460 */
461#define __NR__exit __NR_exit
462static __inline__ _syscall0(int,pause)
463static __inline__ _syscall0(int,sync)
464static __inline__ _syscall0(pid_t,setsid)
465static __inline__ _syscall3(int,write,int,fd,const char *,buf,off_t,count)
466static __inline__ _syscall3(int,read,int,fd,char *,buf,off_t,count)
467static __inline__ _syscall3(off_t,lseek,int,fd,off_t,offset,int,count)
468static __inline__ _syscall1(int,dup,int,fd)
469static __inline__ _syscall3(int,execve,const char *,file,char **,argv,char **,envp)
470static __inline__ _syscall3(int,open,const char *,file,int,flag,int,mode)
471static __inline__ _syscall1(int,close,int,fd)
472static __inline__ _syscall3(pid_t,waitpid,pid_t,pid,int *,wait_stat,int,options)
473static __inline__ _syscall1(int,delete_module,const char *,name)
474
475static __inline__ pid_t wait(int * wait_stat)
476{
477 return waitpid(-1,wait_stat,0);
478}
479
480asmlinkage long sys_mmap2(
481 unsigned long addr, unsigned long len,
482 unsigned long prot, unsigned long flags,
483 unsigned long fd, unsigned long pgoff);
484asmlinkage int sys_execve(char *ufilename, char **uargv,
485 char **uenvp, unsigned long r7,
486 struct pt_regs regs);
487asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp,
488 unsigned long parent_tidptr,
489 unsigned long child_tidptr,
490 struct pt_regs regs);
491asmlinkage int sys_fork(unsigned long r4, unsigned long r5,
492 unsigned long r6, unsigned long r7,
493 struct pt_regs regs);
494asmlinkage int sys_vfork(unsigned long r4, unsigned long r5,
495 unsigned long r6, unsigned long r7,
496 struct pt_regs regs);
497asmlinkage int sys_pipe(unsigned long r4, unsigned long r5,
498 unsigned long r6, unsigned long r7,
499 struct pt_regs regs);
500asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
501asmlinkage ssize_t sys_pread_wrapper(unsigned int fd, char *buf,
502 size_t count, long dummy, loff_t pos);
503asmlinkage ssize_t sys_pwrite_wrapper(unsigned int fd, const char *buf,
504 size_t count, long dummy, loff_t pos);
505struct sigaction;
506asmlinkage long sys_rt_sigaction(int sig,
507 const struct sigaction __user *act,
508 struct sigaction __user *oact,
509 size_t sigsetsize);
510
511#endif
512
513/*
514 * "Conditional" syscalls
515 *
516 * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
517 * but it doesn't work on all toolchains, so we just do it by hand
518 */
519#ifndef cond_syscall
520#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
521#endif
522
523#endif /* __ASM_SH_UNISTD_H */
diff --git a/include/asm-sh/user.h b/include/asm-sh/user.h
new file mode 100644
index 000000000000..d1b8511d9d9f
--- /dev/null
+++ b/include/asm-sh/user.h
@@ -0,0 +1,60 @@
1#ifndef __ASM_SH_USER_H
2#define __ASM_SH_USER_H
3
4#include <asm/ptrace.h>
5#include <asm/page.h>
6
7/*
8 * Core file format: The core file is written in such a way that gdb
9 * can understand it and provide useful information to the user (under
10 * linux we use the `trad-core' bfd). The file contents are as follows:
11 *
12 * upage: 1 page consisting of a user struct that tells gdb
13 * what is present in the file. Directly after this is a
14 * copy of the task_struct, which is currently not used by gdb,
15 * but it may come in handy at some point. All of the registers
16 * are stored as part of the upage. The upage should always be
17 * only one page long.
18 * data: The data segment follows next. We use current->end_text to
19 * current->brk to pick up all of the user variables, plus any memory
20 * that may have been sbrk'ed. No attempt is made to determine if a
21 * page is demand-zero or if a page is totally unused, we just cover
22 * the entire range. All of the addresses are rounded in such a way
23 * that an integral number of pages is written.
24 * stack: We need the stack information in order to get a meaningful
25 * backtrace. We need to write the data from usp to
26 * current->start_stack, so we round each of these in order to be able
27 * to write an integer number of pages.
28 */
29
30struct user_fpu_struct {
31 unsigned long fp_regs[16];
32 unsigned long xfp_regs[16];
33 unsigned long fpscr;
34 unsigned long fpul;
35};
36
37struct user {
38 struct pt_regs regs; /* entire machine state */
39 struct user_fpu_struct fpu; /* Math Co-processor registers */
40 int u_fpvalid; /* True if math co-processor being used */
41 size_t u_tsize; /* text size (pages) */
42 size_t u_dsize; /* data size (pages) */
43 size_t u_ssize; /* stack size (pages) */
44 unsigned long start_code; /* text starting address */
45 unsigned long start_data; /* data starting address */
46 unsigned long start_stack; /* stack starting address */
47 long int signal; /* signal causing core dump */
48 struct regs * u_ar0; /* help gdb find registers */
49 struct user_fpu_struct* u_fpstate; /* Math Co-processor pointer */
50 unsigned long magic; /* identifies a core file */
51 char u_comm[32]; /* user command name */
52};
53
54#define NBPG PAGE_SIZE
55#define UPAGES 1
56#define HOST_TEXT_START_ADDR (u.start_code)
57#define HOST_DATA_START_ADDR (u.start_data)
58#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
59
60#endif /* __ASM_SH_USER_H */
diff --git a/include/asm-sh/watchdog.h b/include/asm-sh/watchdog.h
new file mode 100644
index 000000000000..f0cf4be21655
--- /dev/null
+++ b/include/asm-sh/watchdog.h
@@ -0,0 +1,111 @@
1/*
2 * include/asm-sh/watchdog.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11#ifndef __ASM_SH_WATCHDOG_H
12#define __ASM_SH_WATCHDOG_H
13#ifdef __KERNEL__
14
15#include <linux/types.h>
16#include <linux/config.h>
17#include <asm/cpu/watchdog.h>
18#include <asm/io.h>
19
20/*
21 * See asm/cpu-sh2/watchdog.h for explanation of this stupidity..
22 */
23#ifndef WTCNT_R
24# define WTCNT_R WTCNT
25#endif
26
27#ifndef WTCSR_R
28# define WTCSR_R WTCSR
29#endif
30
31#define WTCNT_HIGH 0x5a
32#define WTCSR_HIGH 0xa5
33
34#define WTCSR_CKS2 0x04
35#define WTCSR_CKS1 0x02
36#define WTCSR_CKS0 0x01
37
38/*
39 * CKS0-2 supports a number of clock division ratios. At the time the watchdog
40 * is enabled, it defaults to a 41 usec overflow period .. we overload this to
41 * something a little more reasonable, and really can't deal with anything
42 * lower than WTCSR_CKS_1024, else we drop back into the usec range.
43 *
44 * Clock Division Ratio Overflow Period
45 * --------------------------------------------
46 * 1/32 (initial value) 41 usecs
47 * 1/64 82 usecs
48 * 1/128 164 usecs
49 * 1/256 328 usecs
50 * 1/512 656 usecs
51 * 1/1024 1.31 msecs
52 * 1/2048 2.62 msecs
53 * 1/4096 5.25 msecs
54 */
55#define WTCSR_CKS_32 0x00
56#define WTCSR_CKS_64 0x01
57#define WTCSR_CKS_128 0x02
58#define WTCSR_CKS_256 0x03
59#define WTCSR_CKS_512 0x04
60#define WTCSR_CKS_1024 0x05
61#define WTCSR_CKS_2048 0x06
62#define WTCSR_CKS_4096 0x07
63
64/**
65 * sh_wdt_read_cnt - Read from Counter
66 *
67 * Reads back the WTCNT value.
68 */
69static inline __u8 sh_wdt_read_cnt(void)
70{
71 return ctrl_inb(WTCNT_R);
72}
73
74/**
75 * sh_wdt_write_cnt - Write to Counter
76 *
77 * @val: Value to write
78 *
79 * Writes the given value @val to the lower byte of the timer counter.
80 * The upper byte is set manually on each write.
81 */
82static inline void sh_wdt_write_cnt(__u8 val)
83{
84 ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, WTCNT);
85}
86
87/**
88 * sh_wdt_read_csr - Read from Control/Status Register
89 *
90 * Reads back the WTCSR value.
91 */
92static inline __u8 sh_wdt_read_csr(void)
93{
94 return ctrl_inb(WTCSR_R);
95}
96
97/**
98 * sh_wdt_write_csr - Write to Control/Status Register
99 *
100 * @val: Value to write
101 *
102 * Writes the given value @val to the lower byte of the control/status
103 * register. The upper byte is set manually on each write.
104 */
105static inline void sh_wdt_write_csr(__u8 val)
106{
107 ctrl_outw((WTCSR_HIGH << 8) | (__u16)val, WTCSR);
108}
109
110#endif /* __KERNEL__ */
111#endif /* __ASM_SH_WATCHDOG_H */
diff --git a/include/asm-sh/xor.h b/include/asm-sh/xor.h
new file mode 100644
index 000000000000..c82eb12a5b18
--- /dev/null
+++ b/include/asm-sh/xor.h
@@ -0,0 +1 @@
#include <asm-generic/xor.h>