diff options
Diffstat (limited to 'include/asm-sh')
-rw-r--r-- | include/asm-sh/hd64461.h | 28 | ||||
-rw-r--r-- | include/asm-sh/microdev.h | 4 | ||||
-rw-r--r-- | include/asm-sh/voyagergx.h | 2 |
3 files changed, 17 insertions, 17 deletions
diff --git a/include/asm-sh/hd64461.h b/include/asm-sh/hd64461.h index 342ca55a266a..8c1353baf00f 100644 --- a/include/asm-sh/hd64461.h +++ b/include/asm-sh/hd64461.h | |||
@@ -46,10 +46,10 @@ | |||
46 | /* CPU Data Bus Control Register */ | 46 | /* CPU Data Bus Control Register */ |
47 | #define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x04) | 47 | #define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x04) |
48 | 48 | ||
49 | /* Base Adress Register */ | 49 | /* Base Address Register */ |
50 | #define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x1000) | 50 | #define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x1000) |
51 | 51 | ||
52 | /* Line increment adress */ | 52 | /* Line increment address */ |
53 | #define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x1002) | 53 | #define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x1002) |
54 | 54 | ||
55 | /* Controls LCD controller */ | 55 | /* Controls LCD controller */ |
@@ -80,9 +80,9 @@ | |||
80 | #define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x101e) | 80 | #define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x101e) |
81 | 81 | ||
82 | /* Palette Registers */ | 82 | /* Palette Registers */ |
83 | #define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x1030) /* Color Palette Write Adress Register */ | 83 | #define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x1030) /* Color Palette Write Address Register */ |
84 | #define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x1032) /* Color Palette Write Data Register */ | 84 | #define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x1032) /* Color Palette Write Data Register */ |
85 | #define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x1034) /* Color Palette Read Adress Register */ | 85 | #define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x1034) /* Color Palette Read Address Register */ |
86 | #define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x1036) /* Color Palette Read Data Register */ | 86 | #define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x1036) /* Color Palette Read Data Register */ |
87 | 87 | ||
88 | #define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x1040) /* Display Resolution Offset Register */ | 88 | #define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x1040) /* Display Resolution Offset Register */ |
@@ -97,8 +97,8 @@ | |||
97 | #define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */ | 97 | #define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */ |
98 | 98 | ||
99 | /* Line Drawing Registers */ | 99 | /* Line Drawing Registers */ |
100 | #define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x1046) /* Line Start Adress Register (H) */ | 100 | #define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x1046) /* Line Start Address Register (H) */ |
101 | #define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x1048) /* Line Start Adress Register (L) */ | 101 | #define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x1048) /* Line Start Address Register (L) */ |
102 | #define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x104a) /* Axis Pixel Length Register */ | 102 | #define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x104a) /* Axis Pixel Length Register */ |
103 | #define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x104c) /* Diagonal Register */ | 103 | #define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x104c) /* Diagonal Register */ |
104 | #define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x104e) /* Axial Register */ | 104 | #define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x104e) /* Axial Register */ |
@@ -106,16 +106,16 @@ | |||
106 | #define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x1052) /* Line Mode Register */ | 106 | #define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x1052) /* Line Mode Register */ |
107 | 107 | ||
108 | /* BitBLT Registers */ | 108 | /* BitBLT Registers */ |
109 | #define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x1054) /* Source Start Adress Register (H) */ | 109 | #define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x1054) /* Source Start Address Register (H) */ |
110 | #define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x1056) /* Source Start Adress Register (L) */ | 110 | #define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x1056) /* Source Start Address Register (L) */ |
111 | #define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x1058) /* Destination Start Adress Register (H) */ | 111 | #define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x1058) /* Destination Start Address Register (H) */ |
112 | #define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x105a) /* Destination Start Adress Register (L) */ | 112 | #define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x105a) /* Destination Start Address Register (L) */ |
113 | #define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x105c) /* Destination Block Width Register */ | 113 | #define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x105c) /* Destination Block Width Register */ |
114 | #define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x105e) /* Destination Block Height Register */ | 114 | #define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x105e) /* Destination Block Height Register */ |
115 | #define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x1060) /* Pattern Start Adress Register (H) */ | 115 | #define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x1060) /* Pattern Start Address Register (H) */ |
116 | #define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x1062) /* Pattern Start Adress Register (L) */ | 116 | #define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x1062) /* Pattern Start Address Register (L) */ |
117 | #define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x1064) /* Mask Start Adress Register (H) */ | 117 | #define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x1064) /* Mask Start Address Register (H) */ |
118 | #define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x1066) /* Mask Start Adress Register (L) */ | 118 | #define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x1066) /* Mask Start Address Register (L) */ |
119 | #define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x1068) /* ROP Register */ | 119 | #define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x1068) /* ROP Register */ |
120 | #define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x106a) /* BitBLT Mode Register */ | 120 | #define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x106a) /* BitBLT Mode Register */ |
121 | 121 | ||
diff --git a/include/asm-sh/microdev.h b/include/asm-sh/microdev.h index 018332a9e590..1aed15856e11 100644 --- a/include/asm-sh/microdev.h +++ b/include/asm-sh/microdev.h | |||
@@ -17,7 +17,7 @@ extern void microdev_print_fpga_intc_status(void); | |||
17 | /* | 17 | /* |
18 | * The following are useful macros for manipulating the interrupt | 18 | * The following are useful macros for manipulating the interrupt |
19 | * controller (INTC) on the CPU-board FPGA. should be noted that there | 19 | * controller (INTC) on the CPU-board FPGA. should be noted that there |
20 | * is an INTC on the FPGA, and a seperate INTC on the SH4-202 core - | 20 | * is an INTC on the FPGA, and a separate INTC on the SH4-202 core - |
21 | * these are two different things, both of which need to be prorammed to | 21 | * these are two different things, both of which need to be prorammed to |
22 | * correctly route - unfortunately, they have the same name and | 22 | * correctly route - unfortunately, they have the same name and |
23 | * abbreviations! | 23 | * abbreviations! |
@@ -25,7 +25,7 @@ extern void microdev_print_fpga_intc_status(void); | |||
25 | #define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */ | 25 | #define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */ |
26 | #define MICRODEV_FPGA_INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */ | 26 | #define MICRODEV_FPGA_INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */ |
27 | #define MICRODEV_FPGA_INTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */ | 27 | #define MICRODEV_FPGA_INTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */ |
28 | #define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interupt mask to enable/disable INTC in CPU-board FPGA */ | 28 | #define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-board FPGA */ |
29 | #define MICRODEV_FPGA_INTPRI_REG(n) (MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */ | 29 | #define MICRODEV_FPGA_INTPRI_REG(n) (MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */ |
30 | #define MICRODEV_FPGA_INTPRI_LEVEL(n,x) ((x)<<(((n)%8)*4)) /* MICRODEV_FPGA_INTPRI_LEVEL(int_number, int_level) */ | 30 | #define MICRODEV_FPGA_INTPRI_LEVEL(n,x) ((x)<<(((n)%8)*4)) /* MICRODEV_FPGA_INTPRI_LEVEL(int_number, int_level) */ |
31 | #define MICRODEV_FPGA_INTPRI_MASK(n) (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */ | 31 | #define MICRODEV_FPGA_INTPRI_MASK(n) (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */ |
diff --git a/include/asm-sh/voyagergx.h b/include/asm-sh/voyagergx.h index d825596562df..45b4547c74ac 100644 --- a/include/asm-sh/voyagergx.h +++ b/include/asm-sh/voyagergx.h | |||
@@ -213,7 +213,7 @@ | |||
213 | /* ----- Power mode 1 clock register -------------------------- */ | 213 | /* ----- Power mode 1 clock register -------------------------- */ |
214 | #define POWER_MODE1_CLOCK (0x00004C + VOYAGER_BASE) | 214 | #define POWER_MODE1_CLOCK (0x00004C + VOYAGER_BASE) |
215 | 215 | ||
216 | /* ----- Power mode controll register ------------------------- */ | 216 | /* ----- Power mode control register ------------------------- */ |
217 | #define POWER_MODE_CTRL (0x000054 + VOYAGER_BASE) | 217 | #define POWER_MODE_CTRL (0x000054 + VOYAGER_BASE) |
218 | 218 | ||
219 | /* ----- Miscellaneous Timing register ------------------------ */ | 219 | /* ----- Miscellaneous Timing register ------------------------ */ |