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-rw-r--r--include/asm-sh/bus-sh.h1
-rw-r--r--include/asm-sh/cpu-sh3/dma.h31
-rw-r--r--include/asm-sh/cpu-sh4/dma.h52
-rw-r--r--include/asm-sh/dma-mapping.h25
-rw-r--r--include/asm-sh/dma.h14
5 files changed, 97 insertions, 26 deletions
diff --git a/include/asm-sh/bus-sh.h b/include/asm-sh/bus-sh.h
index 83c5d2fd057f..e42d63b65cb5 100644
--- a/include/asm-sh/bus-sh.h
+++ b/include/asm-sh/bus-sh.h
@@ -21,6 +21,7 @@ struct sh_dev {
21 void *mapbase; 21 void *mapbase;
22 unsigned int irq[6]; 22 unsigned int irq[6];
23 u64 *dma_mask; 23 u64 *dma_mask;
24 u64 coherent_dma_mask;
24}; 25};
25 26
26#define to_sh_dev(d) container_of((d), struct sh_dev, dev) 27#define to_sh_dev(d) container_of((d), struct sh_dev, dev)
diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h
index b972e715f9ee..954801b46022 100644
--- a/include/asm-sh/cpu-sh3/dma.h
+++ b/include/asm-sh/cpu-sh3/dma.h
@@ -3,5 +3,34 @@
3 3
4#define SH_DMAC_BASE 0xa4000020 4#define SH_DMAC_BASE 0xa4000020
5 5
6#endif /* __ASM_CPU_SH3_DMA_H */ 6/* Definitions for the SuperH DMAC */
7#define TM_BURST 0x00000020
8#define TS_8 0x00000000
9#define TS_16 0x00000008
10#define TS_32 0x00000010
11#define TS_128 0x00000018
12
13#define CHCR_TS_MASK 0x18
14#define CHCR_TS_SHIFT 3
15
16#define DMAOR_INIT DMAOR_DME
7 17
18/*
19 * The SuperH DMAC supports a number of transmit sizes, we list them here,
20 * with their respective values as they appear in the CHCR registers.
21 */
22enum {
23 XMIT_SZ_8BIT,
24 XMIT_SZ_16BIT,
25 XMIT_SZ_32BIT,
26 XMIT_SZ_128BIT,
27};
28
29static unsigned int ts_shift[] __attribute__ ((used)) = {
30 [XMIT_SZ_8BIT] = 0,
31 [XMIT_SZ_16BIT] = 1,
32 [XMIT_SZ_32BIT] = 2,
33 [XMIT_SZ_128BIT] = 4,
34};
35
36#endif /* __ASM_CPU_SH3_DMA_H */
diff --git a/include/asm-sh/cpu-sh4/dma.h b/include/asm-sh/cpu-sh4/dma.h
index e2b91adf821a..0dfe61f14802 100644
--- a/include/asm-sh/cpu-sh4/dma.h
+++ b/include/asm-sh/cpu-sh4/dma.h
@@ -1,17 +1,49 @@
1#ifndef __ASM_CPU_SH4_DMA_H 1#ifndef __ASM_CPU_SH4_DMA_H
2#define __ASM_CPU_SH4_DMA_H 2#define __ASM_CPU_SH4_DMA_H
3 3
4#ifdef CONFIG_CPU_SH4A
5#define SH_DMAC_BASE 0xfc808020
6#else
4#define SH_DMAC_BASE 0xffa00000 7#define SH_DMAC_BASE 0xffa00000
8#endif
5 9
6#define SAR ((unsigned long[]){SH_DMAC_BASE + 0x00, SH_DMAC_BASE + 0x10, \ 10/* Definitions for the SuperH DMAC */
7 SH_DMAC_BASE + 0x20, SH_DMAC_BASE + 0x30}) 11#define TM_BURST 0x0000080
8#define DAR ((unsigned long[]){SH_DMAC_BASE + 0x04, SH_DMAC_BASE + 0x14, \ 12#define TS_8 0x00000010
9 SH_DMAC_BASE + 0x24, SH_DMAC_BASE + 0x34}) 13#define TS_16 0x00000020
10#define DMATCR ((unsigned long[]){SH_DMAC_BASE + 0x08, SH_DMAC_BASE + 0x18, \ 14#define TS_32 0x00000030
11 SH_DMAC_BASE + 0x28, SH_DMAC_BASE + 0x38}) 15#define TS_64 0x00000000
12#define CHCR ((unsigned long[]){SH_DMAC_BASE + 0x0c, SH_DMAC_BASE + 0x1c, \
13 SH_DMAC_BASE + 0x2c, SH_DMAC_BASE + 0x3c})
14#define DMAOR (SH_DMAC_BASE + 0x40)
15 16
16#endif /* __ASM_CPU_SH4_DMA_H */ 17#define CHCR_TS_MASK 0x30
18#define CHCR_TS_SHIFT 4
19
20#define DMAOR_COD 0x00000008
21
22#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
17 23
24/*
25 * The SuperH DMAC supports a number of transmit sizes, we list them here,
26 * with their respective values as they appear in the CHCR registers.
27 *
28 * Defaults to a 64-bit transfer size.
29 */
30enum {
31 XMIT_SZ_64BIT,
32 XMIT_SZ_8BIT,
33 XMIT_SZ_16BIT,
34 XMIT_SZ_32BIT,
35 XMIT_SZ_256BIT,
36};
37
38/*
39 * The DMA count is defined as the number of bytes to transfer.
40 */
41static unsigned int ts_shift[] __attribute__ ((used)) = {
42 [XMIT_SZ_64BIT] = 3,
43 [XMIT_SZ_8BIT] = 0,
44 [XMIT_SZ_16BIT] = 1,
45 [XMIT_SZ_32BIT] = 2,
46 [XMIT_SZ_256BIT] = 5,
47};
48
49#endif /* __ASM_CPU_SH4_DMA_H */
diff --git a/include/asm-sh/dma-mapping.h b/include/asm-sh/dma-mapping.h
index d3fa5c2b889d..48f1f42c5d14 100644
--- a/include/asm-sh/dma-mapping.h
+++ b/include/asm-sh/dma-mapping.h
@@ -4,6 +4,7 @@
4#include <linux/config.h> 4#include <linux/config.h>
5#include <linux/mm.h> 5#include <linux/mm.h>
6#include <asm/scatterlist.h> 6#include <asm/scatterlist.h>
7#include <asm/cacheflush.h>
7#include <asm/io.h> 8#include <asm/io.h>
8 9
9extern struct bus_type pci_bus_type; 10extern struct bus_type pci_bus_type;
@@ -141,24 +142,24 @@ static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg,
141 } 142 }
142} 143}
143 144
144static inline void dma_sync_single_for_cpu(struct device *dev, 145static void dma_sync_single_for_cpu(struct device *dev,
145 dma_addr_t dma_handle, size_t size, 146 dma_addr_t dma_handle, size_t size,
146 enum dma_data_direction dir) 147 enum dma_data_direction dir)
147 __attribute__ ((alias("dma_sync_single"))); 148 __attribute__ ((alias("dma_sync_single")));
148 149
149static inline void dma_sync_single_for_device(struct device *dev, 150static void dma_sync_single_for_device(struct device *dev,
150 dma_addr_t dma_handle, size_t size, 151 dma_addr_t dma_handle, size_t size,
151 enum dma_data_direction dir) 152 enum dma_data_direction dir)
152 __attribute__ ((alias("dma_sync_single"))); 153 __attribute__ ((alias("dma_sync_single")));
153 154
154static inline void dma_sync_sg_for_cpu(struct device *dev, 155static void dma_sync_sg_for_cpu(struct device *dev,
155 struct scatterlist *sg, int nelems, 156 struct scatterlist *sg, int nelems,
156 enum dma_data_direction dir) 157 enum dma_data_direction dir)
157 __attribute__ ((alias("dma_sync_sg"))); 158 __attribute__ ((alias("dma_sync_sg")));
158 159
159static inline void dma_sync_sg_for_device(struct device *dev, 160static void dma_sync_sg_for_device(struct device *dev,
160 struct scatterlist *sg, int nelems, 161 struct scatterlist *sg, int nelems,
161 enum dma_data_direction dir) 162 enum dma_data_direction dir)
162 __attribute__ ((alias("dma_sync_sg"))); 163 __attribute__ ((alias("dma_sync_sg")));
163 164
164static inline int dma_get_cache_alignment(void) 165static inline int dma_get_cache_alignment(void)
diff --git a/include/asm-sh/dma.h b/include/asm-sh/dma.h
index 8e9436093ca8..a118a0d43053 100644
--- a/include/asm-sh/dma.h
+++ b/include/asm-sh/dma.h
@@ -15,6 +15,7 @@
15#include <linux/spinlock.h> 15#include <linux/spinlock.h>
16#include <linux/wait.h> 16#include <linux/wait.h>
17#include <linux/sysdev.h> 17#include <linux/sysdev.h>
18#include <linux/device.h>
18#include <asm/cpu/dma.h> 19#include <asm/cpu/dma.h>
19#include <asm/semaphore.h> 20#include <asm/semaphore.h>
20 21
@@ -54,8 +55,8 @@ enum {
54 * DMA channel capabilities / flags 55 * DMA channel capabilities / flags
55 */ 56 */
56enum { 57enum {
57 DMA_CONFIGURED = 0x00,
58 DMA_TEI_CAPABLE = 0x01, 58 DMA_TEI_CAPABLE = 0x01,
59 DMA_CONFIGURED = 0x02,
59}; 60};
60 61
61extern spinlock_t dma_spin_lock; 62extern spinlock_t dma_spin_lock;
@@ -74,7 +75,8 @@ struct dma_ops {
74struct dma_channel { 75struct dma_channel {
75 char dev_id[16]; 76 char dev_id[16];
76 77
77 unsigned int chan; 78 unsigned int chan; /* Physical channel number */
79 unsigned int vchan; /* Virtual channel number */
78 unsigned int mode; 80 unsigned int mode;
79 unsigned int count; 81 unsigned int count;
80 82
@@ -91,6 +93,8 @@ struct dma_channel {
91}; 93};
92 94
93struct dma_info { 95struct dma_info {
96 struct platform_device *pdev;
97
94 const char *name; 98 const char *name;
95 unsigned int nr_channels; 99 unsigned int nr_channels;
96 unsigned long flags; 100 unsigned long flags;
@@ -130,7 +134,11 @@ extern void unregister_dmac(struct dma_info *info);
130 134
131#ifdef CONFIG_SYSFS 135#ifdef CONFIG_SYSFS
132/* arch/sh/drivers/dma/dma-sysfs.c */ 136/* arch/sh/drivers/dma/dma-sysfs.c */
133extern int dma_create_sysfs_files(struct dma_channel *); 137extern int dma_create_sysfs_files(struct dma_channel *, struct dma_info *);
138extern void dma_remove_sysfs_files(struct dma_channel *, struct dma_info *);
139#else
140#define dma_create_sysfs_file(channel, info) do { } while (0)
141#define dma_remove_sysfs_file(channel, info) do { } while (0)
134#endif 142#endif
135 143
136#ifdef CONFIG_PCI 144#ifdef CONFIG_PCI
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 18:13:27 -0500