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-rw-r--r--include/asm-sh/bus-sh.h1
-rw-r--r--include/asm-sh/clock.h61
-rw-r--r--include/asm-sh/cpu-sh3/dma.h31
-rw-r--r--include/asm-sh/cpu-sh4/dma.h52
-rw-r--r--include/asm-sh/cpu-sh4/freq.h2
-rw-r--r--include/asm-sh/dma-mapping.h25
-rw-r--r--include/asm-sh/dma.h14
-rw-r--r--include/asm-sh/freq.h11
-rw-r--r--include/asm-sh/io.h283
-rw-r--r--include/asm-sh/io_generic.h96
-rw-r--r--include/asm-sh/irq-sh7780.h349
-rw-r--r--include/asm-sh/irq.h143
-rw-r--r--include/asm-sh/kexec.h33
-rw-r--r--include/asm-sh/machvec.h66
-rw-r--r--include/asm-sh/timer.h42
15 files changed, 906 insertions, 303 deletions
diff --git a/include/asm-sh/bus-sh.h b/include/asm-sh/bus-sh.h
index 83c5d2fd057f..e42d63b65cb5 100644
--- a/include/asm-sh/bus-sh.h
+++ b/include/asm-sh/bus-sh.h
@@ -21,6 +21,7 @@ struct sh_dev {
21 void *mapbase; 21 void *mapbase;
22 unsigned int irq[6]; 22 unsigned int irq[6];
23 u64 *dma_mask; 23 u64 *dma_mask;
24 u64 coherent_dma_mask;
24}; 25};
25 26
26#define to_sh_dev(d) container_of((d), struct sh_dev, dev) 27#define to_sh_dev(d) container_of((d), struct sh_dev, dev)
diff --git a/include/asm-sh/clock.h b/include/asm-sh/clock.h
new file mode 100644
index 000000000000..fdfb75b30f0d
--- /dev/null
+++ b/include/asm-sh/clock.h
@@ -0,0 +1,61 @@
1#ifndef __ASM_SH_CLOCK_H
2#define __ASM_SH_CLOCK_H
3
4#include <linux/kref.h>
5#include <linux/list.h>
6#include <linux/seq_file.h>
7
8struct clk;
9
10struct clk_ops {
11 void (*init)(struct clk *clk);
12 void (*enable)(struct clk *clk);
13 void (*disable)(struct clk *clk);
14 void (*recalc)(struct clk *clk);
15 int (*set_rate)(struct clk *clk, unsigned long rate);
16};
17
18struct clk {
19 struct list_head node;
20 const char *name;
21
22 struct module *owner;
23
24 struct clk *parent;
25 struct clk_ops *ops;
26
27 struct kref kref;
28
29 unsigned long rate;
30 unsigned long flags;
31};
32
33#define CLK_ALWAYS_ENABLED (1 << 0)
34#define CLK_RATE_PROPAGATES (1 << 1)
35
36/* Should be defined by processor-specific code */
37void arch_init_clk_ops(struct clk_ops **, int type);
38
39/* arch/sh/kernel/cpu/clock.c */
40int clk_init(void);
41
42int __clk_enable(struct clk *);
43int clk_enable(struct clk *);
44
45void __clk_disable(struct clk *);
46void clk_disable(struct clk *);
47
48int clk_set_rate(struct clk *, unsigned long rate);
49unsigned long clk_get_rate(struct clk *);
50void clk_recalc_rate(struct clk *);
51
52struct clk *clk_get(const char *id);
53void clk_put(struct clk *);
54
55int clk_register(struct clk *);
56void clk_unregister(struct clk *);
57
58int show_clocks(struct seq_file *m);
59
60#endif /* __ASM_SH_CLOCK_H */
61
diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h
index b972e715f9ee..954801b46022 100644
--- a/include/asm-sh/cpu-sh3/dma.h
+++ b/include/asm-sh/cpu-sh3/dma.h
@@ -3,5 +3,34 @@
3 3
4#define SH_DMAC_BASE 0xa4000020 4#define SH_DMAC_BASE 0xa4000020
5 5
6#endif /* __ASM_CPU_SH3_DMA_H */ 6/* Definitions for the SuperH DMAC */
7#define TM_BURST 0x00000020
8#define TS_8 0x00000000
9#define TS_16 0x00000008
10#define TS_32 0x00000010
11#define TS_128 0x00000018
12
13#define CHCR_TS_MASK 0x18
14#define CHCR_TS_SHIFT 3
15
16#define DMAOR_INIT DMAOR_DME
7 17
18/*
19 * The SuperH DMAC supports a number of transmit sizes, we list them here,
20 * with their respective values as they appear in the CHCR registers.
21 */
22enum {
23 XMIT_SZ_8BIT,
24 XMIT_SZ_16BIT,
25 XMIT_SZ_32BIT,
26 XMIT_SZ_128BIT,
27};
28
29static unsigned int ts_shift[] __attribute__ ((used)) = {
30 [XMIT_SZ_8BIT] = 0,
31 [XMIT_SZ_16BIT] = 1,
32 [XMIT_SZ_32BIT] = 2,
33 [XMIT_SZ_128BIT] = 4,
34};
35
36#endif /* __ASM_CPU_SH3_DMA_H */
diff --git a/include/asm-sh/cpu-sh4/dma.h b/include/asm-sh/cpu-sh4/dma.h
index e2b91adf821a..0dfe61f14802 100644
--- a/include/asm-sh/cpu-sh4/dma.h
+++ b/include/asm-sh/cpu-sh4/dma.h
@@ -1,17 +1,49 @@
1#ifndef __ASM_CPU_SH4_DMA_H 1#ifndef __ASM_CPU_SH4_DMA_H
2#define __ASM_CPU_SH4_DMA_H 2#define __ASM_CPU_SH4_DMA_H
3 3
4#ifdef CONFIG_CPU_SH4A
5#define SH_DMAC_BASE 0xfc808020
6#else
4#define SH_DMAC_BASE 0xffa00000 7#define SH_DMAC_BASE 0xffa00000
8#endif
5 9
6#define SAR ((unsigned long[]){SH_DMAC_BASE + 0x00, SH_DMAC_BASE + 0x10, \ 10/* Definitions for the SuperH DMAC */
7 SH_DMAC_BASE + 0x20, SH_DMAC_BASE + 0x30}) 11#define TM_BURST 0x0000080
8#define DAR ((unsigned long[]){SH_DMAC_BASE + 0x04, SH_DMAC_BASE + 0x14, \ 12#define TS_8 0x00000010
9 SH_DMAC_BASE + 0x24, SH_DMAC_BASE + 0x34}) 13#define TS_16 0x00000020
10#define DMATCR ((unsigned long[]){SH_DMAC_BASE + 0x08, SH_DMAC_BASE + 0x18, \ 14#define TS_32 0x00000030
11 SH_DMAC_BASE + 0x28, SH_DMAC_BASE + 0x38}) 15#define TS_64 0x00000000
12#define CHCR ((unsigned long[]){SH_DMAC_BASE + 0x0c, SH_DMAC_BASE + 0x1c, \
13 SH_DMAC_BASE + 0x2c, SH_DMAC_BASE + 0x3c})
14#define DMAOR (SH_DMAC_BASE + 0x40)
15 16
16#endif /* __ASM_CPU_SH4_DMA_H */ 17#define CHCR_TS_MASK 0x30
18#define CHCR_TS_SHIFT 4
19
20#define DMAOR_COD 0x00000008
21
22#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
17 23
24/*
25 * The SuperH DMAC supports a number of transmit sizes, we list them here,
26 * with their respective values as they appear in the CHCR registers.
27 *
28 * Defaults to a 64-bit transfer size.
29 */
30enum {
31 XMIT_SZ_64BIT,
32 XMIT_SZ_8BIT,
33 XMIT_SZ_16BIT,
34 XMIT_SZ_32BIT,
35 XMIT_SZ_256BIT,
36};
37
38/*
39 * The DMA count is defined as the number of bytes to transfer.
40 */
41static unsigned int ts_shift[] __attribute__ ((used)) = {
42 [XMIT_SZ_64BIT] = 3,
43 [XMIT_SZ_8BIT] = 0,
44 [XMIT_SZ_16BIT] = 1,
45 [XMIT_SZ_32BIT] = 2,
46 [XMIT_SZ_256BIT] = 5,
47};
48
49#endif /* __ASM_CPU_SH4_DMA_H */
diff --git a/include/asm-sh/cpu-sh4/freq.h b/include/asm-sh/cpu-sh4/freq.h
index 201d94fd214f..ef2b9b1ae41f 100644
--- a/include/asm-sh/cpu-sh4/freq.h
+++ b/include/asm-sh/cpu-sh4/freq.h
@@ -12,6 +12,8 @@
12 12
13#if defined(CONFIG_CPU_SUBTYPE_SH73180) 13#if defined(CONFIG_CPU_SUBTYPE_SH73180)
14#define FRQCR 0xa4150000 14#define FRQCR 0xa4150000
15#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
16#define FRQCR 0xffc80000
15#else 17#else
16#define FRQCR 0xffc00000 18#define FRQCR 0xffc00000
17#endif 19#endif
diff --git a/include/asm-sh/dma-mapping.h b/include/asm-sh/dma-mapping.h
index d3fa5c2b889d..48f1f42c5d14 100644
--- a/include/asm-sh/dma-mapping.h
+++ b/include/asm-sh/dma-mapping.h
@@ -4,6 +4,7 @@
4#include <linux/config.h> 4#include <linux/config.h>
5#include <linux/mm.h> 5#include <linux/mm.h>
6#include <asm/scatterlist.h> 6#include <asm/scatterlist.h>
7#include <asm/cacheflush.h>
7#include <asm/io.h> 8#include <asm/io.h>
8 9
9extern struct bus_type pci_bus_type; 10extern struct bus_type pci_bus_type;
@@ -141,24 +142,24 @@ static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg,
141 } 142 }
142} 143}
143 144
144static inline void dma_sync_single_for_cpu(struct device *dev, 145static void dma_sync_single_for_cpu(struct device *dev,
145 dma_addr_t dma_handle, size_t size, 146 dma_addr_t dma_handle, size_t size,
146 enum dma_data_direction dir) 147 enum dma_data_direction dir)
147 __attribute__ ((alias("dma_sync_single"))); 148 __attribute__ ((alias("dma_sync_single")));
148 149
149static inline void dma_sync_single_for_device(struct device *dev, 150static void dma_sync_single_for_device(struct device *dev,
150 dma_addr_t dma_handle, size_t size, 151 dma_addr_t dma_handle, size_t size,
151 enum dma_data_direction dir) 152 enum dma_data_direction dir)
152 __attribute__ ((alias("dma_sync_single"))); 153 __attribute__ ((alias("dma_sync_single")));
153 154
154static inline void dma_sync_sg_for_cpu(struct device *dev, 155static void dma_sync_sg_for_cpu(struct device *dev,
155 struct scatterlist *sg, int nelems, 156 struct scatterlist *sg, int nelems,
156 enum dma_data_direction dir) 157 enum dma_data_direction dir)
157 __attribute__ ((alias("dma_sync_sg"))); 158 __attribute__ ((alias("dma_sync_sg")));
158 159
159static inline void dma_sync_sg_for_device(struct device *dev, 160static void dma_sync_sg_for_device(struct device *dev,
160 struct scatterlist *sg, int nelems, 161 struct scatterlist *sg, int nelems,
161 enum dma_data_direction dir) 162 enum dma_data_direction dir)
162 __attribute__ ((alias("dma_sync_sg"))); 163 __attribute__ ((alias("dma_sync_sg")));
163 164
164static inline int dma_get_cache_alignment(void) 165static inline int dma_get_cache_alignment(void)
diff --git a/include/asm-sh/dma.h b/include/asm-sh/dma.h
index 8e9436093ca8..a118a0d43053 100644
--- a/include/asm-sh/dma.h
+++ b/include/asm-sh/dma.h
@@ -15,6 +15,7 @@
15#include <linux/spinlock.h> 15#include <linux/spinlock.h>
16#include <linux/wait.h> 16#include <linux/wait.h>
17#include <linux/sysdev.h> 17#include <linux/sysdev.h>
18#include <linux/device.h>
18#include <asm/cpu/dma.h> 19#include <asm/cpu/dma.h>
19#include <asm/semaphore.h> 20#include <asm/semaphore.h>
20 21
@@ -54,8 +55,8 @@ enum {
54 * DMA channel capabilities / flags 55 * DMA channel capabilities / flags
55 */ 56 */
56enum { 57enum {
57 DMA_CONFIGURED = 0x00,
58 DMA_TEI_CAPABLE = 0x01, 58 DMA_TEI_CAPABLE = 0x01,
59 DMA_CONFIGURED = 0x02,
59}; 60};
60 61
61extern spinlock_t dma_spin_lock; 62extern spinlock_t dma_spin_lock;
@@ -74,7 +75,8 @@ struct dma_ops {
74struct dma_channel { 75struct dma_channel {
75 char dev_id[16]; 76 char dev_id[16];
76 77
77 unsigned int chan; 78 unsigned int chan; /* Physical channel number */
79 unsigned int vchan; /* Virtual channel number */
78 unsigned int mode; 80 unsigned int mode;
79 unsigned int count; 81 unsigned int count;
80 82
@@ -91,6 +93,8 @@ struct dma_channel {
91}; 93};
92 94
93struct dma_info { 95struct dma_info {
96 struct platform_device *pdev;
97
94 const char *name; 98 const char *name;
95 unsigned int nr_channels; 99 unsigned int nr_channels;
96 unsigned long flags; 100 unsigned long flags;
@@ -130,7 +134,11 @@ extern void unregister_dmac(struct dma_info *info);
130 134
131#ifdef CONFIG_SYSFS 135#ifdef CONFIG_SYSFS
132/* arch/sh/drivers/dma/dma-sysfs.c */ 136/* arch/sh/drivers/dma/dma-sysfs.c */
133extern int dma_create_sysfs_files(struct dma_channel *); 137extern int dma_create_sysfs_files(struct dma_channel *, struct dma_info *);
138extern void dma_remove_sysfs_files(struct dma_channel *, struct dma_info *);
139#else
140#define dma_create_sysfs_file(channel, info) do { } while (0)
141#define dma_remove_sysfs_file(channel, info) do { } while (0)
134#endif 142#endif
135 143
136#ifdef CONFIG_PCI 144#ifdef CONFIG_PCI
diff --git a/include/asm-sh/freq.h b/include/asm-sh/freq.h
index 2c0fde46a0ed..39c0e091cf58 100644
--- a/include/asm-sh/freq.h
+++ b/include/asm-sh/freq.h
@@ -14,16 +14,5 @@
14 14
15#include <asm/cpu/freq.h> 15#include <asm/cpu/freq.h>
16 16
17/* arch/sh/kernel/time.c */
18extern void get_current_frequency_divisors(unsigned int *ifc, unsigned int *pfc, unsigned int *bfc);
19
20extern unsigned int get_ifc_divisor(unsigned int value);
21extern unsigned int get_ifc_divisor(unsigned int value);
22extern unsigned int get_ifc_divisor(unsigned int value);
23
24extern unsigned int get_ifc_value(unsigned int divisor);
25extern unsigned int get_pfc_value(unsigned int divisor);
26extern unsigned int get_bfc_value(unsigned int divisor);
27
28#endif /* __KERNEL__ */ 17#endif /* __KERNEL__ */
29#endif /* __ASM_SH_FREQ_H */ 18#endif /* __ASM_SH_FREQ_H */
diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h
index 6bc343fee7a0..b0b2937b6f83 100644
--- a/include/asm-sh/io.h
+++ b/include/asm-sh/io.h
@@ -11,7 +11,7 @@
11 * For read{b,w,l} and write{b,w,l} there are also __raw versions, which 11 * For read{b,w,l} and write{b,w,l} there are also __raw versions, which
12 * do not have a memory barrier after them. 12 * do not have a memory barrier after them.
13 * 13 *
14 * In addition, we have 14 * In addition, we have
15 * ctrl_in{b,w,l}/ctrl_out{b,w,l} for SuperH specific I/O. 15 * ctrl_in{b,w,l}/ctrl_out{b,w,l} for SuperH specific I/O.
16 * which are processor specific. 16 * which are processor specific.
17 */ 17 */
@@ -23,19 +23,27 @@
23 * inb by default expands to _inb, but the machine specific code may 23 * inb by default expands to _inb, but the machine specific code may
24 * define it to __inb if it chooses. 24 * define it to __inb if it chooses.
25 */ 25 */
26 26#include <linux/config.h>
27#include <asm/cache.h> 27#include <asm/cache.h>
28#include <asm/system.h> 28#include <asm/system.h>
29#include <asm/addrspace.h> 29#include <asm/addrspace.h>
30#include <asm/machvec.h> 30#include <asm/machvec.h>
31#include <linux/config.h> 31#include <asm/pgtable.h>
32#include <asm-generic/iomap.h>
33
34#ifdef __KERNEL__
32 35
33/* 36/*
34 * Depending on which platform we are running on, we need different 37 * Depending on which platform we are running on, we need different
35 * I/O functions. 38 * I/O functions.
36 */ 39 */
40#define __IO_PREFIX generic
41#include <asm/io_generic.h>
42
43#define maybebadio(port) \
44 printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
45 __FUNCTION__, __LINE__, (port), (u32)__builtin_return_address(0))
37 46
38#ifdef __KERNEL__
39/* 47/*
40 * Since boards are able to define their own set of I/O routines through 48 * Since boards are able to define their own set of I/O routines through
41 * their respective machine vector, we always wrap through the mv. 49 * their respective machine vector, we always wrap through the mv.
@@ -44,113 +52,120 @@
44 * a given routine, it will be wrapped to generic code at run-time. 52 * a given routine, it will be wrapped to generic code at run-time.
45 */ 53 */
46 54
47# define __inb(p) sh_mv.mv_inb((p)) 55#define __inb(p) sh_mv.mv_inb((p))
48# define __inw(p) sh_mv.mv_inw((p)) 56#define __inw(p) sh_mv.mv_inw((p))
49# define __inl(p) sh_mv.mv_inl((p)) 57#define __inl(p) sh_mv.mv_inl((p))
50# define __outb(x,p) sh_mv.mv_outb((x),(p)) 58#define __outb(x,p) sh_mv.mv_outb((x),(p))
51# define __outw(x,p) sh_mv.mv_outw((x),(p)) 59#define __outw(x,p) sh_mv.mv_outw((x),(p))
52# define __outl(x,p) sh_mv.mv_outl((x),(p)) 60#define __outl(x,p) sh_mv.mv_outl((x),(p))
53 61
54# define __inb_p(p) sh_mv.mv_inb_p((p)) 62#define __inb_p(p) sh_mv.mv_inb_p((p))
55# define __inw_p(p) sh_mv.mv_inw_p((p)) 63#define __inw_p(p) sh_mv.mv_inw_p((p))
56# define __inl_p(p) sh_mv.mv_inl_p((p)) 64#define __inl_p(p) sh_mv.mv_inl_p((p))
57# define __outb_p(x,p) sh_mv.mv_outb_p((x),(p)) 65#define __outb_p(x,p) sh_mv.mv_outb_p((x),(p))
58# define __outw_p(x,p) sh_mv.mv_outw_p((x),(p)) 66#define __outw_p(x,p) sh_mv.mv_outw_p((x),(p))
59# define __outl_p(x,p) sh_mv.mv_outl_p((x),(p)) 67#define __outl_p(x,p) sh_mv.mv_outl_p((x),(p))
60 68
61# define __insb(p,b,c) sh_mv.mv_insb((p), (b), (c)) 69#define __insb(p,b,c) sh_mv.mv_insb((p), (b), (c))
62# define __insw(p,b,c) sh_mv.mv_insw((p), (b), (c)) 70#define __insw(p,b,c) sh_mv.mv_insw((p), (b), (c))
63# define __insl(p,b,c) sh_mv.mv_insl((p), (b), (c)) 71#define __insl(p,b,c) sh_mv.mv_insl((p), (b), (c))
64# define __outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c)) 72#define __outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c))
65# define __outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c)) 73#define __outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c))
66# define __outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c)) 74#define __outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c))
67 75
68# define __readb(a) sh_mv.mv_readb((a)) 76#define __readb(a) sh_mv.mv_readb((a))
69# define __readw(a) sh_mv.mv_readw((a)) 77#define __readw(a) sh_mv.mv_readw((a))
70# define __readl(a) sh_mv.mv_readl((a)) 78#define __readl(a) sh_mv.mv_readl((a))
71# define __writeb(v,a) sh_mv.mv_writeb((v),(a)) 79#define __writeb(v,a) sh_mv.mv_writeb((v),(a))
72# define __writew(v,a) sh_mv.mv_writew((v),(a)) 80#define __writew(v,a) sh_mv.mv_writew((v),(a))
73# define __writel(v,a) sh_mv.mv_writel((v),(a)) 81#define __writel(v,a) sh_mv.mv_writel((v),(a))
74 82
75# define __ioremap(a,s) sh_mv.mv_ioremap((a), (s)) 83#define inb __inb
76# define __iounmap(a) sh_mv.mv_iounmap((a)) 84#define inw __inw
77 85#define inl __inl
78# define __isa_port2addr(a) sh_mv.mv_isa_port2addr(a) 86#define outb __outb
79 87#define outw __outw
80# define inb __inb 88#define outl __outl
81# define inw __inw 89
82# define inl __inl 90#define inb_p __inb_p
83# define outb __outb 91#define inw_p __inw_p
84# define outw __outw 92#define inl_p __inl_p
85# define outl __outl 93#define outb_p __outb_p
86 94#define outw_p __outw_p
87# define inb_p __inb_p 95#define outl_p __outl_p
88# define inw_p __inw_p 96
89# define inl_p __inl_p 97#define insb __insb
90# define outb_p __outb_p 98#define insw __insw
91# define outw_p __outw_p 99#define insl __insl
92# define outl_p __outl_p 100#define outsb __outsb
93 101#define outsw __outsw
94# define insb __insb 102#define outsl __outsl
95# define insw __insw 103
96# define insl __insl 104#define __raw_readb(a) __readb((void __iomem *)(a))
97# define outsb __outsb 105#define __raw_readw(a) __readw((void __iomem *)(a))
98# define outsw __outsw 106#define __raw_readl(a) __readl((void __iomem *)(a))
99# define outsl __outsl 107#define __raw_writeb(v, a) __writeb(v, (void __iomem *)(a))
100 108#define __raw_writew(v, a) __writew(v, (void __iomem *)(a))
101# define __raw_readb __readb 109#define __raw_writel(v, a) __writel(v, (void __iomem *)(a))
102# define __raw_readw __readw
103# define __raw_readl __readl
104# define __raw_writeb __writeb
105# define __raw_writew __writew
106# define __raw_writel __writel
107 110
108/* 111/*
109 * The platform header files may define some of these macros to use 112 * The platform header files may define some of these macros to use
110 * the inlined versions where appropriate. These macros may also be 113 * the inlined versions where appropriate. These macros may also be
111 * redefined by userlevel programs. 114 * redefined by userlevel programs.
112 */ 115 */
113#ifdef __raw_readb 116#ifdef __readb
114# define readb(a) ({ unsigned long r_ = __raw_readb((unsigned long)a); mb(); r_; }) 117# define readb(a) ({ unsigned long r_ = __raw_readb(a); mb(); r_; })
115#endif 118#endif
116#ifdef __raw_readw 119#ifdef __raw_readw
117# define readw(a) ({ unsigned long r_ = __raw_readw((unsigned long)a); mb(); r_; }) 120# define readw(a) ({ unsigned long r_ = __raw_readw(a); mb(); r_; })
118#endif 121#endif
119#ifdef __raw_readl 122#ifdef __raw_readl
120# define readl(a) ({ unsigned long r_ = __raw_readl((unsigned long)a); mb(); r_; }) 123# define readl(a) ({ unsigned long r_ = __raw_readl(a); mb(); r_; })
121#endif 124#endif
122 125
123#ifdef __raw_writeb 126#ifdef __raw_writeb
124# define writeb(v,a) ({ __raw_writeb((v),(unsigned long)(a)); mb(); }) 127# define writeb(v,a) ({ __raw_writeb((v),(a)); mb(); })
125#endif 128#endif
126#ifdef __raw_writew 129#ifdef __raw_writew
127# define writew(v,a) ({ __raw_writew((v),(unsigned long)(a)); mb(); }) 130# define writew(v,a) ({ __raw_writew((v),(a)); mb(); })
128#endif 131#endif
129#ifdef __raw_writel 132#ifdef __raw_writel
130# define writel(v,a) ({ __raw_writel((v),(unsigned long)(a)); mb(); }) 133# define writel(v,a) ({ __raw_writel((v),(a)); mb(); })
131#endif 134#endif
132 135
133#define readb_relaxed(a) readb(a) 136#define readb_relaxed(a) readb(a)
134#define readw_relaxed(a) readw(a) 137#define readw_relaxed(a) readw(a)
135#define readl_relaxed(a) readl(a) 138#define readl_relaxed(a) readl(a)
136 139
137#define mmiowb() 140/* Simple MMIO */
141#define ioread8(a) readb(a)
142#define ioread16(a) readw(a)
143#define ioread16be(a) be16_to_cpu(__raw_readw((a)))
144#define ioread32(a) readl(a)
145#define ioread32be(a) be32_to_cpu(__raw_readl((a)))
138 146
139/* 147#define iowrite8(v,a) writeb((v),(a))
140 * If the platform has PC-like I/O, this function converts the offset into 148#define iowrite16(v,a) writew((v),(a))
141 * an address. 149#define iowrite16be(v,a) __raw_writew(cpu_to_be16((v)),(a))
142 */ 150#define iowrite32(v,a) writel((v),(a))
143static __inline__ unsigned long isa_port2addr(unsigned long offset) 151#define iowrite32be(v,a) __raw_writel(cpu_to_be32((v)),(a))
144{ 152
145 return __isa_port2addr(offset); 153#define ioread8_rep(a,d,c) insb((a),(d),(c))
146} 154#define ioread16_rep(a,d,c) insw((a),(d),(c))
155#define ioread32_rep(a,d,c) insl((a),(d),(c))
156
157#define iowrite8_rep(a,s,c) outsb((a),(s),(c))
158#define iowrite16_rep(a,s,c) outsw((a),(s),(c))
159#define iowrite32_rep(a,s,c) outsl((a),(s),(c))
160
161#define mmiowb() wmb() /* synco on SH-4A, otherwise a nop */
147 162
148/* 163/*
149 * This function provides a method for the generic case where a board-specific 164 * This function provides a method for the generic case where a board-specific
150 * isa_port2addr simply needs to return the port + some arbitrary port base. 165 * ioport_map simply needs to return the port + some arbitrary port base.
151 * 166 *
152 * We use this at board setup time to implicitly set the port base, and 167 * We use this at board setup time to implicitly set the port base, and
153 * as a result, we can use the generic isa_port2addr. 168 * as a result, we can use the generic ioport_map.
154 */ 169 */
155static inline void __set_io_port_base(unsigned long pbase) 170static inline void __set_io_port_base(unsigned long pbase)
156{ 171{
@@ -159,51 +174,52 @@ static inline void __set_io_port_base(unsigned long pbase)
159 generic_io_base = pbase; 174 generic_io_base = pbase;
160} 175}
161 176
162#define isa_readb(a) readb(isa_port2addr(a)) 177#define isa_readb(a) readb(ioport_map(a, 1))
163#define isa_readw(a) readw(isa_port2addr(a)) 178#define isa_readw(a) readw(ioport_map(a, 2))
164#define isa_readl(a) readl(isa_port2addr(a)) 179#define isa_readl(a) readl(ioport_map(a, 4))
165#define isa_writeb(b,a) writeb(b,isa_port2addr(a)) 180#define isa_writeb(b,a) writeb(b,ioport_map(a, 1))
166#define isa_writew(w,a) writew(w,isa_port2addr(a)) 181#define isa_writew(w,a) writew(w,ioport_map(a, 2))
167#define isa_writel(l,a) writel(l,isa_port2addr(a)) 182#define isa_writel(l,a) writel(l,ioport_map(a, 4))
183
168#define isa_memset_io(a,b,c) \ 184#define isa_memset_io(a,b,c) \
169 memset((void *)(isa_port2addr((unsigned long)a)),(b),(c)) 185 memset((void *)(ioport_map((unsigned long)(a), 1)),(b),(c))
170#define isa_memcpy_fromio(a,b,c) \ 186#define isa_memcpy_fromio(a,b,c) \
171 memcpy((a),(void *)(isa_port2addr((unsigned long)(b))),(c)) 187 memcpy((a),(void *)(ioport_map((unsigned long)(b), 1)),(c))
172#define isa_memcpy_toio(a,b,c) \ 188#define isa_memcpy_toio(a,b,c) \
173 memcpy((void *)(isa_port2addr((unsigned long)(a))),(b),(c)) 189 memcpy((void *)(ioport_map((unsigned long)(a), 1)),(b),(c))
174 190
175/* We really want to try and get these to memcpy etc */ 191/* We really want to try and get these to memcpy etc */
176extern void memcpy_fromio(void *, unsigned long, unsigned long); 192extern void memcpy_fromio(void *, volatile void __iomem *, unsigned long);
177extern void memcpy_toio(unsigned long, const void *, unsigned long); 193extern void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
178extern void memset_io(unsigned long, int, unsigned long); 194extern void memset_io(volatile void __iomem *, int, unsigned long);
179 195
180/* SuperH on-chip I/O functions */ 196/* SuperH on-chip I/O functions */
181static __inline__ unsigned char ctrl_inb(unsigned long addr) 197static inline unsigned char ctrl_inb(unsigned long addr)
182{ 198{
183 return *(volatile unsigned char*)addr; 199 return *(volatile unsigned char*)addr;
184} 200}
185 201
186static __inline__ unsigned short ctrl_inw(unsigned long addr) 202static inline unsigned short ctrl_inw(unsigned long addr)
187{ 203{
188 return *(volatile unsigned short*)addr; 204 return *(volatile unsigned short*)addr;
189} 205}
190 206
191static __inline__ unsigned int ctrl_inl(unsigned long addr) 207static inline unsigned int ctrl_inl(unsigned long addr)
192{ 208{
193 return *(volatile unsigned long*)addr; 209 return *(volatile unsigned long*)addr;
194} 210}
195 211
196static __inline__ void ctrl_outb(unsigned char b, unsigned long addr) 212static inline void ctrl_outb(unsigned char b, unsigned long addr)
197{ 213{
198 *(volatile unsigned char*)addr = b; 214 *(volatile unsigned char*)addr = b;
199} 215}
200 216
201static __inline__ void ctrl_outw(unsigned short b, unsigned long addr) 217static inline void ctrl_outw(unsigned short b, unsigned long addr)
202{ 218{
203 *(volatile unsigned short*)addr = b; 219 *(volatile unsigned short*)addr = b;
204} 220}
205 221
206static __inline__ void ctrl_outl(unsigned int b, unsigned long addr) 222static inline void ctrl_outl(unsigned int b, unsigned long addr)
207{ 223{
208 *(volatile unsigned long*)addr = b; 224 *(volatile unsigned long*)addr = b;
209} 225}
@@ -214,12 +230,12 @@ static __inline__ void ctrl_outl(unsigned int b, unsigned long addr)
214 * Change virtual addresses to physical addresses and vv. 230 * Change virtual addresses to physical addresses and vv.
215 * These are trivial on the 1:1 Linux/SuperH mapping 231 * These are trivial on the 1:1 Linux/SuperH mapping
216 */ 232 */
217static __inline__ unsigned long virt_to_phys(volatile void * address) 233static inline unsigned long virt_to_phys(volatile void *address)
218{ 234{
219 return PHYSADDR(address); 235 return PHYSADDR(address);
220} 236}
221 237
222static __inline__ void * phys_to_virt(unsigned long address) 238static inline void *phys_to_virt(unsigned long address)
223{ 239{
224 return (void *)P1SEGADDR(address); 240 return (void *)P1SEGADDR(address);
225} 241}
@@ -234,27 +250,60 @@ static __inline__ void * phys_to_virt(unsigned long address)
234 * differently. On the x86 architecture, we just read/write the 250 * differently. On the x86 architecture, we just read/write the
235 * memory location directly. 251 * memory location directly.
236 * 252 *
237 * On SH, we have the whole physical address space mapped at all times 253 * On SH, we traditionally have the whole physical address space mapped
238 * (as MIPS does), so "ioremap()" and "iounmap()" do not need to do 254 * at all times (as MIPS does), so "ioremap()" and "iounmap()" do not
239 * anything. (This isn't true for all machines but we still handle 255 * need to do anything but place the address in the proper segment. This
240 * these cases with wired TLB entries anyway ...) 256 * is true for P1 and P2 addresses, as well as some P3 ones. However,
257 * most of the P3 addresses and newer cores using extended addressing
258 * need to map through page tables, so the ioremap() implementation
259 * becomes a bit more complicated. See arch/sh/mm/ioremap.c for
260 * additional notes on this.
241 * 261 *
242 * We cheat a bit and always return uncachable areas until we've fixed 262 * We cheat a bit and always return uncachable areas until we've fixed
243 * the drivers to handle caching properly. 263 * the drivers to handle caching properly.
244 */ 264 */
245static __inline__ void * ioremap(unsigned long offset, unsigned long size) 265#ifdef CONFIG_MMU
266void __iomem *__ioremap(unsigned long offset, unsigned long size,
267 unsigned long flags);
268void __iounmap(void __iomem *addr);
269#else
270#define __ioremap(offset, size, flags) ((void __iomem *)(offset))
271#define __iounmap(addr) do { } while (0)
272#endif /* CONFIG_MMU */
273
274static inline void __iomem *
275__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
246{ 276{
247 return __ioremap(offset, size); 277 unsigned long last_addr = offset + size - 1;
278
279 /*
280 * For P1 and P2 space this is trivial, as everything is already
281 * mapped. Uncached access for P1 addresses are done through P2.
282 * In the P3 case or for addresses outside of the 29-bit space,
283 * mapping must be done by the PMB or by using page tables.
284 */
285 if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
286 if (unlikely(flags & _PAGE_CACHABLE))
287 return (void __iomem *)P1SEGADDR(offset);
288
289 return (void __iomem *)P2SEGADDR(offset);
290 }
291
292 return __ioremap(offset, size, flags);
248} 293}
249 294
250static __inline__ void iounmap(void *addr) 295#define ioremap(offset, size) \
251{ 296 __ioremap_mode((offset), (size), 0)
252 return __iounmap(addr); 297#define ioremap_nocache(offset, size) \
253} 298 __ioremap_mode((offset), (size), 0)
254 299#define ioremap_cache(offset, size) \
255#define ioremap_nocache(off,size) ioremap(off,size) 300 __ioremap_mode((offset), (size), _PAGE_CACHABLE)
256 301#define p3_ioremap(offset, size, flags) \
257static __inline__ int check_signature(unsigned long io_addr, 302 __ioremap((offset), (size), (flags))
303#define iounmap(addr) \
304 __iounmap((addr))
305
306static inline int check_signature(char __iomem *io_addr,
258 const unsigned char *signature, int length) 307 const unsigned char *signature, int length)
259{ 308{
260 int retval = 0; 309 int retval = 0;
diff --git a/include/asm-sh/io_generic.h b/include/asm-sh/io_generic.h
index be14587342f7..92fc6070d7b3 100644
--- a/include/asm-sh/io_generic.h
+++ b/include/asm-sh/io_generic.h
@@ -1,51 +1,49 @@
1/* 1/*
2 * include/asm-sh/io_generic.h 2 * Trivial I/O routine definitions, intentionally meant to be included
3 * 3 * multiple times. Ugly I/O routine concatenation helpers taken from
4 * Copyright 2000 Stuart Menefy (stuart.menefy@st.com) 4 * alpha. Must be included _before_ io.h to avoid preprocessor-induced
5 * 5 * routine mismatch.
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * Generic IO functions
10 */ 6 */
11 7#define IO_CONCAT(a,b) _IO_CONCAT(a,b)
12#ifndef _ASM_SH_IO_GENERIC_H 8#define _IO_CONCAT(a,b) a ## _ ## b
13#define _ASM_SH_IO_GENERIC_H 9
14 10#ifndef __IO_PREFIX
15extern unsigned long generic_io_base; 11#error "Don't include this header without a valid system prefix"
16 12#endif
17extern unsigned char generic_inb(unsigned long port); 13
18extern unsigned short generic_inw(unsigned long port); 14u8 IO_CONCAT(__IO_PREFIX,inb)(unsigned long);
19extern unsigned int generic_inl(unsigned long port); 15u16 IO_CONCAT(__IO_PREFIX,inw)(unsigned long);
20 16u32 IO_CONCAT(__IO_PREFIX,inl)(unsigned long);
21extern void generic_outb(unsigned char value, unsigned long port); 17
22extern void generic_outw(unsigned short value, unsigned long port); 18void IO_CONCAT(__IO_PREFIX,outb)(u8, unsigned long);
23extern void generic_outl(unsigned int value, unsigned long port); 19void IO_CONCAT(__IO_PREFIX,outw)(u16, unsigned long);
24 20void IO_CONCAT(__IO_PREFIX,outl)(u32, unsigned long);
25extern unsigned char generic_inb_p(unsigned long port); 21
26extern unsigned short generic_inw_p(unsigned long port); 22u8 IO_CONCAT(__IO_PREFIX,inb_p)(unsigned long);
27extern unsigned int generic_inl_p(unsigned long port); 23u16 IO_CONCAT(__IO_PREFIX,inw_p)(unsigned long);
28extern void generic_outb_p(unsigned char value, unsigned long port); 24u32 IO_CONCAT(__IO_PREFIX,inl_p)(unsigned long);
29extern void generic_outw_p(unsigned short value, unsigned long port); 25void IO_CONCAT(__IO_PREFIX,outb_p)(u8, unsigned long);
30extern void generic_outl_p(unsigned int value, unsigned long port); 26void IO_CONCAT(__IO_PREFIX,outw_p)(u16, unsigned long);
31 27void IO_CONCAT(__IO_PREFIX,outl_p)(u32, unsigned long);
32extern void generic_insb(unsigned long port, void *addr, unsigned long count); 28
33extern void generic_insw(unsigned long port, void *addr, unsigned long count); 29void IO_CONCAT(__IO_PREFIX,insb)(unsigned long, void *dst, unsigned long count);
34extern void generic_insl(unsigned long port, void *addr, unsigned long count); 30void IO_CONCAT(__IO_PREFIX,insw)(unsigned long, void *dst, unsigned long count);
35extern void generic_outsb(unsigned long port, const void *addr, unsigned long count); 31void IO_CONCAT(__IO_PREFIX,insl)(unsigned long, void *dst, unsigned long count);
36extern void generic_outsw(unsigned long port, const void *addr, unsigned long count); 32void IO_CONCAT(__IO_PREFIX,outsb)(unsigned long, const void *src, unsigned long count);
37extern void generic_outsl(unsigned long port, const void *addr, unsigned long count); 33void IO_CONCAT(__IO_PREFIX,outsw)(unsigned long, const void *src, unsigned long count);
38 34void IO_CONCAT(__IO_PREFIX,outsl)(unsigned long, const void *src, unsigned long count);
39extern unsigned char generic_readb(unsigned long addr); 35
40extern unsigned short generic_readw(unsigned long addr); 36u8 IO_CONCAT(__IO_PREFIX,readb)(void __iomem *);
41extern unsigned int generic_readl(unsigned long addr); 37u16 IO_CONCAT(__IO_PREFIX,readw)(void __iomem *);
42extern void generic_writeb(unsigned char b, unsigned long addr); 38u32 IO_CONCAT(__IO_PREFIX,readl)(void __iomem *);
43extern void generic_writew(unsigned short b, unsigned long addr); 39void IO_CONCAT(__IO_PREFIX,writeb)(u8, void __iomem *);
44extern void generic_writel(unsigned int b, unsigned long addr); 40void IO_CONCAT(__IO_PREFIX,writew)(u16, void __iomem *);
45 41void IO_CONCAT(__IO_PREFIX,writel)(u32, void __iomem *);
46extern void *generic_ioremap(unsigned long offset, unsigned long size); 42
47extern void generic_iounmap(void *addr); 43void *IO_CONCAT(__IO_PREFIX,ioremap)(unsigned long offset, unsigned long size);
48 44void IO_CONCAT(__IO_PREFIX,iounmap)(void *addr);
49extern unsigned long generic_isa_port2addr(unsigned long offset); 45
50 46void __iomem *IO_CONCAT(__IO_PREFIX,ioport_map)(unsigned long addr, unsigned int size);
51#endif /* _ASM_SH_IO_GENERIC_H */ 47void IO_CONCAT(__IO_PREFIX,ioport_unmap)(void __iomem *addr);
48
49#undef __IO_PREFIX
diff --git a/include/asm-sh/irq-sh7780.h b/include/asm-sh/irq-sh7780.h
new file mode 100644
index 000000000000..8c8ca1281084
--- /dev/null
+++ b/include/asm-sh/irq-sh7780.h
@@ -0,0 +1,349 @@
1#ifndef __ASM_SH_IRQ_SH7780_H
2#define __ASM_SH_IRQ_SH7780_H
3
4/*
5 * linux/include/asm-sh/irq-sh7780.h
6 *
7 * Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp>
8 */
9
10#ifdef CONFIG_IDE
11# ifndef IRQ_CFCARD
12# define IRQ_CFCARD 14
13# endif
14# ifndef IRQ_PCMCIA
15# define IRQ_PCMCIA 15
16# endif
17#endif
18
19#define INTC_BASE 0xffd00000
20#define INTC_ICR0 (INTC_BASE+0x0)
21#define INTC_ICR1 (INTC_BASE+0x1c)
22#define INTC_INTPRI (INTC_BASE+0x10)
23#define INTC_INTREQ (INTC_BASE+0x24)
24#define INTC_INTMSK0 (INTC_BASE+0x44)
25#define INTC_INTMSK1 (INTC_BASE+0x48)
26#define INTC_INTMSK2 (INTC_BASE+0x40080)
27#define INTC_INTMSKCLR0 (INTC_BASE+0x64)
28#define INTC_INTMSKCLR1 (INTC_BASE+0x68)
29#define INTC_INTMSKCLR2 (INTC_BASE+0x40084)
30#define INTC_NMIFCR (INTC_BASE+0xc0)
31#define INTC_USERIMASK (INTC_BASE+0x30000)
32
33#define INTC_INT2PRI0 (INTC_BASE+0x40000)
34#define INTC_INT2PRI1 (INTC_BASE+0x40004)
35#define INTC_INT2PRI2 (INTC_BASE+0x40008)
36#define INTC_INT2PRI3 (INTC_BASE+0x4000c)
37#define INTC_INT2PRI4 (INTC_BASE+0x40010)
38#define INTC_INT2PRI5 (INTC_BASE+0x40014)
39#define INTC_INT2PRI6 (INTC_BASE+0x40018)
40#define INTC_INT2PRI7 (INTC_BASE+0x4001c)
41#define INTC_INT2A0 (INTC_BASE+0x40030)
42#define INTC_INT2A1 (INTC_BASE+0x40034)
43#define INTC_INT2MSKR (INTC_BASE+0x40038)
44#define INTC_INT2MSKCR (INTC_BASE+0x4003c)
45#define INTC_INT2B0 (INTC_BASE+0x40040)
46#define INTC_INT2B1 (INTC_BASE+0x40044)
47#define INTC_INT2B2 (INTC_BASE+0x40048)
48#define INTC_INT2B3 (INTC_BASE+0x4004c)
49#define INTC_INT2B4 (INTC_BASE+0x40050)
50#define INTC_INT2B5 (INTC_BASE+0x40054)
51#define INTC_INT2B6 (INTC_BASE+0x40058)
52#define INTC_INT2B7 (INTC_BASE+0x4005c)
53#define INTC_INT2GPIC (INTC_BASE+0x40090)
54/*
55 NOTE:
56 *_IRQ = (INTEVT2 - 0x200)/0x20
57*/
58/* IRQ 0-7 line external int*/
59#define IRQ0_IRQ 2
60#define IRQ0_IPR_ADDR INTC_INTPRI
61#define IRQ0_IPR_POS 7
62#define IRQ0_PRIORITY 2
63
64#define IRQ1_IRQ 4
65#define IRQ1_IPR_ADDR INTC_INTPRI
66#define IRQ1_IPR_POS 6
67#define IRQ1_PRIORITY 2
68
69#define IRQ2_IRQ 6
70#define IRQ2_IPR_ADDR INTC_INTPRI
71#define IRQ2_IPR_POS 5
72#define IRQ2_PRIORITY 2
73
74#define IRQ3_IRQ 8
75#define IRQ3_IPR_ADDR INTC_INTPRI
76#define IRQ3_IPR_POS 4
77#define IRQ3_PRIORITY 2
78
79#define IRQ4_IRQ 10
80#define IRQ4_IPR_ADDR INTC_INTPRI
81#define IRQ4_IPR_POS 3
82#define IRQ4_PRIORITY 2
83
84#define IRQ5_IRQ 12
85#define IRQ5_IPR_ADDR INTC_INTPRI
86#define IRQ5_IPR_POS 2
87#define IRQ5_PRIORITY 2
88
89#define IRQ6_IRQ 14
90#define IRQ6_IPR_ADDR INTC_INTPRI
91#define IRQ6_IPR_POS 1
92#define IRQ6_PRIORITY 2
93
94#define IRQ7_IRQ 0
95#define IRQ7_IPR_ADDR INTC_INTPRI
96#define IRQ7_IPR_POS 0
97#define IRQ7_PRIORITY 2
98
99/* TMU */
100/* ch0 */
101#define TMU_IRQ 28
102#define TMU_IPR_ADDR INTC_INT2PRI0
103#define TMU_IPR_POS 3
104#define TMU_PRIORITY 2
105
106#define TIMER_IRQ 28
107#define TIMER_IPR_ADDR INTC_INT2PRI0
108#define TIMER_IPR_POS 3
109#define TIMER_PRIORITY 2
110
111/* ch 1*/
112#define TMU_CH1_IRQ 29
113#define TMU_CH1_IPR_ADDR INTC_INT2PRI0
114#define TMU_CH1_IPR_POS 2
115#define TMU_CH1_PRIORITY 2
116
117#define TIMER1_IRQ 29
118#define TIMER1_IPR_ADDR INTC_INT2PRI0
119#define TIMER1_IPR_POS 2
120#define TIMER1_PRIORITY 2
121
122/* ch 2*/
123#define TMU_CH2_IRQ 30
124#define TMU_CH2_IPR_ADDR INTC_INT2PRI0
125#define TMU_CH2_IPR_POS 1
126#define TMU_CH2_PRIORITY 2
127/* ch 2 Input capture */
128#define TMU_CH2IC_IRQ 31
129#define TMU_CH2IC_IPR_ADDR INTC_INT2PRI0
130#define TMU_CH2IC_IPR_POS 0
131#define TMU_CH2IC_PRIORITY 2
132/* ch 3 */
133#define TMU_CH3_IRQ 96
134#define TMU_CH3_IPR_ADDR INTC_INT2PRI1
135#define TMU_CH3_IPR_POS 3
136#define TMU_CH3_PRIORITY 2
137/* ch 4 */
138#define TMU_CH4_IRQ 97
139#define TMU_CH4_IPR_ADDR INTC_INT2PRI1
140#define TMU_CH4_IPR_POS 2
141#define TMU_CH4_PRIORITY 2
142/* ch 5*/
143#define TMU_CH5_IRQ 98
144#define TMU_CH5_IPR_ADDR INTC_INT2PRI1
145#define TMU_CH5_IPR_POS 1
146#define TMU_CH5_PRIORITY 2
147
148#define RTC_IRQ 22
149#define RTC_IPR_ADDR INTC_INT2PRI1
150#define RTC_IPR_POS 0
151#define RTC_PRIORITY TIMER_PRIORITY
152
153/* SCIF0 */
154#define SCIF0_ERI_IRQ 40
155#define SCIF0_RXI_IRQ 41
156#define SCIF0_BRI_IRQ 42
157#define SCIF0_TXI_IRQ 43
158#define SCIF0_IPR_ADDR INTC_INT2PRI2
159#define SCIF0_IPR_POS 3
160#define SCIF0_PRIORITY 3
161
162/* SCIF1 */
163#define SCIF1_ERI_IRQ 76
164#define SCIF1_RXI_IRQ 77
165#define SCIF1_BRI_IRQ 78
166#define SCIF1_TXI_IRQ 79
167#define SCIF1_IPR_ADDR INTC_INT2PRI2
168#define SCIF1_IPR_POS 2
169#define SCIF1_PRIORITY 3
170
171#define WDT_IRQ 27
172#define WDT_IPR_ADDR INTC_INT2PRI2
173#define WDT_IPR_POS 1
174#define WDT_PRIORITY 2
175
176/* DMAC(0) */
177#define DMINT0_IRQ 34
178#define DMINT1_IRQ 35
179#define DMINT2_IRQ 36
180#define DMINT3_IRQ 37
181#define DMINT4_IRQ 44
182#define DMINT5_IRQ 45
183#define DMINT6_IRQ 46
184#define DMINT7_IRQ 47
185#define DMAE_IRQ 38
186#define DMA0_IPR_ADDR INTC_INT2PRI3
187#define DMA0_IPR_POS 2
188#define DMA0_PRIORITY 7
189
190/* DMAC(1) */
191#define DMINT8_IRQ 92
192#define DMINT9_IRQ 93
193#define DMINT10_IRQ 94
194#define DMINT11_IRQ 95
195#define DMA1_IPR_ADDR INTC_INT2PRI3
196#define DMA1_IPR_POS 1
197#define DMA1_PRIORITY 7
198
199#define DMTE0_IRQ DMINT0_IRQ
200#define DMTE4_IRQ DMINT4_IRQ
201#define DMA_IPR_ADDR DMA0_IPR_ADDR
202#define DMA_IPR_POS DMA0_IPR_POS
203#define DMA_PRIORITY DMA0_PRIORITY
204
205/* CMT */
206#define CMT_IRQ 56
207#define CMT_IPR_ADDR INTC_INT2PRI4
208#define CMT_IPR_POS 3
209#define CMT_PRIORITY 0
210
211/* HAC */
212#define HAC_IRQ 60
213#define HAC_IPR_ADDR INTC_INT2PRI4
214#define HAC_IPR_POS 2
215#define CMT_PRIORITY 0
216
217/* PCIC(0) */
218#define PCIC0_IRQ 64
219#define PCIC0_IPR_ADDR INTC_INT2PRI4
220#define PCIC0_IPR_POS 1
221#define PCIC0_PRIORITY 2
222
223/* PCIC(1) */
224#define PCIC1_IRQ 65
225#define PCIC1_IPR_ADDR INTC_INT2PRI4
226#define PCIC1_IPR_POS 0
227#define PCIC1_PRIORITY 2
228
229/* PCIC(2) */
230#define PCIC2_IRQ 66
231#define PCIC2_IPR_ADDR INTC_INT2PRI5
232#define PCIC2_IPR_POS 3
233#define PCIC2_PRIORITY 2
234
235/* PCIC(3) */
236#define PCIC3_IRQ 67
237#define PCIC3_IPR_ADDR INTC_INT2PRI5
238#define PCIC3_IPR_POS 2
239#define PCIC3_PRIORITY 2
240
241/* PCIC(4) */
242#define PCIC4_IRQ 68
243#define PCIC4_IPR_ADDR INTC_INT2PRI5
244#define PCIC4_IPR_POS 1
245#define PCIC4_PRIORITY 2
246
247/* PCIC(5) */
248#define PCICERR_IRQ 69
249#define PCICPWD3_IRQ 70
250#define PCICPWD2_IRQ 71
251#define PCICPWD1_IRQ 72
252#define PCICPWD0_IRQ 73
253#define PCIC5_IPR_ADDR INTC_INT2PRI5
254#define PCIC5_IPR_POS 0
255#define PCIC5_PRIORITY 2
256
257/* SIOF */
258#define SIOF_IRQ 80
259#define SIOF_IPR_ADDR INTC_INT2PRI6
260#define SIOF_IPR_POS 3
261#define SIOF_PRIORITY 3
262
263/* HSPI */
264#define HSPI_IRQ 84
265#define HSPI_IPR_ADDR INTC_INT2PRI6
266#define HSPI_IPR_POS 2
267#define HSPI_PRIORITY 3
268
269/* MMCIF */
270#define MMCIF_FSTAT_IRQ 88
271#define MMCIF_TRAN_IRQ 89
272#define MMCIF_ERR_IRQ 90
273#define MMCIF_FRDY_IRQ 91
274#define MMCIF_IPR_ADDR INTC_INT2PRI6
275#define MMCIF_IPR_POS 1
276#define HSPI_PRIORITY 3
277
278/* SSI */
279#define SSI_IRQ 100
280#define SSI_IPR_ADDR INTC_INT2PRI6
281#define SSI_IPR_POS 0
282#define SSI_PRIORITY 3
283
284/* FLCTL */
285#define FLCTL_FLSTE_IRQ 104
286#define FLCTL_FLTEND_IRQ 105
287#define FLCTL_FLTRQ0_IRQ 106
288#define FLCTL_FLTRQ1_IRQ 107
289#define FLCTL_IPR_ADDR INTC_INT2PRI7
290#define FLCTL_IPR_POS 3
291#define FLCTL_PRIORITY 3
292
293/* GPIO */
294#define GPIO0_IRQ 108
295#define GPIO1_IRQ 109
296#define GPIO2_IRQ 110
297#define GPIO3_IRQ 111
298#define GPIO_IPR_ADDR INTC_INT2PRI7
299#define GPIO_IPR_POS 2
300#define GPIO_PRIORITY 3
301
302/* ONCHIP_NR_IRQS */
303#define NR_IRQS 150 /* 111 + 16 */
304
305/* In a generic kernel, NR_IRQS is an upper bound, and we should use
306 * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
307 */
308#define ACTUAL_NR_IRQS NR_IRQS
309
310extern void disable_irq(unsigned int);
311extern void disable_irq_nosync(unsigned int);
312extern void enable_irq(unsigned int);
313
314/*
315 * Simple Mask Register Support
316 */
317extern void make_maskreg_irq(unsigned int irq);
318extern unsigned short *irq_mask_register;
319
320/*
321 * Function for "on chip support modules".
322 */
323extern void make_imask_irq(unsigned int irq);
324
325#define INTC_TMU0_MSK 0
326#define INTC_TMU3_MSK 1
327#define INTC_RTC_MSK 2
328#define INTC_SCIF0_MSK 3
329#define INTC_SCIF1_MSK 4
330#define INTC_WDT_MSK 5
331#define INTC_HUID_MSK 7
332#define INTC_DMAC0_MSK 8
333#define INTC_DMAC1_MSK 9
334#define INTC_CMT_MSK 12
335#define INTC_HAC_MSK 13
336#define INTC_PCIC0_MSK 14
337#define INTC_PCIC1_MSK 15
338#define INTC_PCIC2_MSK 16
339#define INTC_PCIC3_MSK 17
340#define INTC_PCIC4_MSK 18
341#define INTC_PCIC5_MSK 19
342#define INTC_SIOF_MSK 20
343#define INTC_HSPI_MSK 21
344#define INTC_MMCIF_MSK 22
345#define INTC_SSI_MSK 23
346#define INTC_FLCTL_MSK 24
347#define INTC_GPIO_MSK 25
348
349#endif /* __ASM_SH_IRQ_SH7780_H */
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index 614a8c13b721..060ec3c27207 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -15,13 +15,20 @@
15#include <asm/machvec.h> 15#include <asm/machvec.h>
16#include <asm/ptrace.h> /* for pt_regs */ 16#include <asm/ptrace.h> /* for pt_regs */
17 17
18#if defined(CONFIG_SH_HP600) || \ 18#if defined(CONFIG_SH_HP6XX) || \
19 defined(CONFIG_SH_RTS7751R2D) || \ 19 defined(CONFIG_SH_RTS7751R2D) || \
20 defined(CONFIG_SH_HS7751RVOIP) || \ 20 defined(CONFIG_SH_HS7751RVOIP) || \
21 defined(CONFIG_SH_SH03) 21 defined(CONFIG_SH_HS7751RVOIP) || \
22 defined(CONFIG_SH_SH03) || \
23 defined(CONFIG_SH_R7780RP) || \
24 defined(CONFIG_SH_LANDISK)
22#include <asm/mach/ide.h> 25#include <asm/mach/ide.h>
23#endif 26#endif
24 27
28#ifndef CONFIG_CPU_SUBTYPE_SH7780
29
30#define INTC_DMAC0_MSK 0
31
25#if defined(CONFIG_CPU_SH3) 32#if defined(CONFIG_CPU_SH3)
26#define INTC_IPRA 0xfffffee2UL 33#define INTC_IPRA 0xfffffee2UL
27#define INTC_IPRB 0xfffffee4UL 34#define INTC_IPRB 0xfffffee4UL
@@ -235,8 +242,9 @@
235#define SCIF1_IPR_ADDR INTC_IPRB 242#define SCIF1_IPR_ADDR INTC_IPRB
236#define SCIF1_IPR_POS 1 243#define SCIF1_IPR_POS 1
237#define SCIF1_PRIORITY 3 244#define SCIF1_PRIORITY 3
238#endif 245#endif /* ST40STB1 */
239#endif 246
247#endif /* 775x / SH4-202 / ST40STB1 */
240 248
241/* NR_IRQS is made from three components: 249/* NR_IRQS is made from three components:
242 * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules 250 * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
@@ -245,37 +253,35 @@
245 */ 253 */
246 254
247/* 1. ONCHIP_NR_IRQS */ 255/* 1. ONCHIP_NR_IRQS */
248#ifdef CONFIG_SH_GENERIC 256#if defined(CONFIG_CPU_SUBTYPE_SH7604)
257# define ONCHIP_NR_IRQS 24 // Actually 21
258#elif defined(CONFIG_CPU_SUBTYPE_SH7707)
259# define ONCHIP_NR_IRQS 64
260# define PINT_NR_IRQS 16
261#elif defined(CONFIG_CPU_SUBTYPE_SH7708)
262# define ONCHIP_NR_IRQS 32
263#elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
264 defined(CONFIG_CPU_SUBTYPE_SH7705)
265# define ONCHIP_NR_IRQS 64 // Actually 61
266# define PINT_NR_IRQS 16
267#elif defined(CONFIG_CPU_SUBTYPE_SH7750)
268# define ONCHIP_NR_IRQS 48 // Actually 44
269#elif defined(CONFIG_CPU_SUBTYPE_SH7751)
270# define ONCHIP_NR_IRQS 72
271#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
272# define ONCHIP_NR_IRQS 112 /* XXX */
273#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
274# define ONCHIP_NR_IRQS 72
275#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
276# define ONCHIP_NR_IRQS 144
277#elif defined(CONFIG_CPU_SUBTYPE_SH7300)
278# define ONCHIP_NR_IRQS 109
279#elif defined(CONFIG_SH_UNKNOWN) /* Most be last */
249# define ONCHIP_NR_IRQS 144 280# define ONCHIP_NR_IRQS 144
250#else
251# if defined(CONFIG_CPU_SUBTYPE_SH7604)
252# define ONCHIP_NR_IRQS 24 // Actually 21
253# elif defined(CONFIG_CPU_SUBTYPE_SH7707)
254# define ONCHIP_NR_IRQS 64
255# define PINT_NR_IRQS 16
256# elif defined(CONFIG_CPU_SUBTYPE_SH7708)
257# define ONCHIP_NR_IRQS 32
258# elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
259 defined(CONFIG_CPU_SUBTYPE_SH7705)
260# define ONCHIP_NR_IRQS 64 // Actually 61
261# define PINT_NR_IRQS 16
262# elif defined(CONFIG_CPU_SUBTYPE_SH7750)
263# define ONCHIP_NR_IRQS 48 // Actually 44
264# elif defined(CONFIG_CPU_SUBTYPE_SH7751)
265# define ONCHIP_NR_IRQS 72
266# elif defined(CONFIG_CPU_SUBTYPE_SH7760)
267# define ONCHIP_NR_IRQS 110
268# elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
269# define ONCHIP_NR_IRQS 72
270# elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
271# define ONCHIP_NR_IRQS 144
272# elif defined(CONFIG_CPU_SUBTYPE_SH7300)
273# define ONCHIP_NR_IRQS 109
274# endif
275#endif 281#endif
276 282
277/* 2. PINT_NR_IRQS */ 283/* 2. PINT_NR_IRQS */
278#ifdef CONFIG_SH_GENERIC 284#ifdef CONFIG_SH_UNKNOWN
279# define PINT_NR_IRQS 16 285# define PINT_NR_IRQS 16
280#else 286#else
281# ifndef PINT_NR_IRQS 287# ifndef PINT_NR_IRQS
@@ -288,22 +294,22 @@
288#endif 294#endif
289 295
290/* 3. OFFCHIP_NR_IRQS */ 296/* 3. OFFCHIP_NR_IRQS */
291#ifdef CONFIG_SH_GENERIC 297#if defined(CONFIG_HD64461)
298# define OFFCHIP_NR_IRQS 18
299#elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
300# define OFFCHIP_NR_IRQS 48
301#elif defined(CONFIG_HD64465)
292# define OFFCHIP_NR_IRQS 16 302# define OFFCHIP_NR_IRQS 16
303#elif defined (CONFIG_SH_EC3104)
304# define OFFCHIP_NR_IRQS 16
305#elif defined (CONFIG_SH_DREAMCAST)
306# define OFFCHIP_NR_IRQS 96
307#elif defined (CONFIG_SH_TITAN)
308# define OFFCHIP_NR_IRQS 4
309#elif defined(CONFIG_SH_UNKNOWN)
310# define OFFCHIP_NR_IRQS 16 /* Must also be last */
293#else 311#else
294# if defined(CONFIG_HD64461) 312# define OFFCHIP_NR_IRQS 0
295# define OFFCHIP_NR_IRQS 18
296# elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
297# define OFFCHIP_NR_IRQS 48
298# elif defined(CONFIG_HD64465)
299# define OFFCHIP_NR_IRQS 16
300# elif defined (CONFIG_SH_EC3104)
301# define OFFCHIP_NR_IRQS 16
302# elif defined (CONFIG_SH_DREAMCAST)
303# define OFFCHIP_NR_IRQS 96
304# else
305# define OFFCHIP_NR_IRQS 0
306# endif
307#endif 313#endif
308 314
309#if OFFCHIP_NR_IRQS > 0 315#if OFFCHIP_NR_IRQS > 0
@@ -313,16 +319,6 @@
313/* NR_IRQS. 1+2+3 */ 319/* NR_IRQS. 1+2+3 */
314#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS) 320#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
315 321
316/* In a generic kernel, NR_IRQS is an upper bound, and we should use
317 * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
318 */
319#ifdef CONFIG_SH_GENERIC
320# define ACTUAL_NR_IRQS (sh_mv.mv_nr_irqs)
321#else
322# define ACTUAL_NR_IRQS NR_IRQS
323#endif
324
325
326extern void disable_irq(unsigned int); 322extern void disable_irq(unsigned int);
327extern void disable_irq_nosync(unsigned int); 323extern void disable_irq_nosync(unsigned int);
328extern void enable_irq(unsigned int); 324extern void enable_irq(unsigned int);
@@ -542,9 +538,6 @@ extern int ipr_irq_demux(int irq);
542 538
543extern int ipr_irq_demux(int irq); 539extern int ipr_irq_demux(int irq);
544#define __irq_demux(irq) ipr_irq_demux(irq) 540#define __irq_demux(irq) ipr_irq_demux(irq)
545
546#else
547#define __irq_demux(irq) irq
548#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */ 541#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
549 542
550#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 543#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
@@ -557,18 +550,35 @@ extern int ipr_irq_demux(int irq);
557#define INTC_ICR_IRLM (1<<7) 550#define INTC_ICR_IRLM (1<<7)
558#endif 551#endif
559 552
560#ifdef CONFIG_CPU_SUBTYPE_ST40STB1 553#else
554#include <asm/irq-sh7780.h>
555#endif
561 556
557/* SH with INTC2-style interrupts */
558#ifdef CONFIG_CPU_HAS_INTC2_IRQ
559#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
560#define INTC2_BASE 0xfe080000
562#define INTC2_FIRST_IRQ 64 561#define INTC2_FIRST_IRQ 64
563#define NR_INTC2_IRQS 25 562#define INTC2_INTREQ_OFFSET 0x20
564 563#define INTC2_INTMSK_OFFSET 0x40
564#define INTC2_INTMSKCLR_OFFSET 0x60
565#define NR_INTC2_IRQS 25
566#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
565#define INTC2_BASE 0xfe080000 567#define INTC2_BASE 0xfe080000
566#define INTC2_INTC2MODE (INTC2_BASE+0x80) 568#define INTC2_FIRST_IRQ 48 /* INTEVT 0x800 */
567
568#define INTC2_INTPRI_OFFSET 0x00
569#define INTC2_INTREQ_OFFSET 0x20 569#define INTC2_INTREQ_OFFSET 0x20
570#define INTC2_INTMSK_OFFSET 0x40 570#define INTC2_INTMSK_OFFSET 0x40
571#define INTC2_INTMSKCLR_OFFSET 0x60 571#define INTC2_INTMSKCLR_OFFSET 0x60
572#define NR_INTC2_IRQS 64
573#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
574#define INTC2_BASE 0xffd40000
575#define INTC2_FIRST_IRQ 22
576#define INTC2_INTMSK_OFFSET (0x38)
577#define INTC2_INTMSKCLR_OFFSET (0x3c)
578#define NR_INTC2_IRQS 60
579#endif
580
581#define INTC2_INTPRI_OFFSET 0x00
572 582
573void make_intc2_irq(unsigned int irq, 583void make_intc2_irq(unsigned int irq,
574 unsigned int ipr_offset, unsigned int ipr_shift, 584 unsigned int ipr_offset, unsigned int ipr_shift,
@@ -577,13 +587,16 @@ void make_intc2_irq(unsigned int irq,
577void init_IRQ_intc2(void); 587void init_IRQ_intc2(void);
578void intc2_add_clear_irq(int irq, int (*fn)(int)); 588void intc2_add_clear_irq(int irq, int (*fn)(int));
579 589
580#endif /* CONFIG_CPU_SUBTYPE_ST40STB1 */ 590#endif
581 591
582static inline int generic_irq_demux(int irq) 592static inline int generic_irq_demux(int irq)
583{ 593{
584 return irq; 594 return irq;
585} 595}
586 596
597#ifndef __irq_demux
598#define __irq_demux(irq) (irq)
599#endif
587#define irq_canonicalize(irq) (irq) 600#define irq_canonicalize(irq) (irq)
588#define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq)) 601#define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq))
589 602
diff --git a/include/asm-sh/kexec.h b/include/asm-sh/kexec.h
new file mode 100644
index 000000000000..9dfe59f6fcb5
--- /dev/null
+++ b/include/asm-sh/kexec.h
@@ -0,0 +1,33 @@
1#ifndef _SH_KEXEC_H
2#define _SH_KEXEC_H
3
4/*
5 * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
6 * I.e. Maximum page that is mapped directly into kernel memory,
7 * and kmap is not required.
8 *
9 * Someone correct me if FIXADDR_START - PAGEOFFSET is not the correct
10 * calculation for the amount of memory directly mappable into the
11 * kernel memory space.
12 */
13
14/* Maximum physical address we can use pages from */
15#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
16/* Maximum address we can reach in physical address mode */
17#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
18/* Maximum address we can use for the control code buffer */
19#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
20
21#define KEXEC_CONTROL_CODE_SIZE 4096
22
23/* The native architecture */
24#define KEXEC_ARCH KEXEC_ARCH_SH
25
26#ifndef __ASSEMBLY__
27
28extern void machine_shutdown(void);
29extern void *crash_notes;
30
31#endif /* __ASSEMBLY__ */
32
33#endif /* _SH_KEXEC_H */
diff --git a/include/asm-sh/machvec.h b/include/asm-sh/machvec.h
index 3f18aa180516..550c50a7359e 100644
--- a/include/asm-sh/machvec.h
+++ b/include/asm-sh/machvec.h
@@ -18,44 +18,37 @@
18#include <asm/machvec_init.h> 18#include <asm/machvec_init.h>
19 19
20struct device; 20struct device;
21struct timeval;
22 21
23struct sh_machine_vector 22struct sh_machine_vector {
24{
25 int mv_nr_irqs; 23 int mv_nr_irqs;
26 24
27 unsigned char (*mv_inb)(unsigned long); 25 u8 (*mv_inb)(unsigned long);
28 unsigned short (*mv_inw)(unsigned long); 26 u16 (*mv_inw)(unsigned long);
29 unsigned int (*mv_inl)(unsigned long); 27 u32 (*mv_inl)(unsigned long);
30 void (*mv_outb)(unsigned char, unsigned long); 28 void (*mv_outb)(u8, unsigned long);
31 void (*mv_outw)(unsigned short, unsigned long); 29 void (*mv_outw)(u16, unsigned long);
32 void (*mv_outl)(unsigned int, unsigned long); 30 void (*mv_outl)(u32, unsigned long);
33 31
34 unsigned char (*mv_inb_p)(unsigned long); 32 u8 (*mv_inb_p)(unsigned long);
35 unsigned short (*mv_inw_p)(unsigned long); 33 u16 (*mv_inw_p)(unsigned long);
36 unsigned int (*mv_inl_p)(unsigned long); 34 u32 (*mv_inl_p)(unsigned long);
37 void (*mv_outb_p)(unsigned char, unsigned long); 35 void (*mv_outb_p)(u8, unsigned long);
38 void (*mv_outw_p)(unsigned short, unsigned long); 36 void (*mv_outw_p)(u16, unsigned long);
39 void (*mv_outl_p)(unsigned int, unsigned long); 37 void (*mv_outl_p)(u32, unsigned long);
40 38
41 void (*mv_insb)(unsigned long port, void *addr, unsigned long count); 39 void (*mv_insb)(unsigned long, void *dst, unsigned long count);
42 void (*mv_insw)(unsigned long port, void *addr, unsigned long count); 40 void (*mv_insw)(unsigned long, void *dst, unsigned long count);
43 void (*mv_insl)(unsigned long port, void *addr, unsigned long count); 41 void (*mv_insl)(unsigned long, void *dst, unsigned long count);
44 void (*mv_outsb)(unsigned long port, const void *addr, unsigned long count); 42 void (*mv_outsb)(unsigned long, const void *src, unsigned long count);
45 void (*mv_outsw)(unsigned long port, const void *addr, unsigned long count); 43 void (*mv_outsw)(unsigned long, const void *src, unsigned long count);
46 void (*mv_outsl)(unsigned long port, const void *addr, unsigned long count); 44 void (*mv_outsl)(unsigned long, const void *src, unsigned long count);
47 45
48 unsigned char (*mv_readb)(unsigned long); 46 u8 (*mv_readb)(void __iomem *);
49 unsigned short (*mv_readw)(unsigned long); 47 u16 (*mv_readw)(void __iomem *);
50 unsigned int (*mv_readl)(unsigned long); 48 u32 (*mv_readl)(void __iomem *);
51 void (*mv_writeb)(unsigned char, unsigned long); 49 void (*mv_writeb)(u8, void __iomem *);
52 void (*mv_writew)(unsigned short, unsigned long); 50 void (*mv_writew)(u16, void __iomem *);
53 void (*mv_writel)(unsigned int, unsigned long); 51 void (*mv_writel)(u32, void __iomem *);
54
55 void* (*mv_ioremap)(unsigned long offset, unsigned long size);
56 void (*mv_iounmap)(void *addr);
57
58 unsigned long (*mv_isa_port2addr)(unsigned long offset);
59 52
60 int (*mv_irq_demux)(int irq); 53 int (*mv_irq_demux)(int irq);
61 54
@@ -66,6 +59,9 @@ struct sh_machine_vector
66 59
67 void *(*mv_consistent_alloc)(struct device *, size_t, dma_addr_t *, gfp_t); 60 void *(*mv_consistent_alloc)(struct device *, size_t, dma_addr_t *, gfp_t);
68 int (*mv_consistent_free)(struct device *, size_t, void *, dma_addr_t); 61 int (*mv_consistent_free)(struct device *, size_t, void *, dma_addr_t);
62
63 void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size);
64 void (*mv_ioport_unmap)(void __iomem *);
69}; 65};
70 66
71extern struct sh_machine_vector sh_mv; 67extern struct sh_machine_vector sh_mv;
diff --git a/include/asm-sh/timer.h b/include/asm-sh/timer.h
new file mode 100644
index 000000000000..dd6579c0b04c
--- /dev/null
+++ b/include/asm-sh/timer.h
@@ -0,0 +1,42 @@
1#ifndef __ASM_SH_TIMER_H
2#define __ASM_SH_TIMER_H
3
4#include <linux/sysdev.h>
5#include <asm/cpu/timer.h>
6
7struct sys_timer_ops {
8 int (*init)(void);
9 unsigned long (*get_offset)(void);
10 unsigned long (*get_frequency)(void);
11};
12
13struct sys_timer {
14 const char *name;
15
16 struct sys_device dev;
17 struct sys_timer_ops *ops;
18};
19
20#define TICK_SIZE (tick_nsec / 1000)
21
22extern struct sys_timer tmu_timer;
23extern struct sys_timer *sys_timer;
24
25static inline unsigned long get_timer_offset(void)
26{
27 return sys_timer->ops->get_offset();
28}
29
30static inline unsigned long get_timer_frequency(void)
31{
32 return sys_timer->ops->get_frequency();
33}
34
35/* arch/sh/kernel/timers/timer.c */
36struct sys_timer *get_sys_timer(void);
37
38/* arch/sh/kernel/time.c */
39void handle_timer_tick(struct pt_regs *);
40
41#endif /* __ASM_SH_TIMER_H */
42
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 18:28:20 -0500