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-rw-r--r--include/asm-sh/system.h173
1 files changed, 41 insertions, 132 deletions
diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h
index 4faa2fb88616..772cd1a0a674 100644
--- a/include/asm-sh/system.h
+++ b/include/asm-sh/system.h
@@ -12,60 +12,9 @@
12#include <asm/types.h> 12#include <asm/types.h>
13#include <asm/ptrace.h> 13#include <asm/ptrace.h>
14 14
15struct task_struct *__switch_to(struct task_struct *prev, 15#define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
16 struct task_struct *next);
17 16
18#define AT_VECTOR_SIZE_ARCH 1 /* entries in ARCH_DLINFO */ 17#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
19/*
20 * switch_to() should switch tasks to task nr n, first
21 */
22
23#define switch_to(prev, next, last) do { \
24 struct task_struct *__last; \
25 register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp; \
26 register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc; \
27 register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev; \
28 register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next; \
29 register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \
30 register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \
31 __asm__ __volatile__ (".balign 4\n\t" \
32 "stc.l gbr, @-r15\n\t" \
33 "sts.l pr, @-r15\n\t" \
34 "mov.l r8, @-r15\n\t" \
35 "mov.l r9, @-r15\n\t" \
36 "mov.l r10, @-r15\n\t" \
37 "mov.l r11, @-r15\n\t" \
38 "mov.l r12, @-r15\n\t" \
39 "mov.l r13, @-r15\n\t" \
40 "mov.l r14, @-r15\n\t" \
41 "mov.l r15, @r1 ! save SP\n\t" \
42 "mov.l @r6, r15 ! change to new stack\n\t" \
43 "mova 1f, %0\n\t" \
44 "mov.l %0, @r2 ! save PC\n\t" \
45 "mov.l 2f, %0\n\t" \
46 "jmp @%0 ! call __switch_to\n\t" \
47 " lds r7, pr ! with return to new PC\n\t" \
48 ".balign 4\n" \
49 "2:\n\t" \
50 ".long __switch_to\n" \
51 "1:\n\t" \
52 "mov.l @r15+, r14\n\t" \
53 "mov.l @r15+, r13\n\t" \
54 "mov.l @r15+, r12\n\t" \
55 "mov.l @r15+, r11\n\t" \
56 "mov.l @r15+, r10\n\t" \
57 "mov.l @r15+, r9\n\t" \
58 "mov.l @r15+, r8\n\t" \
59 "lds.l @r15+, pr\n\t" \
60 "ldc.l @r15+, gbr\n\t" \
61 : "=z" (__last) \
62 : "r" (__ts1), "r" (__ts2), "r" (__ts4), \
63 "r" (__ts5), "r" (__ts6), "r" (__ts7) \
64 : "r3", "t"); \
65 last = __last; \
66} while (0)
67
68#ifdef CONFIG_CPU_SH4A
69#define __icbi() \ 18#define __icbi() \
70{ \ 19{ \
71 unsigned long __addr; \ 20 unsigned long __addr; \
@@ -91,7 +40,7 @@ struct task_struct *__switch_to(struct task_struct *prev,
91 * Historically we have only done this type of barrier for the MMUCR, but 40 * Historically we have only done this type of barrier for the MMUCR, but
92 * it's also necessary for the CCR, so we make it generic here instead. 41 * it's also necessary for the CCR, so we make it generic here instead.
93 */ 42 */
94#ifdef CONFIG_CPU_SH4A 43#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
95#define mb() __asm__ __volatile__ ("synco": : :"memory") 44#define mb() __asm__ __volatile__ ("synco": : :"memory")
96#define rmb() mb() 45#define rmb() mb()
97#define wmb() __asm__ __volatile__ ("synco": : :"memory") 46#define wmb() __asm__ __volatile__ ("synco": : :"memory")
@@ -119,63 +68,11 @@ struct task_struct *__switch_to(struct task_struct *prev,
119 68
120#define set_mb(var, value) do { (void)xchg(&var, value); } while (0) 69#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
121 70
122/* 71#ifdef CONFIG_GUSA_RB
123 * Jump to P2 area. 72#include <asm/cmpxchg-grb.h>
124 * When handling TLB or caches, we need to do it from P2 area. 73#else
125 */ 74#include <asm/cmpxchg-irq.h>
126#define jump_to_P2() \ 75#endif
127do { \
128 unsigned long __dummy; \
129 __asm__ __volatile__( \
130 "mov.l 1f, %0\n\t" \
131 "or %1, %0\n\t" \
132 "jmp @%0\n\t" \
133 " nop\n\t" \
134 ".balign 4\n" \
135 "1: .long 2f\n" \
136 "2:" \
137 : "=&r" (__dummy) \
138 : "r" (0x20000000)); \
139} while (0)
140
141/*
142 * Back to P1 area.
143 */
144#define back_to_P1() \
145do { \
146 unsigned long __dummy; \
147 ctrl_barrier(); \
148 __asm__ __volatile__( \
149 "mov.l 1f, %0\n\t" \
150 "jmp @%0\n\t" \
151 " nop\n\t" \
152 ".balign 4\n" \
153 "1: .long 2f\n" \
154 "2:" \
155 : "=&r" (__dummy)); \
156} while (0)
157
158static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
159{
160 unsigned long flags, retval;
161
162 local_irq_save(flags);
163 retval = *m;
164 *m = val;
165 local_irq_restore(flags);
166 return retval;
167}
168
169static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
170{
171 unsigned long flags, retval;
172
173 local_irq_save(flags);
174 retval = *m;
175 *m = val & 0xff;
176 local_irq_restore(flags);
177 return retval;
178}
179 76
180extern void __xchg_called_with_bad_pointer(void); 77extern void __xchg_called_with_bad_pointer(void);
181 78
@@ -202,20 +99,6 @@ extern void __xchg_called_with_bad_pointer(void);
202#define xchg(ptr,x) \ 99#define xchg(ptr,x) \
203 ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr)))) 100 ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
204 101
205static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
206 unsigned long new)
207{
208 __u32 retval;
209 unsigned long flags;
210
211 local_irq_save(flags);
212 retval = *m;
213 if (retval == old)
214 *m = new;
215 local_irq_restore(flags); /* implies memory barrier */
216 return retval;
217}
218
219/* This function doesn't exist, so you'll get a linker error 102/* This function doesn't exist, so you'll get a linker error
220 * if something tries to do an invalid cmpxchg(). */ 103 * if something tries to do an invalid cmpxchg(). */
221extern void __cmpxchg_called_with_bad_pointer(void); 104extern void __cmpxchg_called_with_bad_pointer(void);
@@ -255,10 +138,14 @@ static inline void *set_exception_table_evt(unsigned int evt, void *handler)
255 */ 138 */
256#ifdef CONFIG_CPU_SH2A 139#ifdef CONFIG_CPU_SH2A
257extern unsigned int instruction_size(unsigned int insn); 140extern unsigned int instruction_size(unsigned int insn);
258#else 141#elif defined(CONFIG_SUPERH32)
259#define instruction_size(insn) (2) 142#define instruction_size(insn) (2)
143#else
144#define instruction_size(insn) (4)
260#endif 145#endif
261 146
147extern unsigned long cached_to_uncached;
148
262/* XXX 149/* XXX
263 * disable hlt during certain critical i/o operations 150 * disable hlt during certain critical i/o operations
264 */ 151 */
@@ -270,13 +157,35 @@ void default_idle(void);
270void per_cpu_trap_init(void); 157void per_cpu_trap_init(void);
271 158
272asmlinkage void break_point_trap(void); 159asmlinkage void break_point_trap(void);
273asmlinkage void debug_trap_handler(unsigned long r4, unsigned long r5, 160
274 unsigned long r6, unsigned long r7, 161#ifdef CONFIG_SUPERH32
275 struct pt_regs __regs); 162#define BUILD_TRAP_HANDLER(name) \
276asmlinkage void bug_trap_handler(unsigned long r4, unsigned long r5, 163asmlinkage void name##_trap_handler(unsigned long r4, unsigned long r5, \
277 unsigned long r6, unsigned long r7, 164 unsigned long r6, unsigned long r7, \
278 struct pt_regs __regs); 165 struct pt_regs __regs)
166
167#define TRAP_HANDLER_DECL \
168 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); \
169 unsigned int vec = regs->tra; \
170 (void)vec;
171#else
172#define BUILD_TRAP_HANDLER(name) \
173asmlinkage void name##_trap_handler(unsigned int vec, struct pt_regs *regs)
174#define TRAP_HANDLER_DECL
175#endif
176
177BUILD_TRAP_HANDLER(address_error);
178BUILD_TRAP_HANDLER(debug);
179BUILD_TRAP_HANDLER(bug);
180BUILD_TRAP_HANDLER(fpu_error);
181BUILD_TRAP_HANDLER(fpu_state_restore);
279 182
280#define arch_align_stack(x) (x) 183#define arch_align_stack(x) (x)
281 184
185#ifdef CONFIG_SUPERH32
186# include "system_32.h"
187#else
188# include "system_64.h"
189#endif
190
282#endif 191#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 00:49:01 -0500