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-rw-r--r--include/asm-sh/overdrive/fpga.h15
-rw-r--r--include/asm-sh/overdrive/gt64111.h109
-rw-r--r--include/asm-sh/overdrive/io.h39
-rw-r--r--include/asm-sh/overdrive/overdrive.h89
4 files changed, 252 insertions, 0 deletions
diff --git a/include/asm-sh/overdrive/fpga.h b/include/asm-sh/overdrive/fpga.h
new file mode 100644
index 000000000000..1cd87992c124
--- /dev/null
+++ b/include/asm-sh/overdrive/fpga.h
@@ -0,0 +1,15 @@
1/*
2 * Copyright (C) 2000 David J. Mckay (david.mckay@st.com)
3 *
4 * May be copied or modified under the terms of the GNU General Public
5 * License. See linux/COPYING for more information.
6 *
7 */
8
9#ifndef __FPGA_OD_H__
10#define __FPGA_OD_H__
11
12/* This routine will program up the fpga which interfaces to the galileo */
13int init_overdrive_fpga(void);
14
15#endif
diff --git a/include/asm-sh/overdrive/gt64111.h b/include/asm-sh/overdrive/gt64111.h
new file mode 100644
index 000000000000..01d58bc13a44
--- /dev/null
+++ b/include/asm-sh/overdrive/gt64111.h
@@ -0,0 +1,109 @@
1#ifndef _GT64111_H_
2#define _GT64111_H_
3
4#define MASTER_INTERFACE 0x0
5#define RAS10_LO_DEC_ADR 0x8
6#define RAS10_HI_DEC_ADR 0x10
7#define RAS32_LO_DEC_ADR 0x18
8#define RAS32_HI_DEC_ADR 0x20
9#define CS20_LO_DEC_ADR 0x28
10#define CS20_HI_DEC_ADR 0x30
11#define CS3_LO_DEC_ADR 0x38
12#define CS3_HI_DEC_ADR 0x40
13#define PCI_IO_LO_DEC_ADR 0x48
14#define PCI_IO_HI_DEC_ADR 0x50
15#define PCI_MEM0_LO_DEC_ADR 0x58
16#define PCI_MEM0_HI_DEC_ADR 0x60
17#define INTERNAL_SPACE_DEC 0x68
18#define BUS_ERR_ADR_LO_CPU 0x70
19#define READONLY0 0x78
20#define PCI_MEM1_LO_DEC_ADR 0x80
21#define PCI_MEM1_HI_DEC_ADR 0x88
22#define RAS0_LO_DEC_ADR 0x400
23#define RAS0_HI_DEC_ADR 0x404
24#define RAS1_LO_DEC_ADR 0x408
25#define RAS1_HI_DEC_ADR 0x40c
26#define RAS2_LO_DEC_ADR 0x410
27#define RAS2_HI_DEC_ADR 0x414
28#define RAS3_LO_DEC_ADR 0x418
29#define RAS3_HI_DEC_ADR 0x41c
30#define DEV_CS0_LO_DEC_ADR 0x420
31#define DEV_CS0_HI_DEC_ADR 0x424
32#define DEV_CS1_LO_DEC_ADR 0x428
33#define DEV_CS1_HI_DEC_ADR 0x42c
34#define DEV_CS2_LO_DEC_ADR 0x430
35#define DEV_CS2_HI_DEC_ADR 0x434
36#define DEV_CS3_LO_DEC_ADR 0x438
37#define DEV_CS3_HI_DEC_ADR 0x43c
38#define DEV_BOOTCS_LO_DEC_ADR 0x440
39#define DEV_BOOTCS_HI_DEC_ADR 0x444
40#define DEV_ADR_DEC_ERR 0x470
41#define DRAM_CFG 0x448
42#define DRAM_BANK0_PARMS 0x44c
43#define DRAM_BANK1_PARMS 0x450
44#define DRAM_BANK2_PARMS 0x454
45#define DRAM_BANK3_PARMS 0x458
46#define DEV_BANK0_PARMS 0x45c
47#define DEV_BANK1_PARMS 0x460
48#define DEV_BANK2_PARMS 0x464
49#define DEV_BANK3_PARMS 0x468
50#define DEV_BOOT_BANK_PARMS 0x46c
51#define CH0_DMA_BYTECOUNT 0x800
52#define CH1_DMA_BYTECOUNT 0x804
53#define CH2_DMA_BYTECOUNT 0x808
54#define CH3_DMA_BYTECOUNT 0x80c
55#define CH0_DMA_SRC_ADR 0x810
56#define CH1_DMA_SRC_ADR 0x814
57#define CH2_DMA_SRC_ADR 0x818
58#define CH3_DMA_SRC_ADR 0x81c
59#define CH0_DMA_DST_ADR 0x820
60#define CH1_DMA_DST_ADR 0x824
61#define CH2_DMA_DST_ADR 0x828
62#define CH3_DMA_DST_ADR 0x82c
63#define CH0_NEXT_REC_PTR 0x830
64#define CH1_NEXT_REC_PTR 0x834
65#define CH2_NEXT_REC_PTR 0x838
66#define CH3_NEXT_REC_PTR 0x83c
67#define CH0_CTRL 0x840
68#define CH1_CTRL 0x844
69#define CH2_CTRL 0x848
70#define CH3_CTRL 0x84c
71#define DMA_ARBITER 0x860
72#define TIMER0 0x850
73#define TIMER1 0x854
74#define TIMER2 0x858
75#define TIMER3 0x85c
76#define TIMER_CTRL 0x864
77#define PCI_CMD 0xc00
78#define PCI_TIMEOUT 0xc04
79#define PCI_RAS10_BANK_SIZE 0xc08
80#define PCI_RAS32_BANK_SIZE 0xc0c
81#define PCI_CS20_BANK_SIZE 0xc10
82#define PCI_CS3_BANK_SIZE 0xc14
83#define PCI_SERRMASK 0xc28
84#define PCI_INTACK 0xc34
85#define PCI_BAR_EN 0xc3c
86#define PCI_CFG_ADR 0xcf8
87#define PCI_CFG_DATA 0xcfc
88#define PCI_INTCAUSE 0xc18
89#define PCI_MAST_MASK 0xc1c
90#define PCI_PCIMASK 0xc24
91#define BAR_ENABLE_ADR 0xc3c
92
93/* These are config registers, accessible via PCI space */
94#define PCI_CONFIG_RAS10_BASE_ADR 0x010
95#define PCI_CONFIG_RAS32_BASE_ADR 0x014
96#define PCI_CONFIG_CS20_BASE_ADR 0x018
97#define PCI_CONFIG_CS3_BASE_ADR 0x01c
98#define PCI_CONFIG_INT_REG_MM_ADR 0x020
99#define PCI_CONFIG_INT_REG_IO_ADR 0x024
100#define PCI_CONFIG_BOARD_VENDOR 0x02c
101#define PCI_CONFIG_ROM_ADR 0x030
102#define PCI_CONFIG_INT_PIN_LINE 0x03c
103
104
105
106
107
108#endif
109
diff --git a/include/asm-sh/overdrive/io.h b/include/asm-sh/overdrive/io.h
new file mode 100644
index 000000000000..0dba700e9643
--- /dev/null
+++ b/include/asm-sh/overdrive/io.h
@@ -0,0 +1,39 @@
1/*
2 * include/asm-sh/io_od.h
3 *
4 * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * IO functions for an STMicroelectronics Overdrive
10 */
11
12#ifndef _ASM_SH_IO_OD_H
13#define _ASM_SH_IO_OD_H
14
15extern unsigned char od_inb(unsigned long port);
16extern unsigned short od_inw(unsigned long port);
17extern unsigned int od_inl(unsigned long port);
18
19extern void od_outb(unsigned char value, unsigned long port);
20extern void od_outw(unsigned short value, unsigned long port);
21extern void od_outl(unsigned int value, unsigned long port);
22
23extern unsigned char od_inb_p(unsigned long port);
24extern unsigned short od_inw_p(unsigned long port);
25extern unsigned int od_inl_p(unsigned long port);
26extern void od_outb_p(unsigned char value, unsigned long port);
27extern void od_outw_p(unsigned short value, unsigned long port);
28extern void od_outl_p(unsigned int value, unsigned long port);
29
30extern void od_insb(unsigned long port, void *addr, unsigned long count);
31extern void od_insw(unsigned long port, void *addr, unsigned long count);
32extern void od_insl(unsigned long port, void *addr, unsigned long count);
33extern void od_outsb(unsigned long port, const void *addr, unsigned long count);
34extern void od_outsw(unsigned long port, const void *addr, unsigned long count);
35extern void od_outsl(unsigned long port, const void *addr, unsigned long count);
36
37extern unsigned long od_isa_port2addr(unsigned long offset);
38
39#endif /* _ASM_SH_IO_OD_H */
diff --git a/include/asm-sh/overdrive/overdrive.h b/include/asm-sh/overdrive/overdrive.h
new file mode 100644
index 000000000000..aa62ae68c55c
--- /dev/null
+++ b/include/asm-sh/overdrive/overdrive.h
@@ -0,0 +1,89 @@
1/*
2 * Copyright (C) 2000 David J. Mckay (david.mckay@st.com)
3 *
4 * May be copied or modified under the terms of the GNU General Public
5 * License. See linux/COPYING for more information.
6 *
7 */
8
9#include <linux/config.h>
10
11#ifndef __OVERDRIVE_H__
12#define __OVERDRIVE_H__
13
14#define OVERDRIVE_INT_CT 0xa3a00000
15#define OVERDRIVE_INT_DT 0xa3b00000
16
17#define OVERDRIVE_CTRL 0xa3000000
18
19/* Shoving all these bits into the same register is not a good idea.
20 * As soon as I get a spare moment, I'll change the FPGA and put each
21 * bit in a separate register
22 */
23
24#define VALID_CTRL_BITS 0x1f
25
26#define ENABLE_RS232_MASK 0x1e
27#define DISABLE_RS232_BIT 0x01
28
29#define ENABLE_NMI_MASK 0x1d
30#define DISABLE_NMI_BIT 0x02
31
32#define RESET_PCI_MASK 0x1b
33#define ENABLE_PCI_BIT 0x04
34
35#define ENABLE_LED_MASK 0x17
36#define DISABLE_LED_BIT 0x08
37
38#define RESET_FPGA_MASK 0x0f
39#define ENABLE_FPGA_BIT 0x10
40
41
42#define FPGA_DCLK_ADDRESS 0xA3C00000
43
44#define FPGA_DATA 0x01 /* W */
45#define FPGA_CONFDONE 0x02 /* R */
46#define FPGA_NOT_STATUS 0x04 /* R */
47#define FPGA_INITDONE 0x08 /* R */
48
49#define FPGA_TIMEOUT 100000
50
51
52/* Interrupts for the overdrive. Note that these numbers have
53 * nothing to do with the actual IRQ numbers they appear on,
54 * this is all programmable. This is simply the position in the
55 * INT_CT register.
56 */
57
58#define OVERDRIVE_PCI_INTA 0
59#define OVERDRIVE_PCI_INTB 1
60#define OVERDRIVE_PCI_INTC 2
61#define OVERDRIVE_PCI_INTD 3
62#define OVERDRIVE_GALILEO_INT 4
63#define OVERDRIVE_GALILEO_LOCAL_INT 5
64#define OVERDRIVE_AUDIO_INT 6
65#define OVERDRIVE_KEYBOARD_INT 7
66
67/* Which Linux IRQ should we assign to each interrupt source? */
68#define OVERDRIVE_PCI_IRQ1 2
69#ifdef CONFIG_HACKED_NE2K
70#define OVERDRIVE_PCI_IRQ2 7
71#else
72#define OVERDRIVE_PCI_IRQ2 2
73#undef OVERDRIVE_PCI_INTB
74#define OVERDRIVE_PCI_INTB OVERDRIVE_PCI_INTA
75
76#endif
77
78/* Put the ESS solo audio chip on IRQ 4 */
79#define OVERDRIVE_ESS_IRQ 4
80
81/* Where the memory behind the PCI bus appears */
82#define PCI_DRAM_BASE 0xb7000000
83#define PCI_DRAM_SIZE (16*1024*1024)
84#define PCI_DRAM_FINISH (PCI_DRAM_BASE+PCI_DRAM_SIZE-1)
85
86/* Where the IO region appears in the memory */
87#define PCI_GTIO_BASE 0xb8000000
88
89#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-24 21:32:37 -0400