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-rw-r--r--include/asm-sh/mpc1211/dma.h304
-rw-r--r--include/asm-sh/mpc1211/io.h22
-rw-r--r--include/asm-sh/mpc1211/keyboard.h64
-rw-r--r--include/asm-sh/mpc1211/m1543c.h200
-rw-r--r--include/asm-sh/mpc1211/mc146818rtc.h6
-rw-r--r--include/asm-sh/mpc1211/mpc1211.h18
-rw-r--r--include/asm-sh/mpc1211/pci.h40
7 files changed, 654 insertions, 0 deletions
diff --git a/include/asm-sh/mpc1211/dma.h b/include/asm-sh/mpc1211/dma.h
new file mode 100644
index 000000000000..0a2fdab3e454
--- /dev/null
+++ b/include/asm-sh/mpc1211/dma.h
@@ -0,0 +1,304 @@
1/* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
3 * Written by Hennus Bergman, 1992.
4 * High DMA channel support & info by Hannu Savolainen
5 * and John Boyd, Nov. 1992.
6 */
7
8#ifndef _ASM_MPC1211_DMA_H
9#define _ASM_MPC1211_DMA_H
10
11#include <linux/config.h>
12#include <linux/spinlock.h> /* And spinlocks */
13#include <asm/io.h> /* need byte IO */
14#include <linux/delay.h>
15
16
17#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
18#define dma_outb outb_p
19#else
20#define dma_outb outb
21#endif
22
23#define dma_inb inb
24
25/*
26 * NOTES about DMA transfers:
27 *
28 * controller 1: channels 0-3, byte operations, ports 00-1F
29 * controller 2: channels 4-7, word operations, ports C0-DF
30 *
31 * - ALL registers are 8 bits only, regardless of transfer size
32 * - channel 4 is not used - cascades 1 into 2.
33 * - channels 0-3 are byte - addresses/counts are for physical bytes
34 * - channels 5-7 are word - addresses/counts are for physical words
35 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
36 * - transfer count loaded to registers is 1 less than actual count
37 * - controller 2 offsets are all even (2x offsets for controller 1)
38 * - page registers for 5-7 don't use data bit 0, represent 128K pages
39 * - page registers for 0-3 use bit 0, represent 64K pages
40 *
41 * DMA transfers are limited to the lower 16MB of _physical_ memory.
42 * Note that addresses loaded into registers must be _physical_ addresses,
43 * not logical addresses (which may differ if paging is active).
44 *
45 * Address mapping for channels 0-3:
46 *
47 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
48 * | ... | | ... | | ... |
49 * | ... | | ... | | ... |
50 * | ... | | ... | | ... |
51 * P7 ... P0 A7 ... A0 A7 ... A0
52 * | Page | Addr MSB | Addr LSB | (DMA registers)
53 *
54 * Address mapping for channels 5-7:
55 *
56 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
57 * | ... | \ \ ... \ \ \ ... \ \
58 * | ... | \ \ ... \ \ \ ... \ (not used)
59 * | ... | \ \ ... \ \ \ ... \
60 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
61 * | Page | Addr MSB | Addr LSB | (DMA registers)
62 *
63 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
64 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
65 * the hardware level, so odd-byte transfers aren't possible).
66 *
67 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
68 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
69 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
70 *
71 */
72
73#define MAX_DMA_CHANNELS 8
74
75/* The maximum address that we can perform a DMA transfer to on this platform */
76#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
77
78/* 8237 DMA controllers */
79#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
80#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
81
82/* DMA controller registers */
83#define DMA1_CMD_REG 0x08 /* command register (w) */
84#define DMA1_STAT_REG 0x08 /* status register (r) */
85#define DMA1_REQ_REG 0x09 /* request register (w) */
86#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
87#define DMA1_MODE_REG 0x0B /* mode register (w) */
88#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
89#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
90#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
91#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
92#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
93
94#define DMA2_CMD_REG 0xD0 /* command register (w) */
95#define DMA2_STAT_REG 0xD0 /* status register (r) */
96#define DMA2_REQ_REG 0xD2 /* request register (w) */
97#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
98#define DMA2_MODE_REG 0xD6 /* mode register (w) */
99#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
100#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
101#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
102#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
103#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
104
105#define DMA_ADDR_0 0x00 /* DMA address registers */
106#define DMA_ADDR_1 0x02
107#define DMA_ADDR_2 0x04
108#define DMA_ADDR_3 0x06
109#define DMA_ADDR_4 0xC0
110#define DMA_ADDR_5 0xC4
111#define DMA_ADDR_6 0xC8
112#define DMA_ADDR_7 0xCC
113
114#define DMA_CNT_0 0x01 /* DMA count registers */
115#define DMA_CNT_1 0x03
116#define DMA_CNT_2 0x05
117#define DMA_CNT_3 0x07
118#define DMA_CNT_4 0xC2
119#define DMA_CNT_5 0xC6
120#define DMA_CNT_6 0xCA
121#define DMA_CNT_7 0xCE
122
123#define DMA_PAGE_0 0x87 /* DMA page registers */
124#define DMA_PAGE_1 0x83
125#define DMA_PAGE_2 0x81
126#define DMA_PAGE_3 0x82
127#define DMA_PAGE_5 0x8B
128#define DMA_PAGE_6 0x89
129#define DMA_PAGE_7 0x8A
130
131#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
132#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
133#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
134
135#define DMA_AUTOINIT 0x10
136
137
138extern spinlock_t dma_spin_lock;
139
140static __inline__ unsigned long claim_dma_lock(void)
141{
142 unsigned long flags;
143 spin_lock_irqsave(&dma_spin_lock, flags);
144 return flags;
145}
146
147static __inline__ void release_dma_lock(unsigned long flags)
148{
149 spin_unlock_irqrestore(&dma_spin_lock, flags);
150}
151
152/* enable/disable a specific DMA channel */
153static __inline__ void enable_dma(unsigned int dmanr)
154{
155 if (dmanr<=3)
156 dma_outb(dmanr, DMA1_MASK_REG);
157 else
158 dma_outb(dmanr & 3, DMA2_MASK_REG);
159}
160
161static __inline__ void disable_dma(unsigned int dmanr)
162{
163 if (dmanr<=3)
164 dma_outb(dmanr | 4, DMA1_MASK_REG);
165 else
166 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
167}
168
169/* Clear the 'DMA Pointer Flip Flop'.
170 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
171 * Use this once to initialize the FF to a known state.
172 * After that, keep track of it. :-)
173 * --- In order to do that, the DMA routines below should ---
174 * --- only be used while holding the DMA lock ! ---
175 */
176static __inline__ void clear_dma_ff(unsigned int dmanr)
177{
178 if (dmanr<=3)
179 dma_outb(0, DMA1_CLEAR_FF_REG);
180 else
181 dma_outb(0, DMA2_CLEAR_FF_REG);
182}
183
184/* set mode (above) for a specific DMA channel */
185static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
186{
187 if (dmanr<=3)
188 dma_outb(mode | dmanr, DMA1_MODE_REG);
189 else
190 dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
191}
192
193/* Set only the page register bits of the transfer address.
194 * This is used for successive transfers when we know the contents of
195 * the lower 16 bits of the DMA current address register, but a 64k boundary
196 * may have been crossed.
197 */
198static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
199{
200 switch(dmanr) {
201 case 0:
202 dma_outb( pagenr & 0xff, DMA_PAGE_0);
203 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_0 + 0x400);
204 break;
205 case 1:
206 dma_outb( pagenr & 0xff, DMA_PAGE_1);
207 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_1 + 0x400);
208 break;
209 case 2:
210 dma_outb( pagenr & 0xff, DMA_PAGE_2);
211 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_2 + 0x400);
212 break;
213 case 3:
214 dma_outb( pagenr & 0xff, DMA_PAGE_3);
215 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_3 + 0x400);
216 break;
217 case 5:
218 dma_outb( pagenr & 0xfe, DMA_PAGE_5);
219 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_5 + 0x400);
220 break;
221 case 6:
222 dma_outb( pagenr & 0xfe, DMA_PAGE_6);
223 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_6 + 0x400);
224 break;
225 case 7:
226 dma_outb( pagenr & 0xfe, DMA_PAGE_7);
227 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_7 + 0x400);
228 break;
229 }
230}
231
232
233/* Set transfer address & page bits for specific DMA channel.
234 * Assumes dma flipflop is clear.
235 */
236static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
237{
238 set_dma_page(dmanr, a>>16);
239 if (dmanr <= 3) {
240 dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
241 dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
242 } else {
243 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
244 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
245 }
246}
247
248
249/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
250 * a specific DMA channel.
251 * You must ensure the parameters are valid.
252 * NOTE: from a manual: "the number of transfers is one more
253 * than the initial word count"! This is taken into account.
254 * Assumes dma flip-flop is clear.
255 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
256 */
257static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
258{
259 count--;
260 if (dmanr <= 3) {
261 dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
262 dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
263 } else {
264 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
265 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
266 }
267}
268
269
270/* Get DMA residue count. After a DMA transfer, this
271 * should return zero. Reading this while a DMA transfer is
272 * still in progress will return unpredictable results.
273 * If called before the channel has been used, it may return 1.
274 * Otherwise, it returns the number of _bytes_ left to transfer.
275 *
276 * Assumes DMA flip-flop is clear.
277 */
278static __inline__ int get_dma_residue(unsigned int dmanr)
279{
280 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
281 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
282
283 /* using short to get 16-bit wrap around */
284 unsigned short count;
285
286 count = 1 + dma_inb(io_port);
287 count += dma_inb(io_port) << 8;
288 return (dmanr<=3)? count : (count<<1);
289}
290
291
292/* These are in kernel/dma.c: */
293extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
294extern void free_dma(unsigned int dmanr); /* release it again */
295
296/* From PCI */
297
298#ifdef CONFIG_PCI
299extern int isa_dma_bridge_buggy;
300#else
301#define isa_dma_bridge_buggy (0)
302#endif
303
304#endif /* _ASM_MPC1211_DMA_H */
diff --git a/include/asm-sh/mpc1211/io.h b/include/asm-sh/mpc1211/io.h
new file mode 100644
index 000000000000..eba8a0b5fd7b
--- /dev/null
+++ b/include/asm-sh/mpc1211/io.h
@@ -0,0 +1,22 @@
1/*
2 * include/asm-sh/io_mpc1211.h
3 *
4 * Copyright 2001 Saito.K & Jeanne
5 *
6 * IO functions for an Interface MPC-1211
7 */
8
9#ifndef _ASM_SH_IO_MPC1211_H
10#define _ASM_SH_IO_MPC1211_H
11
12#include <linux/time.h>
13
14extern int mpc1211_irq_demux(int irq);
15
16extern void init_mpc1211_IRQ(void);
17extern void heartbeat_mpc1211(void);
18
19extern void mpc1211_rtc_gettimeofday(struct timeval *tv);
20extern int mpc1211_rtc_settimeofday(const struct timeval *tv);
21
22#endif /* _ASM_SH_IO_MPC1211_H */
diff --git a/include/asm-sh/mpc1211/keyboard.h b/include/asm-sh/mpc1211/keyboard.h
new file mode 100644
index 000000000000..5f0b9088c796
--- /dev/null
+++ b/include/asm-sh/mpc1211/keyboard.h
@@ -0,0 +1,64 @@
1/*
2 * MPC1211 specific keybord definitions
3 * Taken from the old asm-i386/keybord.h for PC/AT-style definitions
4 * created 3 Nov 1996 by Geert Uytterhoeven.
5 */
6
7#ifdef __KERNEL__
8
9#include <linux/kernel.h>
10#include <linux/ioport.h>
11#include <linux/kd.h>
12#include <linux/pm.h>
13#include <asm/io.h>
14
15#define KEYBOARD_IRQ 1
16#define DISABLE_KBD_DURING_INTERRUPTS 0
17
18extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
19extern int pckbd_getkeycode(unsigned int scancode);
20extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
21 char raw_mode);
22extern char pckbd_unexpected_up(unsigned char keycode);
23extern void pckbd_leds(unsigned char leds);
24extern void pckbd_init_hw(void);
25extern int pckbd_pm_resume(struct pm_dev *, pm_request_t, void *);
26extern pm_callback pm_kbd_request_override;
27extern unsigned char pckbd_sysrq_xlate[128];
28
29#define kbd_setkeycode pckbd_setkeycode
30#define kbd_getkeycode pckbd_getkeycode
31#define kbd_translate pckbd_translate
32#define kbd_unexpected_up pckbd_unexpected_up
33#define kbd_leds pckbd_leds
34#define kbd_init_hw pckbd_init_hw
35#define kbd_sysrq_xlate pckbd_sysrq_xlate
36
37#define SYSRQ_KEY 0x54
38
39/* resource allocation */
40#define kbd_request_region()
41#define kbd_request_irq(handler) request_irq(KEYBOARD_IRQ, handler, 0, \
42 "keyboard", NULL)
43
44/* How to access the keyboard macros on this platform. */
45#define kbd_read_input() inb(KBD_DATA_REG)
46#define kbd_read_status() inb(KBD_STATUS_REG)
47#define kbd_write_output(val) outb(val, KBD_DATA_REG)
48#define kbd_write_command(val) outb(val, KBD_CNTL_REG)
49
50/* Some stoneage hardware needs delays after some operations. */
51#define kbd_pause() do { } while(0)
52
53/*
54 * Machine specific bits for the PS/2 driver
55 */
56
57#define AUX_IRQ 12
58
59#define aux_request_irq(hand, dev_id) \
60 request_irq(AUX_IRQ, hand, SA_SHIRQ, "PS2 Mouse", dev_id)
61
62#define aux_free_irq(dev_id) free_irq(AUX_IRQ, dev_id)
63
64#endif /* __KERNEL__ */
diff --git a/include/asm-sh/mpc1211/m1543c.h b/include/asm-sh/mpc1211/m1543c.h
new file mode 100644
index 000000000000..c95d13236c3b
--- /dev/null
+++ b/include/asm-sh/mpc1211/m1543c.h
@@ -0,0 +1,200 @@
1#ifndef __ASM_SH_M1543C_H
2#define __ASM_SH_M1543C_H
3
4/*
5 * linux/include/asm-sh/m1543c.h
6 * Copyright (C) 2001 Nobuhiro Sakawa
7 * M1543C:PCI-ISA Bus Bridge with Super IO Chip support
8 *
9 * from
10 *
11 * linux/include/asm-sh/smc37c93x.h
12 *
13 * Copyright (C) 2000 Kazumoto Kojima
14 *
15 * SMSC 37C93x Super IO Chip support
16 */
17
18/* Default base I/O address */
19#define FDC_PRIMARY_BASE 0x3f0
20#define IDE1_PRIMARY_BASE 0x1f0
21#define IDE1_SECONDARY_BASE 0x170
22#define PARPORT_PRIMARY_BASE 0x378
23#define COM1_PRIMARY_BASE 0x2f8
24#define COM2_PRIMARY_BASE 0x3f8
25#define COM3_PRIMARY_BASE 0x3e8
26#define RTC_PRIMARY_BASE 0x070
27#define KBC_PRIMARY_BASE 0x060
28#define AUXIO_PRIMARY_BASE 0x000 /* XXX */
29#define I8259_M_CR 0x20
30#define I8259_M_MR 0x21
31#define I8259_S_CR 0xa0
32#define I8259_S_MR 0xa1
33
34/* Logical device number */
35#define LDN_FDC 0
36#define LDN_IDE1 1
37#define LDN_IDE2 2
38#define LDN_PARPORT 3
39#define LDN_COM1 4
40#define LDN_COM2 5
41#define LDN_COM3 11
42#define LDN_RTC 6
43#define LDN_KBC 7
44
45/* Configuration port and key */
46#define CONFIG_PORT 0x3f0
47#define INDEX_PORT CONFIG_PORT
48#define DATA_PORT 0x3f1
49#define CONFIG_ENTER1 0x51
50#define CONFIG_ENTER2 0x23
51#define CONFIG_EXIT 0xbb
52
53/* Configuration index */
54#define CURRENT_LDN_INDEX 0x07
55#define POWER_CONTROL_INDEX 0x22
56#define ACTIVATE_INDEX 0x30
57#define IO_BASE_HI_INDEX 0x60
58#define IO_BASE_LO_INDEX 0x61
59#define IRQ_SELECT_INDEX 0x70
60#define PS2_IRQ_INDEX 0x72
61#define DMA_SELECT_INDEX 0x74
62
63/* UART stuff. Only for debugging. */
64/* UART Register */
65
66#define UART_RBR 0x0 /* Receiver Buffer Register (Read Only) */
67#define UART_THR 0x0 /* Transmitter Holding Register (Write Only) */
68#define UART_IER 0x2 /* Interrupt Enable Register */
69#define UART_IIR 0x4 /* Interrupt Ident Register (Read Only) */
70#define UART_FCR 0x4 /* FIFO Control Register (Write Only) */
71#define UART_LCR 0x6 /* Line Control Register */
72#define UART_MCR 0x8 /* MODEM Control Register */
73#define UART_LSR 0xa /* Line Status Register */
74#define UART_MSR 0xc /* MODEM Status Register */
75#define UART_SCR 0xe /* Scratch Register */
76#define UART_DLL 0x0 /* Divisor Latch (LS) */
77#define UART_DLM 0x2 /* Divisor Latch (MS) */
78
79#ifndef __ASSEMBLY__
80typedef struct uart_reg {
81 volatile __u16 rbr;
82 volatile __u16 ier;
83 volatile __u16 iir;
84 volatile __u16 lcr;
85 volatile __u16 mcr;
86 volatile __u16 lsr;
87 volatile __u16 msr;
88 volatile __u16 scr;
89} uart_reg;
90#endif /* ! __ASSEMBLY__ */
91
92/* Alias for Write Only Register */
93
94#define thr rbr
95#define tcr iir
96
97/* Alias for Divisor Latch Register */
98
99#define dll rbr
100#define dlm ier
101#define fcr iir
102
103/* Interrupt Enable Register */
104
105#define IER_ERDAI 0x0100 /* Enable Received Data Available Interrupt */
106#define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */
107#define IER_ELSI 0x0400 /* Enable Receiver Line Status Interrupt */
108#define IER_EMSI 0x0800 /* Enable MODEM Status Interrupt */
109
110/* Interrupt Ident Register */
111
112#define IIR_IP 0x0100 /* "0" if Interrupt Pending */
113#define IIR_IIB0 0x0200 /* Interrupt ID Bit 0 */
114#define IIR_IIB1 0x0400 /* Interrupt ID Bit 1 */
115#define IIR_IIB2 0x0800 /* Interrupt ID Bit 2 */
116#define IIR_FIFO 0xc000 /* FIFOs enabled */
117
118/* FIFO Control Register */
119
120#define FCR_FEN 0x0100 /* FIFO enable */
121#define FCR_RFRES 0x0200 /* Receiver FIFO reset */
122#define FCR_TFRES 0x0400 /* Transmitter FIFO reset */
123#define FCR_DMA 0x0800 /* DMA mode select */
124#define FCR_RTL 0x4000 /* Receiver triger (LSB) */
125#define FCR_RTM 0x8000 /* Receiver triger (MSB) */
126
127/* Line Control Register */
128
129#define LCR_WLS0 0x0100 /* Word Length Select Bit 0 */
130#define LCR_WLS1 0x0200 /* Word Length Select Bit 1 */
131#define LCR_STB 0x0400 /* Number of Stop Bits */
132#define LCR_PEN 0x0800 /* Parity Enable */
133#define LCR_EPS 0x1000 /* Even Parity Select */
134#define LCR_SP 0x2000 /* Stick Parity */
135#define LCR_SB 0x4000 /* Set Break */
136#define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */
137
138/* MODEM Control Register */
139
140#define MCR_DTR 0x0100 /* Data Terminal Ready */
141#define MCR_RTS 0x0200 /* Request to Send */
142#define MCR_OUT1 0x0400 /* Out 1 */
143#define MCR_IRQEN 0x0800 /* IRQ Enable */
144#define MCR_LOOP 0x1000 /* Loop */
145
146/* Line Status Register */
147
148#define LSR_DR 0x0100 /* Data Ready */
149#define LSR_OE 0x0200 /* Overrun Error */
150#define LSR_PE 0x0400 /* Parity Error */
151#define LSR_FE 0x0800 /* Framing Error */
152#define LSR_BI 0x1000 /* Break Interrupt */
153#define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */
154#define LSR_TEMT 0x4000 /* Transmitter Empty */
155#define LSR_FIFOE 0x8000 /* Receiver FIFO error */
156
157/* MODEM Status Register */
158
159#define MSR_DCTS 0x0100 /* Delta Clear to Send */
160#define MSR_DDSR 0x0200 /* Delta Data Set Ready */
161#define MSR_TERI 0x0400 /* Trailing Edge Ring Indicator */
162#define MSR_DDCD 0x0800 /* Delta Data Carrier Detect */
163#define MSR_CTS 0x1000 /* Clear to Send */
164#define MSR_DSR 0x2000 /* Data Set Ready */
165#define MSR_RI 0x4000 /* Ring Indicator */
166#define MSR_DCD 0x8000 /* Data Carrier Detect */
167
168/* Baud Rate Divisor */
169
170#define UART_CLK (1843200) /* 1.8432 MHz */
171#define UART_BAUD(x) (UART_CLK / (16 * (x)))
172
173/* RTC register definition */
174#define RTC_SECONDS 0
175#define RTC_SECONDS_ALARM 1
176#define RTC_MINUTES 2
177#define RTC_MINUTES_ALARM 3
178#define RTC_HOURS 4
179#define RTC_HOURS_ALARM 5
180#define RTC_DAY_OF_WEEK 6
181#define RTC_DAY_OF_MONTH 7
182#define RTC_MONTH 8
183#define RTC_YEAR 9
184#define RTC_FREQ_SELECT 10
185# define RTC_UIP 0x80
186# define RTC_DIV_CTL 0x70
187/* This RTC can work under 32.768KHz clock only. */
188# define RTC_OSC_ENABLE 0x20
189# define RTC_OSC_DISABLE 0x00
190#define RTC_CONTROL 11
191# define RTC_SET 0x80
192# define RTC_PIE 0x40
193# define RTC_AIE 0x20
194# define RTC_UIE 0x10
195# define RTC_SQWE 0x08
196# define RTC_DM_BINARY 0x04
197# define RTC_24H 0x02
198# define RTC_DST_EN 0x01
199
200#endif /* __ASM_SH_M1543C_H */
diff --git a/include/asm-sh/mpc1211/mc146818rtc.h b/include/asm-sh/mpc1211/mc146818rtc.h
new file mode 100644
index 000000000000..0ec78f66cea4
--- /dev/null
+++ b/include/asm-sh/mpc1211/mc146818rtc.h
@@ -0,0 +1,6 @@
1/*
2 * MPC1211 uses PC/AT style RTC definitions.
3 */
4#include <asm-i386/mc146818rtc.h>
5
6
diff --git a/include/asm-sh/mpc1211/mpc1211.h b/include/asm-sh/mpc1211/mpc1211.h
new file mode 100644
index 000000000000..fa456c3e4e01
--- /dev/null
+++ b/include/asm-sh/mpc1211/mpc1211.h
@@ -0,0 +1,18 @@
1#ifndef __ASM_SH_MPC1211_H
2#define __ASM_SH_MPC1211_H
3
4/*
5 * linux/include/asm-sh/mpc1211.h
6 *
7 * Copyright (C) 2001 Saito.K & Jeanne
8 *
9 * Interface MPC-1211 support
10 */
11
12#define PA_PCI_IO (0xa4000000) /* PCI I/O space */
13#define PA_PCI_MEM (0xb0000000) /* PCI MEM space */
14
15#define PCIPAR (0xa4000cf8) /* PCI Config address */
16#define PCIPDR (0xa4000cfc) /* PCI Config data */
17
18#endif /* __ASM_SH_MPC1211_H */
diff --git a/include/asm-sh/mpc1211/pci.h b/include/asm-sh/mpc1211/pci.h
new file mode 100644
index 000000000000..5d3712c3a701
--- /dev/null
+++ b/include/asm-sh/mpc1211/pci.h
@@ -0,0 +1,40 @@
1/*
2 * Low-Level PCI Support for MPC-1211
3 *
4 * (c) 2002 Saito.K & Jeanne
5 *
6 */
7
8#ifndef _PCI_MPC1211_H_
9#define _PCI_MPC1211_H_
10
11#include <linux/pci.h>
12
13/* set debug level 4=verbose...1=terse */
14//#define DEBUG_PCI 3
15#undef DEBUG_PCI
16
17#ifdef DEBUG_PCI
18#define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); }
19#else
20#define PCIDBG(n, x...)
21#endif
22
23/* startup values */
24#define PCI_PROBE_BIOS 1
25#define PCI_PROBE_CONF1 2
26#define PCI_PROBE_CONF2 4
27#define PCI_NO_SORT 0x100
28#define PCI_BIOS_SORT 0x200
29#define PCI_NO_CHECKS 0x400
30#define PCI_ASSIGN_ROMS 0x1000
31#define PCI_BIOS_IRQ_SCAN 0x2000
32
33/* MPC-1211 Specific Values */
34#define PCIPAR (0xa4000cf8) /* PCI Config address */
35#define PCIPDR (0xa4000cfc) /* PCI Config data */
36
37#define PA_PCI_IO (0xa4000000) /* PCI I/O space */
38#define PA_PCI_MEM (0xb0000000) /* PCI MEM space */
39
40#endif /* _PCI_MPC1211_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-29 13:38:36 -0400