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1/* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
3 * Written by Hennus Bergman, 1992.
4 * High DMA channel support & info by Hannu Savolainen
5 * and John Boyd, Nov. 1992.
6 */
7
8#ifndef _ASM_MPC1211_DMA_H
9#define _ASM_MPC1211_DMA_H
10
11#include <linux/config.h>
12#include <linux/spinlock.h> /* And spinlocks */
13#include <asm/io.h> /* need byte IO */
14#include <linux/delay.h>
15
16
17#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
18#define dma_outb outb_p
19#else
20#define dma_outb outb
21#endif
22
23#define dma_inb inb
24
25/*
26 * NOTES about DMA transfers:
27 *
28 * controller 1: channels 0-3, byte operations, ports 00-1F
29 * controller 2: channels 4-7, word operations, ports C0-DF
30 *
31 * - ALL registers are 8 bits only, regardless of transfer size
32 * - channel 4 is not used - cascades 1 into 2.
33 * - channels 0-3 are byte - addresses/counts are for physical bytes
34 * - channels 5-7 are word - addresses/counts are for physical words
35 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
36 * - transfer count loaded to registers is 1 less than actual count
37 * - controller 2 offsets are all even (2x offsets for controller 1)
38 * - page registers for 5-7 don't use data bit 0, represent 128K pages
39 * - page registers for 0-3 use bit 0, represent 64K pages
40 *
41 * DMA transfers are limited to the lower 16MB of _physical_ memory.
42 * Note that addresses loaded into registers must be _physical_ addresses,
43 * not logical addresses (which may differ if paging is active).
44 *
45 * Address mapping for channels 0-3:
46 *
47 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
48 * | ... | | ... | | ... |
49 * | ... | | ... | | ... |
50 * | ... | | ... | | ... |
51 * P7 ... P0 A7 ... A0 A7 ... A0
52 * | Page | Addr MSB | Addr LSB | (DMA registers)
53 *
54 * Address mapping for channels 5-7:
55 *
56 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
57 * | ... | \ \ ... \ \ \ ... \ \
58 * | ... | \ \ ... \ \ \ ... \ (not used)
59 * | ... | \ \ ... \ \ \ ... \
60 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
61 * | Page | Addr MSB | Addr LSB | (DMA registers)
62 *
63 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
64 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
65 * the hardware level, so odd-byte transfers aren't possible).
66 *
67 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
68 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
69 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
70 *
71 */
72
73#define MAX_DMA_CHANNELS 8
74
75/* The maximum address that we can perform a DMA transfer to on this platform */
76#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
77
78/* 8237 DMA controllers */
79#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
80#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
81
82/* DMA controller registers */
83#define DMA1_CMD_REG 0x08 /* command register (w) */
84#define DMA1_STAT_REG 0x08 /* status register (r) */
85#define DMA1_REQ_REG 0x09 /* request register (w) */
86#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
87#define DMA1_MODE_REG 0x0B /* mode register (w) */
88#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
89#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
90#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
91#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
92#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
93
94#define DMA2_CMD_REG 0xD0 /* command register (w) */
95#define DMA2_STAT_REG 0xD0 /* status register (r) */
96#define DMA2_REQ_REG 0xD2 /* request register (w) */
97#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
98#define DMA2_MODE_REG 0xD6 /* mode register (w) */
99#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
100#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
101#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
102#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
103#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
104
105#define DMA_ADDR_0 0x00 /* DMA address registers */
106#define DMA_ADDR_1 0x02
107#define DMA_ADDR_2 0x04
108#define DMA_ADDR_3 0x06
109#define DMA_ADDR_4 0xC0
110#define DMA_ADDR_5 0xC4
111#define DMA_ADDR_6 0xC8
112#define DMA_ADDR_7 0xCC
113
114#define DMA_CNT_0 0x01 /* DMA count registers */
115#define DMA_CNT_1 0x03
116#define DMA_CNT_2 0x05
117#define DMA_CNT_3 0x07
118#define DMA_CNT_4 0xC2
119#define DMA_CNT_5 0xC6
120#define DMA_CNT_6 0xCA
121#define DMA_CNT_7 0xCE
122
123#define DMA_PAGE_0 0x87 /* DMA page registers */
124#define DMA_PAGE_1 0x83
125#define DMA_PAGE_2 0x81
126#define DMA_PAGE_3 0x82
127#define DMA_PAGE_5 0x8B
128#define DMA_PAGE_6 0x89
129#define DMA_PAGE_7 0x8A
130
131#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
132#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
133#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
134
135#define DMA_AUTOINIT 0x10
136
137
138extern spinlock_t dma_spin_lock;
139
140static __inline__ unsigned long claim_dma_lock(void)
141{
142 unsigned long flags;
143 spin_lock_irqsave(&dma_spin_lock, flags);
144 return flags;
145}
146
147static __inline__ void release_dma_lock(unsigned long flags)
148{
149 spin_unlock_irqrestore(&dma_spin_lock, flags);
150}
151
152/* enable/disable a specific DMA channel */
153static __inline__ void enable_dma(unsigned int dmanr)
154{
155 if (dmanr<=3)
156 dma_outb(dmanr, DMA1_MASK_REG);
157 else
158 dma_outb(dmanr & 3, DMA2_MASK_REG);
159}
160
161static __inline__ void disable_dma(unsigned int dmanr)
162{
163 if (dmanr<=3)
164 dma_outb(dmanr | 4, DMA1_MASK_REG);
165 else
166 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
167}
168
169/* Clear the 'DMA Pointer Flip Flop'.
170 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
171 * Use this once to initialize the FF to a known state.
172 * After that, keep track of it. :-)
173 * --- In order to do that, the DMA routines below should ---
174 * --- only be used while holding the DMA lock ! ---
175 */
176static __inline__ void clear_dma_ff(unsigned int dmanr)
177{
178 if (dmanr<=3)
179 dma_outb(0, DMA1_CLEAR_FF_REG);
180 else
181 dma_outb(0, DMA2_CLEAR_FF_REG);
182}
183
184/* set mode (above) for a specific DMA channel */
185static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
186{
187 if (dmanr<=3)
188 dma_outb(mode | dmanr, DMA1_MODE_REG);
189 else
190 dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
191}
192
193/* Set only the page register bits of the transfer address.
194 * This is used for successive transfers when we know the contents of
195 * the lower 16 bits of the DMA current address register, but a 64k boundary
196 * may have been crossed.
197 */
198static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
199{
200 switch(dmanr) {
201 case 0:
202 dma_outb( pagenr & 0xff, DMA_PAGE_0);
203 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_0 + 0x400);
204 break;
205 case 1:
206 dma_outb( pagenr & 0xff, DMA_PAGE_1);
207 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_1 + 0x400);
208 break;
209 case 2:
210 dma_outb( pagenr & 0xff, DMA_PAGE_2);
211 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_2 + 0x400);
212 break;
213 case 3:
214 dma_outb( pagenr & 0xff, DMA_PAGE_3);
215 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_3 + 0x400);
216 break;
217 case 5:
218 dma_outb( pagenr & 0xfe, DMA_PAGE_5);
219 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_5 + 0x400);
220 break;
221 case 6:
222 dma_outb( pagenr & 0xfe, DMA_PAGE_6);
223 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_6 + 0x400);
224 break;
225 case 7:
226 dma_outb( pagenr & 0xfe, DMA_PAGE_7);
227 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_7 + 0x400);
228 break;
229 }
230}
231
232
233/* Set transfer address & page bits for specific DMA channel.
234 * Assumes dma flipflop is clear.
235 */
236static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
237{
238 set_dma_page(dmanr, a>>16);
239 if (dmanr <= 3) {
240 dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
241 dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
242 } else {
243 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
244 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
245 }
246}
247
248
249/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
250 * a specific DMA channel.
251 * You must ensure the parameters are valid.
252 * NOTE: from a manual: "the number of transfers is one more
253 * than the initial word count"! This is taken into account.
254 * Assumes dma flip-flop is clear.
255 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
256 */
257static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
258{
259 count--;
260 if (dmanr <= 3) {
261 dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
262 dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
263 } else {
264 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
265 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
266 }
267}
268
269
270/* Get DMA residue count. After a DMA transfer, this
271 * should return zero. Reading this while a DMA transfer is
272 * still in progress will return unpredictable results.
273 * If called before the channel has been used, it may return 1.
274 * Otherwise, it returns the number of _bytes_ left to transfer.
275 *
276 * Assumes DMA flip-flop is clear.
277 */
278static __inline__ int get_dma_residue(unsigned int dmanr)
279{
280 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
281 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
282
283 /* using short to get 16-bit wrap around */
284 unsigned short count;
285
286 count = 1 + dma_inb(io_port);
287 count += dma_inb(io_port) << 8;
288 return (dmanr<=3)? count : (count<<1);
289}
290
291
292/* These are in kernel/dma.c: */
293extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
294extern void free_dma(unsigned int dmanr); /* release it again */
295
296/* From PCI */
297
298#ifdef CONFIG_PCI
299extern int isa_dma_bridge_buggy;
300#else
301#define isa_dma_bridge_buggy (0)
302#endif
303
304#endif /* _ASM_MPC1211_DMA_H */
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