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-rw-r--r--include/asm-sh/irq.h70
1 files changed, 70 insertions, 0 deletions
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index 6cd3e9e2a76a..d71326b3c90c 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -14,6 +14,10 @@
14#include <asm/machvec.h> 14#include <asm/machvec.h>
15#include <asm/ptrace.h> /* for pt_regs */ 15#include <asm/ptrace.h> /* for pt_regs */
16 16
17#if defined(CONFIG_CPU_SH2)
18#include <asm/cpu/irq.h>
19#endif
20
17#ifndef CONFIG_CPU_SUBTYPE_SH7780 21#ifndef CONFIG_CPU_SUBTYPE_SH7780
18 22
19#define INTC_DMAC0_MSK 0 23#define INTC_DMAC0_MSK 0
@@ -28,6 +32,31 @@
28#define INTC_IPRD 0xffd00010UL 32#define INTC_IPRD 0xffd00010UL
29#endif 33#endif
30 34
35#if defined(CONFIG_CPU_SUBTYPE_SH7206)
36#ifdef CONFIG_SH_CMT
37#define TIMER_IRQ CMI0_IRQ
38#define TIMER_IPR_ADDR INTC_IPR08
39#define TIMER_IPR_POS 3
40#define TIMER_PRIORITY 2
41
42#define TIMER1_IRQ CMI1_IRQ
43#define TIMER1_IPR_ADDR INTC_IPR08
44#define TIMER1_IPR_POS 2
45#define TIMER1_PRIORITY 2
46#endif
47
48#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
49#define TIMER_IRQ CMI0_IRQ
50#define TIMER_IPR_ADDR INTC_IPRC
51#define TIMER_IPR_POS 1
52#define TIMER_PRIORITY 2
53
54#define TIMER1_IRQ CMI1_IRQ
55#define TIMER1_IPR_ADDR INTC_IPRC
56#define TIMER1_IPR_POS 0
57#define TIMER1_PRIORITY 4
58
59#else
31#define TIMER_IRQ 16 60#define TIMER_IRQ 16
32#define TIMER_IPR_ADDR INTC_IPRA 61#define TIMER_IPR_ADDR INTC_IPRA
33#define TIMER_IPR_POS 3 62#define TIMER_IPR_POS 3
@@ -37,11 +66,14 @@
37#define TIMER1_IPR_ADDR INTC_IPRA 66#define TIMER1_IPR_ADDR INTC_IPRA
38#define TIMER1_IPR_POS 2 67#define TIMER1_IPR_POS 2
39#define TIMER1_PRIORITY 4 68#define TIMER1_PRIORITY 4
69#endif
40 70
71#if !defined(CONFIG_CPU_SH2)
41#define RTC_IRQ 22 72#define RTC_IRQ 22
42#define RTC_IPR_ADDR INTC_IPRA 73#define RTC_IPR_ADDR INTC_IPRA
43#define RTC_IPR_POS 0 74#define RTC_IPR_POS 0
44#define RTC_PRIORITY TIMER_PRIORITY 75#define RTC_PRIORITY TIMER_PRIORITY
76#endif
45 77
46#if defined(CONFIG_CPU_SH3) 78#if defined(CONFIG_CPU_SH3)
47#define DMTE0_IRQ 48 79#define DMTE0_IRQ 48
@@ -265,6 +297,10 @@
265# define ONCHIP_NR_IRQS 109 297# define ONCHIP_NR_IRQS 109
266#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 298#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
267# define ONCHIP_NR_IRQS 111 299# define ONCHIP_NR_IRQS 111
300#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
301# define ONCHIP_NR_IRQS 256
302#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
303# define ONCHIP_NR_IRQS 128
268#elif defined(CONFIG_SH_UNKNOWN) /* Most be last */ 304#elif defined(CONFIG_SH_UNKNOWN) /* Most be last */
269# define ONCHIP_NR_IRQS 144 305# define ONCHIP_NR_IRQS 144
270#endif 306#endif
@@ -322,6 +358,40 @@ extern void enable_irq(unsigned int);
322extern void make_maskreg_irq(unsigned int irq); 358extern void make_maskreg_irq(unsigned int irq);
323extern unsigned short *irq_mask_register; 359extern unsigned short *irq_mask_register;
324 360
361#if defined(CONFIG_CPU_SUBTYPE_SH7619)
362#define IRQ0_IRQ 16
363#define IRQ1_IRQ 17
364#define IRQ2_IRQ 18
365#define IRQ3_IRQ 19
366#define IRQ4_IRQ 32
367#define IRQ5_IRQ 33
368#define IRQ6_IRQ 34
369#define IRQ7_IRQ 35
370#elif !defined(CONFIG_CPU_SUBTYPE_SH7206)
371#define IRQ0_IRQ 32
372#define IRQ1_IRQ 33
373#define IRQ2_IRQ 34
374#define IRQ3_IRQ 35
375#define IRQ4_IRQ 36
376#define IRQ5_IRQ 37
377#endif
378
379#define IRQ0_PRIORITY 1
380#define IRQ1_PRIORITY 1
381#define IRQ2_PRIORITY 1
382#define IRQ3_PRIORITY 1
383#define IRQ4_PRIORITY 1
384#define IRQ5_PRIORITY 1
385
386#ifndef IRQ0_IPR_POS
387#define IRQ0_IPR_POS 0
388#define IRQ1_IPR_POS 1
389#define IRQ2_IPR_POS 2
390#define IRQ3_IPR_POS 3
391#define IRQ4_IPR_POS 0
392#define IRQ5_IPR_POS 1
393#endif
394
325/* 395/*
326 * PINT IRQs 396 * PINT IRQs
327 */ 397 */