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-rw-r--r--include/asm-sh/cpu-sh5/cache.h97
1 files changed, 0 insertions, 97 deletions
diff --git a/include/asm-sh/cpu-sh5/cache.h b/include/asm-sh/cpu-sh5/cache.h
deleted file mode 100644
index ed050ab526f2..000000000000
--- a/include/asm-sh/cpu-sh5/cache.h
+++ /dev/null
@@ -1,97 +0,0 @@
1#ifndef __ASM_SH_CPU_SH5_CACHE_H
2#define __ASM_SH_CPU_SH5_CACHE_H
3
4/*
5 * include/asm-sh/cpu-sh5/cache.h
6 *
7 * Copyright (C) 2000, 2001 Paolo Alberelli
8 * Copyright (C) 2003, 2004 Paul Mundt
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14
15#define L1_CACHE_SHIFT 5
16
17/* Valid and Dirty bits */
18#define SH_CACHE_VALID (1LL<<0)
19#define SH_CACHE_UPDATED (1LL<<57)
20
21/* Unimplemented compat bits.. */
22#define SH_CACHE_COMBINED 0
23#define SH_CACHE_ASSOC 0
24
25/* Cache flags */
26#define SH_CACHE_MODE_WT (1LL<<0)
27#define SH_CACHE_MODE_WB (1LL<<1)
28
29/*
30 * Control Registers.
31 */
32#define ICCR_BASE 0x01600000 /* Instruction Cache Control Register */
33#define ICCR_REG0 0 /* Register 0 offset */
34#define ICCR_REG1 1 /* Register 1 offset */
35#define ICCR0 ICCR_BASE+ICCR_REG0
36#define ICCR1 ICCR_BASE+ICCR_REG1
37
38#define ICCR0_OFF 0x0 /* Set ICACHE off */
39#define ICCR0_ON 0x1 /* Set ICACHE on */
40#define ICCR0_ICI 0x2 /* Invalidate all in IC */
41
42#define ICCR1_NOLOCK 0x0 /* Set No Locking */
43
44#define OCCR_BASE 0x01E00000 /* Operand Cache Control Register */
45#define OCCR_REG0 0 /* Register 0 offset */
46#define OCCR_REG1 1 /* Register 1 offset */
47#define OCCR0 OCCR_BASE+OCCR_REG0
48#define OCCR1 OCCR_BASE+OCCR_REG1
49
50#define OCCR0_OFF 0x0 /* Set OCACHE off */
51#define OCCR0_ON 0x1 /* Set OCACHE on */
52#define OCCR0_OCI 0x2 /* Invalidate all in OC */
53#define OCCR0_WT 0x4 /* Set OCACHE in WT Mode */
54#define OCCR0_WB 0x0 /* Set OCACHE in WB Mode */
55
56#define OCCR1_NOLOCK 0x0 /* Set No Locking */
57
58/*
59 * SH-5
60 * A bit of description here, for neff=32.
61 *
62 * |<--- tag (19 bits) --->|
63 * +-----------------------------+-----------------+------+----------+------+
64 * | | | ways |set index |offset|
65 * +-----------------------------+-----------------+------+----------+------+
66 * ^ 2 bits 8 bits 5 bits
67 * +- Bit 31
68 *
69 * Cacheline size is based on offset: 5 bits = 32 bytes per line
70 * A cache line is identified by a tag + set but OCACHETAG/ICACHETAG
71 * have a broader space for registers. These are outlined by
72 * CACHE_?C_*_STEP below.
73 *
74 */
75
76/* Instruction cache */
77#define CACHE_IC_ADDRESS_ARRAY 0x01000000
78
79/* Operand Cache */
80#define CACHE_OC_ADDRESS_ARRAY 0x01800000
81
82/* These declarations relate to cache 'synonyms' in the operand cache. A
83 'synonym' occurs where effective address bits overlap between those used for
84 indexing the cache sets and those passed to the MMU for translation. In the
85 case of SH5-101 & SH5-103, only bit 12 is affected for 4k pages. */
86
87#define CACHE_OC_N_SYNBITS 1 /* Number of synonym bits */
88#define CACHE_OC_SYN_SHIFT 12
89/* Mask to select synonym bit(s) */
90#define CACHE_OC_SYN_MASK (((1UL<<CACHE_OC_N_SYNBITS)-1)<<CACHE_OC_SYN_SHIFT)
91
92/*
93 * Instruction cache can't be invalidated based on physical addresses.
94 * No Instruction Cache defines required, then.
95 */
96
97#endif /* __ASM_SH_CPU_SH5_CACHE_H */