6 files changed, 62 insertions, 2 deletions

diff --git a/include/asm-sh/cpu-sh4/addrspace.h b/include/asm-sh/cpu-sh4/addrspace.h
index bb2e1b03060c..a3fa733c1c7d 100644
--- a/include/asm-sh/cpu-sh4/addrspace.h
+++ b/include/asm-sh/cpu-sh4/addrspace.h
@@ -10,6 +10,12 @@
 #ifndef __ASM_CPU_SH4_ADDRSPACE_H
 #define __ASM_CPU_SH4_ADDRSPACE_H
 
+#define P0SEG           0x00000000
+#define P1SEG           0x80000000
+#define P2SEG           0xa0000000
+#define P3SEG           0xc0000000
+#define P4SEG           0xe0000000
+
 /* Detailed P4SEG  */
 #define P4SEG_STORE_QUE (P4SEG)
 #define P4SEG_IC_ADDR   0xf0000000
diff --git a/include/asm-sh/cpu-sh4/cache.h b/include/asm-sh/cpu-sh4/cache.h
index f92b20a0983d..1c61ebf5c8e3 100644
--- a/include/asm-sh/cpu-sh4/cache.h
+++ b/include/asm-sh/cpu-sh4/cache.h
@@ -12,6 +12,11 @@
 
 #define L1_CACHE_SHIFT  5
 
+#define SH_CACHE_VALID          1
+#define SH_CACHE_UPDATED        2
+#define SH_CACHE_COMBINED       4
+#define SH_CACHE_ASSOC          8
+
 #define CCR             0xff00001c      /* Address of Cache Control Register */
 #define CCR_CACHE_OCE   0x0001  /* Operand Cache Enable */
 #define CCR_CACHE_WT    0x0002  /* Write-Through (for P0,U0,P3) (else writeback)*/
diff --git a/include/asm-sh/cpu-sh4/fpu.h b/include/asm-sh/cpu-sh4/fpu.h
new file mode 100644
index 000000000000..febef7342528
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/fpu.h
@@ -0,0 +1,32 @@
+/*
+ * linux/arch/sh/kernel/cpu/sh4/sh4_fpu.h
+ *
+ * Copyright (C) 2006 STMicroelectronics Limited
+ * Author: Carl Shaw <carl.shaw@st.com>
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License Version 2.  See linux/COPYING for more information.
+ *
+ * Definitions for SH4 FPU operations
+ */
+
+#ifndef __CPU_SH4_FPU_H
+#define __CPU_SH4_FPU_H
+
+#define FPSCR_ENABLE_MASK       0x00000f80UL
+
+#define FPSCR_FMOV_DOUBLE       (1<<1)
+
+#define FPSCR_CAUSE_INEXACT     (1<<12)
+#define FPSCR_CAUSE_UNDERFLOW   (1<<13)
+#define FPSCR_CAUSE_OVERFLOW    (1<<14)
+#define FPSCR_CAUSE_DIVZERO     (1<<15)
+#define FPSCR_CAUSE_INVALID     (1<<16)
+#define FPSCR_CAUSE_ERROR       (1<<17)
+
+#define FPSCR_DBL_PRECISION     (1<<19)
+#define FPSCR_ROUNDING_MODE(x)  ((x >> 20) & 3)
+#define FPSCR_RM_NEAREST        (0)
+#define FPSCR_RM_ZERO           (1)
+
+#endif
diff --git a/include/asm-sh/cpu-sh4/freq.h b/include/asm-sh/cpu-sh4/freq.h
index dc1d32a86374..1ac10b9a078f 100644
--- a/include/asm-sh/cpu-sh4/freq.h
+++ b/include/asm-sh/cpu-sh4/freq.h
@@ -16,7 +16,8 @@
 #define SCLKACR                 0xa4150008
 #define SCLKBCR                 0xa415000c
 #define IrDACLKCR               0xa4150010
-#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
+      defined(CONFIG_CPU_SUBTYPE_SH7780)
 #define FRQCR                   0xffc80000
 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
 #define FRQCR0                  0xffc80000
diff --git a/include/asm-sh/cpu-sh4/mmu_context.h b/include/asm-sh/cpu-sh4/mmu_context.h
index 979acddc0f8e..9ea8eb27b18e 100644
--- a/include/asm-sh/cpu-sh4/mmu_context.h
+++ b/include/asm-sh/cpu-sh4/mmu_context.h
@@ -22,12 +22,20 @@
 #define MMU_UTLB_ADDRESS_ARRAY  0xF6000000
 #define MMU_PAGE_ASSOC_BIT      0x80
 
+#define MMUCR_TI                (1<<2)
+
 #ifdef CONFIG_X2TLB
 #define MMUCR_ME                (1 << 7)
 #else
 #define MMUCR_ME                (0)
 #endif
 
+#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40)
+#define MMUCR_SE                (1 << 4)
+#else
+#define MMUCR_SE                (0)
+#endif
+
 #ifdef CONFIG_SH_STORE_QUEUES
 #define MMUCR_SQMD              (1 << 9)
 #else
@@ -35,7 +43,7 @@
 #endif
 
 #define MMU_NTLB_ENTRIES        64
-#define MMU_CONTROL_INIT        (0x05|MMUCR_SQMD|MMUCR_ME)
+#define MMU_CONTROL_INIT        (0x05|MMUCR_SQMD|MMUCR_ME|MMUCR_SE)
 
 #define MMU_ITLB_DATA_ARRAY     0xF3000000
 #define MMU_UTLB_DATA_ARRAY     0xF7000000
diff --git a/include/asm-sh/cpu-sh4/rtc.h b/include/asm-sh/cpu-sh4/rtc.h
new file mode 100644
index 000000000000..f3d0f53275e4
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/rtc.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_SH_CPU_SH4_RTC_H
+#define __ASM_SH_CPU_SH4_RTC_H
+
+#define rtc_reg_size            sizeof(u32)
+#define RTC_BIT_INVERTED        0x40    /* bug on SH7750, SH7750S */
+#define RTC_DEF_CAPABILITIES    RTC_CAP_4_DIGIT_YEAR
+
+#endif /* __ASM_SH_CPU_SH4_RTC_H */