diff options
Diffstat (limited to 'include/asm-sh/cpu-sh4/mmu_context.h')
| -rw-r--r-- | include/asm-sh/cpu-sh4/mmu_context.h | 63 |
1 files changed, 0 insertions, 63 deletions
diff --git a/include/asm-sh/cpu-sh4/mmu_context.h b/include/asm-sh/cpu-sh4/mmu_context.h deleted file mode 100644 index 9ea8eb27b18e..000000000000 --- a/include/asm-sh/cpu-sh4/mmu_context.h +++ /dev/null | |||
| @@ -1,63 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-sh/cpu-sh4/mmu_context.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 Niibe Yutaka | ||
| 5 | * | ||
| 6 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | * License. See the file "COPYING" in the main directory of this archive | ||
| 8 | * for more details. | ||
| 9 | */ | ||
| 10 | #ifndef __ASM_CPU_SH4_MMU_CONTEXT_H | ||
| 11 | #define __ASM_CPU_SH4_MMU_CONTEXT_H | ||
| 12 | |||
| 13 | #define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */ | ||
| 14 | #define MMU_PTEL 0xFF000004 /* Page table entry register LOW */ | ||
| 15 | #define MMU_TTB 0xFF000008 /* Translation table base register */ | ||
| 16 | #define MMU_TEA 0xFF00000C /* TLB Exception Address */ | ||
| 17 | #define MMU_PTEA 0xFF000034 /* Page table entry assistance register */ | ||
| 18 | |||
| 19 | #define MMUCR 0xFF000010 /* MMU Control Register */ | ||
| 20 | |||
| 21 | #define MMU_ITLB_ADDRESS_ARRAY 0xF2000000 | ||
| 22 | #define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 | ||
| 23 | #define MMU_PAGE_ASSOC_BIT 0x80 | ||
| 24 | |||
| 25 | #define MMUCR_TI (1<<2) | ||
| 26 | |||
| 27 | #ifdef CONFIG_X2TLB | ||
| 28 | #define MMUCR_ME (1 << 7) | ||
| 29 | #else | ||
| 30 | #define MMUCR_ME (0) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40) | ||
| 34 | #define MMUCR_SE (1 << 4) | ||
| 35 | #else | ||
| 36 | #define MMUCR_SE (0) | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifdef CONFIG_SH_STORE_QUEUES | ||
| 40 | #define MMUCR_SQMD (1 << 9) | ||
| 41 | #else | ||
| 42 | #define MMUCR_SQMD (0) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #define MMU_NTLB_ENTRIES 64 | ||
| 46 | #define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME|MMUCR_SE) | ||
| 47 | |||
| 48 | #define MMU_ITLB_DATA_ARRAY 0xF3000000 | ||
| 49 | #define MMU_UTLB_DATA_ARRAY 0xF7000000 | ||
| 50 | |||
| 51 | #define MMU_UTLB_ENTRIES 64 | ||
| 52 | #define MMU_U_ENTRY_SHIFT 8 | ||
| 53 | #define MMU_UTLB_VALID 0x100 | ||
| 54 | #define MMU_ITLB_ENTRIES 4 | ||
| 55 | #define MMU_I_ENTRY_SHIFT 8 | ||
| 56 | #define MMU_ITLB_VALID 0x100 | ||
| 57 | |||
| 58 | #define TRA 0xff000020 | ||
| 59 | #define EXPEVT 0xff000024 | ||
| 60 | #define INTEVT 0xff000028 | ||
| 61 | |||
| 62 | #endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */ | ||
| 63 | |||