diff options
Diffstat (limited to 'include/asm-sh/cpu-sh4/dma.h')
| -rw-r--r-- | include/asm-sh/cpu-sh4/dma.h | 52 |
1 files changed, 42 insertions, 10 deletions
diff --git a/include/asm-sh/cpu-sh4/dma.h b/include/asm-sh/cpu-sh4/dma.h index e2b91adf821a..0dfe61f14802 100644 --- a/include/asm-sh/cpu-sh4/dma.h +++ b/include/asm-sh/cpu-sh4/dma.h | |||
| @@ -1,17 +1,49 @@ | |||
| 1 | #ifndef __ASM_CPU_SH4_DMA_H | 1 | #ifndef __ASM_CPU_SH4_DMA_H |
| 2 | #define __ASM_CPU_SH4_DMA_H | 2 | #define __ASM_CPU_SH4_DMA_H |
| 3 | 3 | ||
| 4 | #ifdef CONFIG_CPU_SH4A | ||
| 5 | #define SH_DMAC_BASE 0xfc808020 | ||
| 6 | #else | ||
| 4 | #define SH_DMAC_BASE 0xffa00000 | 7 | #define SH_DMAC_BASE 0xffa00000 |
| 8 | #endif | ||
| 5 | 9 | ||
| 6 | #define SAR ((unsigned long[]){SH_DMAC_BASE + 0x00, SH_DMAC_BASE + 0x10, \ | 10 | /* Definitions for the SuperH DMAC */ |
| 7 | SH_DMAC_BASE + 0x20, SH_DMAC_BASE + 0x30}) | 11 | #define TM_BURST 0x0000080 |
| 8 | #define DAR ((unsigned long[]){SH_DMAC_BASE + 0x04, SH_DMAC_BASE + 0x14, \ | 12 | #define TS_8 0x00000010 |
| 9 | SH_DMAC_BASE + 0x24, SH_DMAC_BASE + 0x34}) | 13 | #define TS_16 0x00000020 |
| 10 | #define DMATCR ((unsigned long[]){SH_DMAC_BASE + 0x08, SH_DMAC_BASE + 0x18, \ | 14 | #define TS_32 0x00000030 |
| 11 | SH_DMAC_BASE + 0x28, SH_DMAC_BASE + 0x38}) | 15 | #define TS_64 0x00000000 |
| 12 | #define CHCR ((unsigned long[]){SH_DMAC_BASE + 0x0c, SH_DMAC_BASE + 0x1c, \ | ||
| 13 | SH_DMAC_BASE + 0x2c, SH_DMAC_BASE + 0x3c}) | ||
| 14 | #define DMAOR (SH_DMAC_BASE + 0x40) | ||
| 15 | 16 | ||
| 16 | #endif /* __ASM_CPU_SH4_DMA_H */ | 17 | #define CHCR_TS_MASK 0x30 |
| 18 | #define CHCR_TS_SHIFT 4 | ||
| 19 | |||
| 20 | #define DMAOR_COD 0x00000008 | ||
| 21 | |||
| 22 | #define DMAOR_INIT ( 0x8000 | DMAOR_DME ) | ||
| 17 | 23 | ||
| 24 | /* | ||
| 25 | * The SuperH DMAC supports a number of transmit sizes, we list them here, | ||
| 26 | * with their respective values as they appear in the CHCR registers. | ||
| 27 | * | ||
| 28 | * Defaults to a 64-bit transfer size. | ||
| 29 | */ | ||
| 30 | enum { | ||
| 31 | XMIT_SZ_64BIT, | ||
| 32 | XMIT_SZ_8BIT, | ||
| 33 | XMIT_SZ_16BIT, | ||
| 34 | XMIT_SZ_32BIT, | ||
| 35 | XMIT_SZ_256BIT, | ||
| 36 | }; | ||
| 37 | |||
| 38 | /* | ||
| 39 | * The DMA count is defined as the number of bytes to transfer. | ||
| 40 | */ | ||
| 41 | static unsigned int ts_shift[] __attribute__ ((used)) = { | ||
| 42 | [XMIT_SZ_64BIT] = 3, | ||
| 43 | [XMIT_SZ_8BIT] = 0, | ||
| 44 | [XMIT_SZ_16BIT] = 1, | ||
| 45 | [XMIT_SZ_32BIT] = 2, | ||
| 46 | [XMIT_SZ_256BIT] = 5, | ||
| 47 | }; | ||
| 48 | |||
| 49 | #endif /* __ASM_CPU_SH4_DMA_H */ | ||
